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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / ixgbe / ixgbe_82599.c
blobe8c34cbebe4e1edd021527fe7659ccf2798ac5d5
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
35
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41
42 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
43 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg,
52 bool autoneg_wait_to_complete);
53 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete);
55 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
56 ixgbe_link_speed speed,
57 bool autoneg,
58 bool autoneg_wait_to_complete);
59 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed *speed,
61 bool *autoneg);
62 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
63 ixgbe_link_speed speed,
64 bool autoneg,
65 bool autoneg_wait_to_complete);
66 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
67
68 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
69 {
70 struct ixgbe_mac_info *mac = &hw->mac;
71 if (hw->phy.multispeed_fiber) {
72 /* Set up dual speed SFP+ support */
73 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
74 mac->ops.disable_tx_laser =
75 &ixgbe_disable_tx_laser_multispeed_fiber;
76 mac->ops.enable_tx_laser =
77 &ixgbe_enable_tx_laser_multispeed_fiber;
78 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
79 } else {
80 mac->ops.disable_tx_laser = NULL;
81 mac->ops.enable_tx_laser = NULL;
82 mac->ops.flap_tx_laser = NULL;
83 if ((mac->ops.get_media_type(hw) ==
84 ixgbe_media_type_backplane) &&
85 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
86 hw->phy.smart_speed == ixgbe_smart_speed_on))
87 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
88 else
89 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
90 }
91 }
92
93 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
94 {
95 s32 ret_val = 0;
96 u16 list_offset, data_offset, data_value;
97
98 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
99 ixgbe_init_mac_link_ops_82599(hw);
100
101 hw->phy.ops.reset = NULL;
102
103 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
104 &data_offset);
105
106 if (ret_val != 0)
107 goto setup_sfp_out;
108
109 /* PHY config will finish before releasing the semaphore */
110 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
111 if (ret_val != 0) {
112 ret_val = IXGBE_ERR_SWFW_SYNC;
113 goto setup_sfp_out;
114 }
115
116 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
117 while (data_value != 0xffff) {
118 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
119 IXGBE_WRITE_FLUSH(hw);
120 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
121 }
122 /* Now restart DSP by setting Restart_AN */
123 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
124 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
125
126 /* Release the semaphore */
127 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
128 /* Delay obtaining semaphore again to allow FW access */
129 msleep(hw->eeprom.semaphore_delay);
130 }
131
132 setup_sfp_out:
133 return ret_val;
134 }
135
136 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
137 {
138 struct ixgbe_mac_info *mac = &hw->mac;
139
140 ixgbe_init_mac_link_ops_82599(hw);
141
142 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
143 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
144 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
145 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
146 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
147 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
148
149 return 0;
150 }
151
152 /**
153 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
154 * @hw: pointer to hardware structure
155 *
156 * Initialize any function pointers that were not able to be
157 * set during get_invariants because the PHY/SFP type was
158 * not known. Perform the SFP init if necessary.
159 *
160 **/
161 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
162 {
163 struct ixgbe_mac_info *mac = &hw->mac;
164 struct ixgbe_phy_info *phy = &hw->phy;
165 s32 ret_val = 0;
166
167 /* Identify the PHY or SFP module */
168 ret_val = phy->ops.identify(hw);
169
170 /* Setup function pointers based on detected SFP module and speeds */
171 ixgbe_init_mac_link_ops_82599(hw);
172
173 /* If copper media, overwrite with copper function pointers */
174 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
175 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
176 mac->ops.get_link_capabilities =
177 &ixgbe_get_copper_link_capabilities_82599;
178 }
179
180 /* Set necessary function pointers based on phy type */
181 switch (hw->phy.type) {
182 case ixgbe_phy_tn:
183 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
184 phy->ops.get_firmware_version =
185 &ixgbe_get_phy_firmware_version_tnx;
186 break;
187 default:
188 break;
189 }
190
191 return ret_val;
192 }
193
194 /**
195 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
196 * @hw: pointer to hardware structure
197 * @speed: pointer to link speed
198 * @negotiation: true when autoneg or autotry is enabled
199 *
200 * Determines the link capabilities by reading the AUTOC register.
201 **/
202 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
203 ixgbe_link_speed *speed,
204 bool *negotiation)
205 {
206 s32 status = 0;
207 u32 autoc = 0;
208
209 /* Determine 1G link capabilities off of SFP+ type */
210 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
211 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
212 *speed = IXGBE_LINK_SPEED_1GB_FULL;
213 *negotiation = true;
214 goto out;
215 }
216
217 /*
218 * Determine link capabilities based on the stored value of AUTOC,
219 * which represents EEPROM defaults. If AUTOC value has not been
220 * stored, use the current register value.
221 */
222 if (hw->mac.orig_link_settings_stored)
223 autoc = hw->mac.orig_autoc;
224 else
225 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
226
227 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
228 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
229 *speed = IXGBE_LINK_SPEED_1GB_FULL;
230 *negotiation = false;
231 break;
232
233 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
234 *speed = IXGBE_LINK_SPEED_10GB_FULL;
235 *negotiation = false;
236 break;
237
238 case IXGBE_AUTOC_LMS_1G_AN:
239 *speed = IXGBE_LINK_SPEED_1GB_FULL;
240 *negotiation = true;
241 break;
242
243 case IXGBE_AUTOC_LMS_10G_SERIAL:
244 *speed = IXGBE_LINK_SPEED_10GB_FULL;
245 *negotiation = false;
246 break;
247
248 case IXGBE_AUTOC_LMS_KX4_KX_KR:
249 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
250 *speed = IXGBE_LINK_SPEED_UNKNOWN;
251 if (autoc & IXGBE_AUTOC_KR_SUPP)
252 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
253 if (autoc & IXGBE_AUTOC_KX4_SUPP)
254 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
255 if (autoc & IXGBE_AUTOC_KX_SUPP)
256 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
257 *negotiation = true;
258 break;
259
260 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
261 *speed = IXGBE_LINK_SPEED_100_FULL;
262 if (autoc & IXGBE_AUTOC_KR_SUPP)
263 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
264 if (autoc & IXGBE_AUTOC_KX4_SUPP)
265 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
266 if (autoc & IXGBE_AUTOC_KX_SUPP)
267 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
268 *negotiation = true;
269 break;
270
271 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
272 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
273 *negotiation = false;
274 break;
275
276 default:
277 status = IXGBE_ERR_LINK_SETUP;
278 goto out;
279 break;
280 }
281
282 if (hw->phy.multispeed_fiber) {
283 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
284 IXGBE_LINK_SPEED_1GB_FULL;
285 *negotiation = true;
286 }
287
288 out:
289 return status;
290 }
291
292 /**
293 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
294 * @hw: pointer to hardware structure
295 * @speed: pointer to link speed
296 * @autoneg: boolean auto-negotiation value
297 *
298 * Determines the link capabilities by reading the AUTOC register.
299 **/
300 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
301 ixgbe_link_speed *speed,
302 bool *autoneg)
303 {
304 s32 status = IXGBE_ERR_LINK_SETUP;
305 u16 speed_ability;
306
307 *speed = 0;
308 *autoneg = true;
309
310 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
311 &speed_ability);
312
313 if (status == 0) {
314 if (speed_ability & MDIO_SPEED_10G)
315 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
316 if (speed_ability & MDIO_PMA_SPEED_1000)
317 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
318 }
319
320 return status;
321 }
322
323 /**
324 * ixgbe_get_media_type_82599 - Get media type
325 * @hw: pointer to hardware structure
326 *
327 * Returns the media type (fiber, copper, backplane)
328 **/
329 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
330 {
331 enum ixgbe_media_type media_type;
332
333 /* Detect if there is a copper PHY attached. */
334 if (hw->phy.type == ixgbe_phy_cu_unknown ||
335 hw->phy.type == ixgbe_phy_tn) {
336 media_type = ixgbe_media_type_copper;
337 goto out;
338 }
339
340 switch (hw->device_id) {
341 case IXGBE_DEV_ID_82599_KX4:
342 case IXGBE_DEV_ID_82599_KX4_MEZZ:
343 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
344 case IXGBE_DEV_ID_82599_KR:
345 case IXGBE_DEV_ID_82599_XAUI_LOM:
346 /* Default device ID is mezzanine card KX/KX4 */
347 media_type = ixgbe_media_type_backplane;
348 break;
349 case IXGBE_DEV_ID_82599_SFP:
350 case IXGBE_DEV_ID_82599_SFP_EM:
351 media_type = ixgbe_media_type_fiber;
352 break;
353 case IXGBE_DEV_ID_82599_CX4:
354 media_type = ixgbe_media_type_cx4;
355 break;
356 default:
357 media_type = ixgbe_media_type_unknown;
358 break;
359 }
360 out:
361 return media_type;
362 }
363
364 /**
365 * ixgbe_start_mac_link_82599 - Setup MAC link settings
366 * @hw: pointer to hardware structure
367 * @autoneg_wait_to_complete: true when waiting for completion is needed
368 *
369 * Configures link settings based on values in the ixgbe_hw struct.
370 * Restarts the link. Performs autonegotiation if needed.
371 **/
372 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
373 bool autoneg_wait_to_complete)
374 {
375 u32 autoc_reg;
376 u32 links_reg;
377 u32 i;
378 s32 status = 0;
379
380 /* Restart link */
381 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
382 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
383 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
384
385 /* Only poll for autoneg to complete if specified to do so */
386 if (autoneg_wait_to_complete) {
387 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
388 IXGBE_AUTOC_LMS_KX4_KX_KR ||
389 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
390 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
391 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
392 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
393 links_reg = 0; /* Just in case Autoneg time = 0 */
394 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
395 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
396 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
397 break;
398 msleep(100);
399 }
400 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
401 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
402 hw_dbg(hw, "Autoneg did not complete.\n");
403 }
404 }
405 }
406
407 /* Add delay to filter out noises during initial link setup */
408 msleep(50);
409
410 return status;
411 }
412
413 /**
414 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
415 * @hw: pointer to hardware structure
416 *
417 * The base drivers may require better control over SFP+ module
418 * PHY states. This includes selectively shutting down the Tx
419 * laser on the PHY, effectively halting physical link.
420 **/
421 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
422 {
423 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
424
425 /* Disable tx laser; allow 100us to go dark per spec */
426 esdp_reg |= IXGBE_ESDP_SDP3;
427 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
428 IXGBE_WRITE_FLUSH(hw);
429 udelay(100);
430 }
431
432 /**
433 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
434 * @hw: pointer to hardware structure
435 *
436 * The base drivers may require better control over SFP+ module
437 * PHY states. This includes selectively turning on the Tx
438 * laser on the PHY, effectively starting physical link.
439 **/
440 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
441 {
442 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
443
444 /* Enable tx laser; allow 100ms to light up */
445 esdp_reg &= ~IXGBE_ESDP_SDP3;
446 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
447 IXGBE_WRITE_FLUSH(hw);
448 msleep(100);
449 }
450
451 /**
452 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
453 * @hw: pointer to hardware structure
454 *
455 * When the driver changes the link speeds that it can support,
456 * it sets autotry_restart to true to indicate that we need to
457 * initiate a new autotry session with the link partner. To do
458 * so, we set the speed then disable and re-enable the tx laser, to
459 * alert the link partner that it also needs to restart autotry on its
460 * end. This is consistent with true clause 37 autoneg, which also
461 * involves a loss of signal.
462 **/
463 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
464 {
465 hw_dbg(hw, "ixgbe_flap_tx_laser_multispeed_fiber\n");
466
467 if (hw->mac.autotry_restart) {
468 ixgbe_disable_tx_laser_multispeed_fiber(hw);
469 ixgbe_enable_tx_laser_multispeed_fiber(hw);
470 hw->mac.autotry_restart = false;
471 }
472 }
473
474 /**
475 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
476 * @hw: pointer to hardware structure
477 * @speed: new link speed
478 * @autoneg: true if autonegotiation enabled
479 * @autoneg_wait_to_complete: true when waiting for completion is needed
480 *
481 * Set the link speed in the AUTOC register and restarts link.
482 **/
483 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
484 ixgbe_link_speed speed,
485 bool autoneg,
486 bool autoneg_wait_to_complete)
487 {
488 s32 status = 0;
489 ixgbe_link_speed phy_link_speed;
490 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
491 u32 speedcnt = 0;
492 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
493 bool link_up = false;
494 bool negotiation;
495 int i;
496
497 /* Mask off requested but non-supported speeds */
498 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
499 speed &= phy_link_speed;
500
501 /*
502 * Try each speed one by one, highest priority first. We do this in
503 * software because 10gb fiber doesn't support speed autonegotiation.
504 */
505 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
506 speedcnt++;
507 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
508
509 /* If we already have link at this speed, just jump out */
510 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
511
512 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
513 goto out;
514
515 /* Set the module link speed */
516 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
517 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
518 IXGBE_WRITE_FLUSH(hw);
519
520 /* Allow module to change analog characteristics (1G->10G) */
521 msleep(40);
522
523 status = ixgbe_setup_mac_link_82599(hw,
524 IXGBE_LINK_SPEED_10GB_FULL,
525 autoneg,
526 autoneg_wait_to_complete);
527 if (status != 0)
528 return status;
529
530 /* Flap the tx laser if it has not already been done */
531 hw->mac.ops.flap_tx_laser(hw);
532
533 /*
534 * Wait for the controller to acquire link. Per IEEE 802.3ap,
535 * Section 73.10.2, we may have to wait up to 500ms if KR is
536 * attempted. 82599 uses the same timing for 10g SFI.
537 */
538
539 for (i = 0; i < 5; i++) {
540 /* Wait for the link partner to also set speed */
541 msleep(100);
542
543 /* If we have link, just jump out */
544 hw->mac.ops.check_link(hw, &phy_link_speed,
545 &link_up, false);
546 if (link_up)
547 goto out;
548 }
549 }
550
551 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
552 speedcnt++;
553 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
554 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
555
556 /* If we already have link at this speed, just jump out */
557 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
558
559 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
560 goto out;
561
562 /* Set the module link speed */
563 esdp_reg &= ~IXGBE_ESDP_SDP5;
564 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
565 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
566 IXGBE_WRITE_FLUSH(hw);
567
568 /* Allow module to change analog characteristics (10G->1G) */
569 msleep(40);
570
571 status = ixgbe_setup_mac_link_82599(hw,
572 IXGBE_LINK_SPEED_1GB_FULL,
573 autoneg,
574 autoneg_wait_to_complete);
575 if (status != 0)
576 return status;
577
578 /* Flap the tx laser if it has not already been done */
579 hw->mac.ops.flap_tx_laser(hw);
580
581 /* Wait for the link partner to also set speed */
582 msleep(100);
583
584 /* If we have link, just jump out */
585 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
586 if (link_up)
587 goto out;
588 }
589
590 /*
591 * We didn't get link. Configure back to the highest speed we tried,
592 * (if there was more than one). We call ourselves back with just the
593 * single highest speed that the user requested.
594 */
595 if (speedcnt > 1)
596 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
597 highest_link_speed,
598 autoneg,
599 autoneg_wait_to_complete);
600
601 out:
602 /* Set autoneg_advertised value based on input link speed */
603 hw->phy.autoneg_advertised = 0;
604
605 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
606 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
607
608 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
609 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
610
611 return status;
612 }
613
614 /**
615 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
616 * @hw: pointer to hardware structure
617 * @speed: new link speed
618 * @autoneg: true if autonegotiation enabled
619 * @autoneg_wait_to_complete: true when waiting for completion is needed
620 *
621 * Implements the Intel SmartSpeed algorithm.
622 **/
623 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
624 ixgbe_link_speed speed, bool autoneg,
625 bool autoneg_wait_to_complete)
626 {
627 s32 status = 0;
628 ixgbe_link_speed link_speed;
629 s32 i, j;
630 bool link_up = false;
631 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
632 struct ixgbe_adapter *adapter = hw->back;
633
634 hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n");
635
636 /* Set autoneg_advertised value based on input link speed */
637 hw->phy.autoneg_advertised = 0;
638
639 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
640 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
641
642 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
643 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
644
645 if (speed & IXGBE_LINK_SPEED_100_FULL)
646 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
647
648 /*
649 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
650 * autoneg advertisement if link is unable to be established at the
651 * highest negotiated rate. This can sometimes happen due to integrity
652 * issues with the physical media connection.
653 */
654
655 /* First, try to get link with full advertisement */
656 hw->phy.smart_speed_active = false;
657 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
658 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
659 autoneg_wait_to_complete);
660 if (status)
661 goto out;
662
663 /*
664 * Wait for the controller to acquire link. Per IEEE 802.3ap,
665 * Section 73.10.2, we may have to wait up to 500ms if KR is
666 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
667 * Table 9 in the AN MAS.
668 */
669 for (i = 0; i < 5; i++) {
670 mdelay(100);
671
672 /* If we have link, just jump out */
673 hw->mac.ops.check_link(hw, &link_speed,
674 &link_up, false);
675 if (link_up)
676 goto out;
677 }
678 }
679
680 /*
681 * We didn't get link. If we advertised KR plus one of KX4/KX
682 * (or BX4/BX), then disable KR and try again.
683 */
684 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
685 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
686 goto out;
687
688 /* Turn SmartSpeed on to disable KR support */
689 hw->phy.smart_speed_active = true;
690 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
691 autoneg_wait_to_complete);
692 if (status)
693 goto out;
694
695 /*
696 * Wait for the controller to acquire link. 600ms will allow for
697 * the AN link_fail_inhibit_timer as well for multiple cycles of
698 * parallel detect, both 10g and 1g. This allows for the maximum
699 * connect attempts as defined in the AN MAS table 73-7.
700 */
701 for (i = 0; i < 6; i++) {
702 mdelay(100);
703
704 /* If we have link, just jump out */
705 hw->mac.ops.check_link(hw, &link_speed,
706 &link_up, false);
707 if (link_up)
708 goto out;
709 }
710
711 /* We didn't get link. Turn SmartSpeed back off. */
712 hw->phy.smart_speed_active = false;
713 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
714 autoneg_wait_to_complete);
715
716 out:
717 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
718 e_info(hw, "Smartspeed has downgraded the link speed from "
719 "the maximum advertised\n");
720 return status;
721 }
722
723 /**
724 * ixgbe_setup_mac_link_82599 - Set MAC link speed
725 * @hw: pointer to hardware structure
726 * @speed: new link speed
727 * @autoneg: true if autonegotiation enabled
728 * @autoneg_wait_to_complete: true when waiting for completion is needed
729 *
730 * Set the link speed in the AUTOC register and restarts link.
731 **/
732 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
733 ixgbe_link_speed speed, bool autoneg,
734 bool autoneg_wait_to_complete)
735 {
736 s32 status = 0;
737 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
738 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
739 u32 start_autoc = autoc;
740 u32 orig_autoc = 0;
741 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
742 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
743 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
744 u32 links_reg;
745 u32 i;
746 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
747
748 /* Check to see if speed passed in is supported. */
749 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
750 speed &= link_capabilities;
751
752 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
753 status = IXGBE_ERR_LINK_SETUP;
754 goto out;
755 }
756
757 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
758 if (hw->mac.orig_link_settings_stored)
759 orig_autoc = hw->mac.orig_autoc;
760 else
761 orig_autoc = autoc;
762
763
764 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
765 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
766 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
767 /* Set KX4/KX/KR support according to speed requested */
768 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
769 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
770 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
771 autoc |= IXGBE_AUTOC_KX4_SUPP;
772 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
773 (hw->phy.smart_speed_active == false))
774 autoc |= IXGBE_AUTOC_KR_SUPP;
775 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
776 autoc |= IXGBE_AUTOC_KX_SUPP;
777 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
778 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
779 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
780 /* Switch from 1G SFI to 10G SFI if requested */
781 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
782 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
783 autoc &= ~IXGBE_AUTOC_LMS_MASK;
784 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
785 }
786 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
787 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
788 /* Switch from 10G SFI to 1G SFI if requested */
789 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
790 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
791 autoc &= ~IXGBE_AUTOC_LMS_MASK;
792 if (autoneg)
793 autoc |= IXGBE_AUTOC_LMS_1G_AN;
794 else
795 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
796 }
797 }
798
799 if (autoc != start_autoc) {
800 /* Restart link */
801 autoc |= IXGBE_AUTOC_AN_RESTART;
802 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
803
804 /* Only poll for autoneg to complete if specified to do so */
805 if (autoneg_wait_to_complete) {
806 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
807 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
808 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
809 links_reg = 0; /*Just in case Autoneg time=0*/
810 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
811 links_reg =
812 IXGBE_READ_REG(hw, IXGBE_LINKS);
813 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
814 break;
815 msleep(100);
816 }
817 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
818 status =
819 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
820 hw_dbg(hw, "Autoneg did not "
821 "complete.\n");
822 }
823 }
824 }
825
826 /* Add delay to filter out noises during initial link setup */
827 msleep(50);
828 }
829
830 out:
831 return status;
832 }
833
834 /**
835 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
836 * @hw: pointer to hardware structure
837 * @speed: new link speed
838 * @autoneg: true if autonegotiation enabled
839 * @autoneg_wait_to_complete: true if waiting is needed to complete
840 *
841 * Restarts link on PHY and MAC based on settings passed in.
842 **/
843 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
844 ixgbe_link_speed speed,
845 bool autoneg,
846 bool autoneg_wait_to_complete)
847 {
848 s32 status;
849
850 /* Setup the PHY according to input speed */
851 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
852 autoneg_wait_to_complete);
853 /* Set up MAC */
854 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
855
856 return status;
857 }
858
859 /**
860 * ixgbe_reset_hw_82599 - Perform hardware reset
861 * @hw: pointer to hardware structure
862 *
863 * Resets the hardware by resetting the transmit and receive units, masks
864 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
865 * reset.
866 **/
867 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
868 {
869 s32 status = 0;
870 u32 ctrl;
871 u32 i;
872 u32 autoc;
873 u32 autoc2;
874
875 /* Call adapter stop to disable tx/rx and clear interrupts */
876 hw->mac.ops.stop_adapter(hw);
877
878 /* PHY ops must be identified and initialized prior to reset */
879
880 /* Init PHY and function pointers, perform SFP setup */
881 status = hw->phy.ops.init(hw);
882
883 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
884 goto reset_hw_out;
885
886 /* Setup SFP module if there is one present. */
887 if (hw->phy.sfp_setup_needed) {
888 status = hw->mac.ops.setup_sfp(hw);
889 hw->phy.sfp_setup_needed = false;
890 }
891
892 /* Reset PHY */
893 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
894 hw->phy.ops.reset(hw);
895
896 /*
897 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
898 * access and verify no pending requests before reset
899 */
900 status = ixgbe_disable_pcie_master(hw);
901 if (status != 0) {
902 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
903 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
904 }
905
906 /*
907 * Issue global reset to the MAC. This needs to be a SW reset.
908 * If link reset is used, it might reset the MAC when mng is using it
909 */
910 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
911 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
912 IXGBE_WRITE_FLUSH(hw);
913
914 /* Poll for reset bit to self-clear indicating reset is complete */
915 for (i = 0; i < 10; i++) {
916 udelay(1);
917 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
918 if (!(ctrl & IXGBE_CTRL_RST))
919 break;
920 }
921 if (ctrl & IXGBE_CTRL_RST) {
922 status = IXGBE_ERR_RESET_FAILED;
923 hw_dbg(hw, "Reset polling failed to complete.\n");
924 }
925
926 msleep(50);
927
928 /*
929 * Store the original AUTOC/AUTOC2 values if they have not been
930 * stored off yet. Otherwise restore the stored original
931 * values since the reset operation sets back to defaults.
932 */
933 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
934 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
935 if (hw->mac.orig_link_settings_stored == false) {
936 hw->mac.orig_autoc = autoc;
937 hw->mac.orig_autoc2 = autoc2;
938 hw->mac.orig_link_settings_stored = true;
939 } else {
940 if (autoc != hw->mac.orig_autoc)
941 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
942 IXGBE_AUTOC_AN_RESTART));
943
944 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
945 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
946 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
947 autoc2 |= (hw->mac.orig_autoc2 &
948 IXGBE_AUTOC2_UPPER_MASK);
949 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
950 }
951 }
952
953 /*
954 * Store MAC address from RAR0, clear receive address registers, and
955 * clear the multicast table. Also reset num_rar_entries to 128,
956 * since we modify this value when programming the SAN MAC address.
957 */
958 hw->mac.num_rar_entries = 128;
959 hw->mac.ops.init_rx_addrs(hw);
960
961 /* Store the permanent mac address */
962 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
963
964 /* Store the permanent SAN mac address */
965 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
966
967 /* Add the SAN MAC address to the RAR only if it's a valid address */
968 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
969 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
970 hw->mac.san_addr, 0, IXGBE_RAH_AV);
971
972 /* Reserve the last RAR for the SAN MAC address */
973 hw->mac.num_rar_entries--;
974 }
975
976 /* Store the alternative WWNN/WWPN prefix */
977 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
978 &hw->mac.wwpn_prefix);
979
980 reset_hw_out:
981 return status;
982 }
983
984 /**
985 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
986 * @hw: pointer to hardware structure
987 **/
988 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
989 {
990 int i;
991 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
992 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
993
994 /*
995 * Before starting reinitialization process,
996 * FDIRCMD.CMD must be zero.
997 */
998 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
999 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1000 IXGBE_FDIRCMD_CMD_MASK))
1001 break;
1002 udelay(10);
1003 }
1004 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1005 hw_dbg(hw ,"Flow Director previous command isn't complete, "
1006 "aborting table re-initialization.\n");
1007 return IXGBE_ERR_FDIR_REINIT_FAILED;
1008 }
1009
1010 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1011 IXGBE_WRITE_FLUSH(hw);
1012 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1013 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1014 IXGBE_FDIRCMD_CLEARHT));
1015 IXGBE_WRITE_FLUSH(hw);
1016 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1017 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1018 ~IXGBE_FDIRCMD_CLEARHT));
1019 IXGBE_WRITE_FLUSH(hw);
1020 /*
1021 * Clear FDIR Hash register to clear any leftover hashes
1022 * waiting to be programmed.
1023 */
1024 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1025 IXGBE_WRITE_FLUSH(hw);
1026
1027 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1028 IXGBE_WRITE_FLUSH(hw);
1029
1030 /* Poll init-done after we write FDIRCTRL register */
1031 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1032 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1033 IXGBE_FDIRCTRL_INIT_DONE)
1034 break;
1035 udelay(10);
1036 }
1037 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1038 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1039 return IXGBE_ERR_FDIR_REINIT_FAILED;
1040 }
1041
1042 /* Clear FDIR statistics registers (read to clear) */
1043 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1044 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1045 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1046 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1047 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1048
1049 return 0;
1050 }
1051
1052 /**
1053 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1054 * @hw: pointer to hardware structure
1055 * @pballoc: which mode to allocate filters with
1056 **/
1057 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1058 {
1059 u32 fdirctrl = 0;
1060 u32 pbsize;
1061 int i;
1062
1063 /*
1064 * Before enabling Flow Director, the Rx Packet Buffer size
1065 * must be reduced. The new value is the current size minus
1066 * flow director memory usage size.
1067 */
1068 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1069 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1070 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1071
1072 /*
1073 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1074 * intialized to zero for non DCB mode otherwise actual total RX PB
1075 * would be bigger than programmed and filter space would run into
1076 * the PB 0 region.
1077 */
1078 for (i = 1; i < 8; i++)
1079 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1080
1081 /* Send interrupt when 64 filters are left */
1082 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1083
1084 /* Set the maximum length per hash bucket to 0xA filters */
1085 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1086
1087 switch (pballoc) {
1088 case IXGBE_FDIR_PBALLOC_64K:
1089 /* 8k - 1 signature filters */
1090 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1091 break;
1092 case IXGBE_FDIR_PBALLOC_128K:
1093 /* 16k - 1 signature filters */
1094 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1095 break;
1096 case IXGBE_FDIR_PBALLOC_256K:
1097 /* 32k - 1 signature filters */
1098 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1099 break;
1100 default:
1101 /* bad value */
1102 return IXGBE_ERR_CONFIG;
1103 };
1104
1105 /* Move the flexible bytes to use the ethertype - shift 6 words */
1106 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1107
1108 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1109
1110 /* Prime the keys for hashing */
1111 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1112 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1113 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1114 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1115
1116 /*
1117 * Poll init-done after we write the register. Estimated times:
1118 * 10G: PBALLOC = 11b, timing is 60us
1119 * 1G: PBALLOC = 11b, timing is 600us
1120 * 100M: PBALLOC = 11b, timing is 6ms
1121 *
1122 * Multiple these timings by 4 if under full Rx load
1123 *
1124 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1125 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1126 * this might not finish in our poll time, but we can live with that
1127 * for now.
1128 */
1129 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1130 IXGBE_WRITE_FLUSH(hw);
1131 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1132 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1133 IXGBE_FDIRCTRL_INIT_DONE)
1134 break;
1135 msleep(1);
1136 }
1137 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1138 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1139
1140 return 0;
1141 }
1142
1143 /**
1144 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1145 * @hw: pointer to hardware structure
1146 * @pballoc: which mode to allocate filters with
1147 **/
1148 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1149 {
1150 u32 fdirctrl = 0;
1151 u32 pbsize;
1152 int i;
1153
1154 /*
1155 * Before enabling Flow Director, the Rx Packet Buffer size
1156 * must be reduced. The new value is the current size minus
1157 * flow director memory usage size.
1158 */
1159 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1160 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1161 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1162
1163 /*
1164 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1165 * intialized to zero for non DCB mode otherwise actual total RX PB
1166 * would be bigger than programmed and filter space would run into
1167 * the PB 0 region.
1168 */
1169 for (i = 1; i < 8; i++)
1170 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1171
1172 /* Send interrupt when 64 filters are left */
1173 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1174
1175 /* Initialize the drop queue to Rx queue 127 */
1176 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1177
1178 switch (pballoc) {
1179 case IXGBE_FDIR_PBALLOC_64K:
1180 /* 2k - 1 perfect filters */
1181 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1182 break;
1183 case IXGBE_FDIR_PBALLOC_128K:
1184 /* 4k - 1 perfect filters */
1185 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1186 break;
1187 case IXGBE_FDIR_PBALLOC_256K:
1188 /* 8k - 1 perfect filters */
1189 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1190 break;
1191 default:
1192 /* bad value */
1193 return IXGBE_ERR_CONFIG;
1194 };
1195
1196 /* Turn perfect match filtering on */
1197 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1198 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1199
1200 /* Move the flexible bytes to use the ethertype - shift 6 words */
1201 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1202
1203 /* Prime the keys for hashing */
1204 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1205 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1206 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1207 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1208
1209 /*
1210 * Poll init-done after we write the register. Estimated times:
1211 * 10G: PBALLOC = 11b, timing is 60us
1212 * 1G: PBALLOC = 11b, timing is 600us
1213 * 100M: PBALLOC = 11b, timing is 6ms
1214 *
1215 * Multiple these timings by 4 if under full Rx load
1216 *
1217 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1218 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1219 * this might not finish in our poll time, but we can live with that
1220 * for now.
1221 */
1222
1223 /* Set the maximum length per hash bucket to 0xA filters */
1224 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1225
1226 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1227 IXGBE_WRITE_FLUSH(hw);
1228 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1229 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1230 IXGBE_FDIRCTRL_INIT_DONE)
1231 break;
1232 msleep(1);
1233 }
1234 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1235 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1236
1237 return 0;
1238 }
1239
1240
1241 /**
1242 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1243 * @stream: input bitstream to compute the hash on
1244 * @key: 32-bit hash key
1245 **/
1246 static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1247 u32 key)
1248 {
1249 /*
1250 * The algorithm is as follows:
1251 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1252 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1253 * and A[n] x B[n] is bitwise AND between same length strings
1254 *
1255 * K[n] is 16 bits, defined as:
1256 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1257 * for n modulo 32 < 15, K[n] =
1258 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1259 *
1260 * S[n] is 16 bits, defined as:
1261 * for n >= 15, S[n] = S[n:n - 15]
1262 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1263 *
1264 * To simplify for programming, the algorithm is implemented
1265 * in software this way:
1266 *
1267 * Key[31:0], Stream[335:0]
1268 *
1269 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1270 * int_key[350:0] = tmp_key[351:1]
1271 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1272 *
1273 * hash[15:0] = 0;
1274 * for (i = 0; i < 351; i++) {
1275 * if (int_key[i])
1276 * hash ^= int_stream[(i + 15):i];
1277 * }
1278 */
1279
1280 union {
1281 u64 fill[6];
1282 u32 key[11];
1283 u8 key_stream[44];
1284 } tmp_key;
1285
1286 u8 *stream = (u8 *)atr_input;
1287 u8 int_key[44]; /* upper-most bit unused */
1288 u8 hash_str[46]; /* upper-most 2 bits unused */
1289 u16 hash_result = 0;
1290 int i, j, k, h;
1291
1292 /*
1293 * Initialize the fill member to prevent warnings
1294 * on some compilers
1295 */
1296 tmp_key.fill[0] = 0;
1297
1298 /* First load the temporary key stream */
1299 for (i = 0; i < 6; i++) {
1300 u64 fillkey = ((u64)key << 32) | key;
1301 tmp_key.fill[i] = fillkey;
1302 }
1303
1304 /*
1305 * Set the interim key for the hashing. Bit 352 is unused, so we must
1306 * shift and compensate when building the key.
1307 */
1308
1309 int_key[0] = tmp_key.key_stream[0] >> 1;
1310 for (i = 1, j = 0; i < 44; i++) {
1311 unsigned int this_key = tmp_key.key_stream[j] << 7;
1312 j++;
1313 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1314 }
1315
1316 /*
1317 * Set the interim bit string for the hashing. Bits 368 and 367 are
1318 * unused, so shift and compensate when building the string.
1319 */
1320 hash_str[0] = (stream[40] & 0x7f) >> 1;
1321 for (i = 1, j = 40; i < 46; i++) {
1322 unsigned int this_str = stream[j] << 7;
1323 j++;
1324 if (j > 41)
1325 j = 0;
1326 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1327 }
1328
1329 /*
1330 * Now compute the hash. i is the index into hash_str, j is into our
1331 * key stream, k is counting the number of bits, and h interates within
1332 * each byte.
1333 */
1334 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1335 for (h = 0; h < 8 && k < 351; h++, k++) {
1336 if (int_key[j] & (1 << h)) {
1337 /*
1338 * Key bit is set, XOR in the current 16-bit
1339 * string. Example of processing:
1340 * h = 0,
1341 * tmp = (hash_str[i - 2] & 0 << 16) |
1342 * (hash_str[i - 1] & 0xff << 8) |
1343 * (hash_str[i] & 0xff >> 0)
1344 * So tmp = hash_str[15 + k:k], since the
1345 * i + 2 clause rolls off the 16-bit value
1346 * h = 7,
1347 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1348 * (hash_str[i - 1] & 0xff << 1) |
1349 * (hash_str[i] & 0x80 >> 7)
1350 */
1351 int tmp = (hash_str[i] >> h);
1352 tmp |= (hash_str[i - 1] << (8 - h));
1353 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1354 << (16 - h);
1355 hash_result ^= (u16)tmp;
1356 }
1357 }
1358 }
1359
1360 return hash_result;
1361 }
1362
1363 /**
1364 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1365 * @input: input stream to modify
1366 * @vlan: the VLAN id to load
1367 **/
1368 s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1369 {
1370 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1371 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1372
1373 return 0;
1374 }
1375
1376 /**
1377 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1378 * @input: input stream to modify
1379 * @src_addr: the IP address to load
1380 **/
1381 s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1382 {
1383 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1384 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1385 (src_addr >> 16) & 0xff;
1386 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1387 (src_addr >> 8) & 0xff;
1388 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1389
1390 return 0;
1391 }
1392
1393 /**
1394 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1395 * @input: input stream to modify
1396 * @dst_addr: the IP address to load
1397 **/
1398 s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1399 {
1400 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1401 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1402 (dst_addr >> 16) & 0xff;
1403 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1404 (dst_addr >> 8) & 0xff;
1405 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1406
1407 return 0;
1408 }
1409
1410 /**
1411 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1412 * @input: input stream to modify
1413 * @src_addr_1: the first 4 bytes of the IP address to load
1414 * @src_addr_2: the second 4 bytes of the IP address to load
1415 * @src_addr_3: the third 4 bytes of the IP address to load
1416 * @src_addr_4: the fourth 4 bytes of the IP address to load
1417 **/
1418 s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
1419 u32 src_addr_1, u32 src_addr_2,
1420 u32 src_addr_3, u32 src_addr_4)
1421 {
1422 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
1423 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
1424 (src_addr_4 >> 8) & 0xff;
1425 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
1426 (src_addr_4 >> 16) & 0xff;
1427 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
1428
1429 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
1430 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
1431 (src_addr_3 >> 8) & 0xff;
1432 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
1433 (src_addr_3 >> 16) & 0xff;
1434 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
1435
1436 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
1437 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
1438 (src_addr_2 >> 8) & 0xff;
1439 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
1440 (src_addr_2 >> 16) & 0xff;
1441 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
1442
1443 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
1444 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
1445 (src_addr_1 >> 8) & 0xff;
1446 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
1447 (src_addr_1 >> 16) & 0xff;
1448 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
1449
1450 return 0;
1451 }
1452
1453 /**
1454 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1455 * @input: input stream to modify
1456 * @dst_addr_1: the first 4 bytes of the IP address to load
1457 * @dst_addr_2: the second 4 bytes of the IP address to load
1458 * @dst_addr_3: the third 4 bytes of the IP address to load
1459 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1460 **/
1461 s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
1462 u32 dst_addr_1, u32 dst_addr_2,
1463 u32 dst_addr_3, u32 dst_addr_4)
1464 {
1465 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
1466 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
1467 (dst_addr_4 >> 8) & 0xff;
1468 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
1469 (dst_addr_4 >> 16) & 0xff;
1470 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
1471
1472 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
1473 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
1474 (dst_addr_3 >> 8) & 0xff;
1475 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
1476 (dst_addr_3 >> 16) & 0xff;
1477 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
1478
1479 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
1480 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
1481 (dst_addr_2 >> 8) & 0xff;
1482 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
1483 (dst_addr_2 >> 16) & 0xff;
1484 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
1485
1486 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
1487 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
1488 (dst_addr_1 >> 8) & 0xff;
1489 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
1490 (dst_addr_1 >> 16) & 0xff;
1491 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
1492
1493 return 0;
1494 }
1495
1496 /**
1497 * ixgbe_atr_set_src_port_82599 - Sets the source port
1498 * @input: input stream to modify
1499 * @src_port: the source port to load
1500 **/
1501 s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1502 {
1503 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1504 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1505
1506 return 0;
1507 }
1508
1509 /**
1510 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1511 * @input: input stream to modify
1512 * @dst_port: the destination port to load
1513 **/
1514 s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1515 {
1516 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1517 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1518
1519 return 0;
1520 }
1521
1522 /**
1523 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1524 * @input: input stream to modify
1525 * @flex_bytes: the flexible bytes to load
1526 **/
1527 s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1528 {
1529 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1530 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1531
1532 return 0;
1533 }
1534
1535 /**
1536 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1537 * @input: input stream to modify
1538 * @vm_pool: the Virtual Machine pool to load
1539 **/
1540 s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
1541 u8 vm_pool)
1542 {
1543 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
1544
1545 return 0;
1546 }
1547
1548 /**
1549 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1550 * @input: input stream to modify
1551 * @l4type: the layer 4 type value to load
1552 **/
1553 s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1554 {
1555 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1556
1557 return 0;
1558 }
1559
1560 /**
1561 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1562 * @input: input stream to search
1563 * @vlan: the VLAN id to load
1564 **/
1565 static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan)
1566 {
1567 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1568 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1569
1570 return 0;
1571 }
1572
1573 /**
1574 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1575 * @input: input stream to search
1576 * @src_addr: the IP address to load
1577 **/
1578 static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1579 u32 *src_addr)
1580 {
1581 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1582 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1583 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1584 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1585
1586 return 0;
1587 }
1588
1589 /**
1590 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1591 * @input: input stream to search
1592 * @dst_addr: the IP address to load
1593 **/
1594 static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1595 u32 *dst_addr)
1596 {
1597 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1598 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1599 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1600 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1601
1602 return 0;
1603 }
1604
1605 /**
1606 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1607 * @input: input stream to search
1608 * @src_addr_1: the first 4 bytes of the IP address to load
1609 * @src_addr_2: the second 4 bytes of the IP address to load
1610 * @src_addr_3: the third 4 bytes of the IP address to load
1611 * @src_addr_4: the fourth 4 bytes of the IP address to load
1612 **/
1613 static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1614 u32 *src_addr_1, u32 *src_addr_2,
1615 u32 *src_addr_3, u32 *src_addr_4)
1616 {
1617 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1618 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1619 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1620 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1621
1622 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1623 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1624 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1625 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1626
1627 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1628 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1629 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1630 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1631
1632 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1633 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1634 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1635 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1636
1637 return 0;
1638 }
1639
1640 /**
1641 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1642 * @input: input stream to search
1643 * @dst_addr_1: the first 4 bytes of the IP address to load
1644 * @dst_addr_2: the second 4 bytes of the IP address to load
1645 * @dst_addr_3: the third 4 bytes of the IP address to load
1646 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1647 **/
1648 s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
1649 u32 *dst_addr_1, u32 *dst_addr_2,
1650 u32 *dst_addr_3, u32 *dst_addr_4)
1651 {
1652 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
1653 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
1654 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
1655 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
1656
1657 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
1658 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
1659 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
1660 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
1661
1662 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
1663 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
1664 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
1665 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
1666
1667 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
1668 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
1669 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
1670 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
1671
1672 return 0;
1673 }
1674
1675 /**
1676 * ixgbe_atr_get_src_port_82599 - Gets the source port
1677 * @input: input stream to modify
1678 * @src_port: the source port to load
1679 *
1680 * Even though the input is given in big-endian, the FDIRPORT registers
1681 * expect the ports to be programmed in little-endian. Hence the need to swap
1682 * endianness when retrieving the data. This can be confusing since the
1683 * internal hash engine expects it to be big-endian.
1684 **/
1685 static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1686 u16 *src_port)
1687 {
1688 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1689 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1690
1691 return 0;
1692 }
1693
1694 /**
1695 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1696 * @input: input stream to modify
1697 * @dst_port: the destination port to load
1698 *
1699 * Even though the input is given in big-endian, the FDIRPORT registers
1700 * expect the ports to be programmed in little-endian. Hence the need to swap
1701 * endianness when retrieving the data. This can be confusing since the
1702 * internal hash engine expects it to be big-endian.
1703 **/
1704 static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1705 u16 *dst_port)
1706 {
1707 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1708 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1709
1710 return 0;
1711 }
1712
1713 /**
1714 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1715 * @input: input stream to modify
1716 * @flex_bytes: the flexible bytes to load
1717 **/
1718 static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1719 u16 *flex_byte)
1720 {
1721 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1722 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1723
1724 return 0;
1725 }
1726
1727 /**
1728 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
1729 * @input: input stream to modify
1730 * @vm_pool: the Virtual Machine pool to load
1731 **/
1732 s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
1733 u8 *vm_pool)
1734 {
1735 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
1736
1737 return 0;
1738 }
1739
1740 /**
1741 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
1742 * @input: input stream to modify
1743 * @l4type: the layer 4 type value to load
1744 **/
1745 static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
1746 u8 *l4type)
1747 {
1748 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
1749
1750 return 0;
1751 }
1752
1753 /**
1754 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1755 * @hw: pointer to hardware structure
1756 * @stream: input bitstream
1757 * @queue: queue index to direct traffic to
1758 **/
1759 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1760 struct ixgbe_atr_input *input,
1761 u8 queue)
1762 {
1763 u64 fdirhashcmd;
1764 u64 fdircmd;
1765 u32 fdirhash;
1766 u16 bucket_hash, sig_hash;
1767 u8 l4type;
1768
1769 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1770 IXGBE_ATR_BUCKET_HASH_KEY);
1771
1772 /* bucket_hash is only 15 bits */
1773 bucket_hash &= IXGBE_ATR_HASH_MASK;
1774
1775 sig_hash = ixgbe_atr_compute_hash_82599(input,
1776 IXGBE_ATR_SIGNATURE_HASH_KEY);
1777
1778 /* Get the l4type in order to program FDIRCMD properly */
1779 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
1780 ixgbe_atr_get_l4type_82599(input, &l4type);
1781
1782 /*
1783 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1784 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1785 */
1786 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1787
1788 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1789 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
1790
1791 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1792 case IXGBE_ATR_L4TYPE_TCP:
1793 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1794 break;
1795 case IXGBE_ATR_L4TYPE_UDP:
1796 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1797 break;
1798 case IXGBE_ATR_L4TYPE_SCTP:
1799 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1800 break;
1801 default:
1802 hw_dbg(hw, "Error on l4type input\n");
1803 return IXGBE_ERR_CONFIG;
1804 }
1805
1806 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
1807 fdircmd |= IXGBE_FDIRCMD_IPV6;
1808
1809 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
1810 fdirhashcmd = ((fdircmd << 32) | fdirhash);
1811
1812 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1813
1814 return 0;
1815 }
1816
1817 /**
1818 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1819 * @hw: pointer to hardware structure
1820 * @input: input bitstream
1821 * @input_masks: bitwise masks for relevant fields
1822 * @soft_id: software index into the silicon hash tables for filter storage
1823 * @queue: queue index to direct traffic to
1824 *
1825 * Note that the caller to this function must lock before calling, since the
1826 * hardware writes must be protected from one another.
1827 **/
1828 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1829 struct ixgbe_atr_input *input,
1830 struct ixgbe_atr_input_masks *input_masks,
1831 u16 soft_id, u8 queue)
1832 {
1833 u32 fdircmd = 0;
1834 u32 fdirhash;
1835 u32 src_ipv4 = 0, dst_ipv4 = 0;
1836 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
1837 u16 src_port, dst_port, vlan_id, flex_bytes;
1838 u16 bucket_hash;
1839 u8 l4type;
1840 u8 fdirm = 0;
1841
1842 /* Get our input values */
1843 ixgbe_atr_get_l4type_82599(input, &l4type);
1844
1845 /*
1846 * Check l4type formatting, and bail out before we touch the hardware
1847 * if there's a configuration issue
1848 */
1849 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1850 case IXGBE_ATR_L4TYPE_TCP:
1851 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1852 break;
1853 case IXGBE_ATR_L4TYPE_UDP:
1854 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1855 break;
1856 case IXGBE_ATR_L4TYPE_SCTP:
1857 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1858 break;
1859 default:
1860 hw_dbg(hw, "Error on l4type input\n");
1861 return IXGBE_ERR_CONFIG;
1862 }
1863
1864 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1865 IXGBE_ATR_BUCKET_HASH_KEY);
1866
1867 /* bucket_hash is only 15 bits */
1868 bucket_hash &= IXGBE_ATR_HASH_MASK;
1869
1870 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
1871 ixgbe_atr_get_src_port_82599(input, &src_port);
1872 ixgbe_atr_get_dst_port_82599(input, &dst_port);
1873 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
1874
1875 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1876
1877 /* Now figure out if we're IPv4 or IPv6 */
1878 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
1879 /* IPv6 */
1880 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
1881 &src_ipv6_3, &src_ipv6_4);
1882
1883 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
1884 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
1885 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
1886 /* The last 4 bytes is the same register as IPv4 */
1887 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
1888
1889 fdircmd |= IXGBE_FDIRCMD_IPV6;
1890 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
1891 } else {
1892 /* IPv4 */
1893 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
1894 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
1895 }
1896
1897 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
1898 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
1899
1900 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
1901 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
1902 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
1903 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
1904
1905 /*
1906 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1907 * are zero, then assume a full mask for that field. Also assume that
1908 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1909 * cannot be masked out in this implementation.
1910 *
1911 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1912 * point in time.
1913 */
1914 if (src_ipv4 == 0)
1915 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xffffffff);
1916 else
1917 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask);
1918
1919 if (dst_ipv4 == 0)
1920 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xffffffff);
1921 else
1922 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask);
1923
1924 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1925 case IXGBE_ATR_L4TYPE_TCP:
1926 if (src_port == 0)
1927 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xffff);
1928 else
1929 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
1930 input_masks->src_port_mask);
1931
1932 if (dst_port == 0)
1933 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
1934 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
1935 (0xffff << 16)));
1936 else
1937 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
1938 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
1939 (input_masks->dst_port_mask << 16)));
1940 break;
1941 case IXGBE_ATR_L4TYPE_UDP:
1942 if (src_port == 0)
1943 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xffff);
1944 else
1945 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
1946 input_masks->src_port_mask);
1947
1948 if (dst_port == 0)
1949 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
1950 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
1951 (0xffff << 16)));
1952 else
1953 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
1954 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
1955 (input_masks->src_port_mask << 16)));
1956 break;
1957 default:
1958 /* this already would have failed above */
1959 break;
1960 }
1961
1962 /* Program the last mask register, FDIRM */
1963 if (input_masks->vlan_id_mask || !vlan_id)
1964 /* Mask both VLAN and VLANP - bits 0 and 1 */
1965 fdirm |= 0x3;
1966
1967 if (input_masks->data_mask || !flex_bytes)
1968 /* Flex bytes need masking, so mask the whole thing - bit 4 */
1969 fdirm |= 0x10;
1970
1971 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1972 fdirm |= 0x24;
1973
1974 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1975
1976 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
1977 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
1978 fdircmd |= IXGBE_FDIRCMD_LAST;
1979 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
1980 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1981
1982 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1983 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1984
1985 return 0;
1986 }
1987 /**
1988 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1989 * @hw: pointer to hardware structure
1990 * @reg: analog register to read
1991 * @val: read value
1992 *
1993 * Performs read operation to Omer analog register specified.
1994 **/
1995 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1996 {
1997 u32 core_ctl;
1998
1999 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2000 (reg << 8));
2001 IXGBE_WRITE_FLUSH(hw);
2002 udelay(10);
2003 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2004 *val = (u8)core_ctl;
2005
2006 return 0;
2007 }
2008
2009 /**
2010 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2011 * @hw: pointer to hardware structure
2012 * @reg: atlas register to write
2013 * @val: value to write
2014 *
2015 * Performs write operation to Omer analog register specified.
2016 **/
2017 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2018 {
2019 u32 core_ctl;
2020
2021 core_ctl = (reg << 8) | val;
2022 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2023 IXGBE_WRITE_FLUSH(hw);
2024 udelay(10);
2025
2026 return 0;
2027 }
2028
2029 /**
2030 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2031 * @hw: pointer to hardware structure
2032 *
2033 * Starts the hardware using the generic start_hw function.
2034 * Then performs device-specific:
2035 * Clears the rate limiter registers.
2036 **/
2037 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2038 {
2039 u32 q_num;
2040 s32 ret_val;
2041
2042 ret_val = ixgbe_start_hw_generic(hw);
2043
2044 /* Clear the rate limiters */
2045 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
2046 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
2047 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2048 }
2049 IXGBE_WRITE_FLUSH(hw);
2050
2051 /* We need to run link autotry after the driver loads */
2052 hw->mac.autotry_restart = true;
2053
2054 if (ret_val == 0)
2055 ret_val = ixgbe_verify_fw_version_82599(hw);
2056
2057 return ret_val;
2058 }
2059
2060 /**
2061 * ixgbe_identify_phy_82599 - Get physical layer module
2062 * @hw: pointer to hardware structure
2063 *
2064 * Determines the physical layer module found on the current adapter.
2065 **/
2066 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2067 {
2068 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2069 status = ixgbe_identify_phy_generic(hw);
2070 if (status != 0)
2071 status = ixgbe_identify_sfp_module_generic(hw);
2072 return status;
2073 }
2074
2075 /**
2076 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2077 * @hw: pointer to hardware structure
2078 *
2079 * Determines physical layer capabilities of the current configuration.
2080 **/
2081 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2082 {
2083 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2084 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2085 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2086 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2087 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2088 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2089 u16 ext_ability = 0;
2090 u8 comp_codes_10g = 0;
2091 u8 comp_codes_1g = 0;
2092
2093 hw->phy.ops.identify(hw);
2094
2095 if (hw->phy.type == ixgbe_phy_tn ||
2096 hw->phy.type == ixgbe_phy_cu_unknown) {
2097 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2098 &ext_ability);
2099 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
2100 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2101 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
2102 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2103 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
2104 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2105 goto out;
2106 }
2107
2108 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2109 case IXGBE_AUTOC_LMS_1G_AN:
2110 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2111 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2112 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2113 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2114 goto out;
2115 } else
2116 /* SFI mode so read SFP module */
2117 goto sfp_check;
2118 break;
2119 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2120 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2121 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2122 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2123 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2124 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2125 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2126 goto out;
2127 break;
2128 case IXGBE_AUTOC_LMS_10G_SERIAL:
2129 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2130 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2131 goto out;
2132 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2133 goto sfp_check;
2134 break;
2135 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2136 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2137 if (autoc & IXGBE_AUTOC_KX_SUPP)
2138 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2139 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2140 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2141 if (autoc & IXGBE_AUTOC_KR_SUPP)
2142 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2143 goto out;
2144 break;
2145 default:
2146 goto out;
2147 break;
2148 }
2149
2150 sfp_check:
2151 /* SFP check must be done last since DA modules are sometimes used to
2152 * test KR mode - we need to id KR mode correctly before SFP module.
2153 * Call identify_sfp because the pluggable module may have changed */
2154 hw->phy.ops.identify_sfp(hw);
2155 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2156 goto out;
2157
2158 switch (hw->phy.type) {
2159 case ixgbe_phy_sfp_passive_tyco:
2160 case ixgbe_phy_sfp_passive_unknown:
2161 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2162 break;
2163 case ixgbe_phy_sfp_ftl_active:
2164 case ixgbe_phy_sfp_active_unknown:
2165 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2166 break;
2167 case ixgbe_phy_sfp_avago:
2168 case ixgbe_phy_sfp_ftl:
2169 case ixgbe_phy_sfp_intel:
2170 case ixgbe_phy_sfp_unknown:
2171 hw->phy.ops.read_i2c_eeprom(hw,
2172 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2173 hw->phy.ops.read_i2c_eeprom(hw,
2174 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2175 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2176 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2177 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2178 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2179 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2180 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2181 break;
2182 default:
2183 break;
2184 }
2185
2186 out:
2187 return physical_layer;
2188 }
2189
2190 /**
2191 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2192 * @hw: pointer to hardware structure
2193 * @regval: register value to write to RXCTRL
2194 *
2195 * Enables the Rx DMA unit for 82599
2196 **/
2197 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2198 {
2199 #define IXGBE_MAX_SECRX_POLL 30
2200 int i;
2201 int secrxreg;
2202
2203 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2204 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2205 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2206 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2207 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2208 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2209 break;
2210 else
2211 udelay(10);
2212 }
2213
2214 /* For informational purposes only */
2215 if (i >= IXGBE_MAX_SECRX_POLL)
2216 hw_dbg(hw, "Rx unit being enabled before security "
2217 "path fully disabled. Continuing with init.\n");
2218
2219 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2220 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2221 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2222 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2223 IXGBE_WRITE_FLUSH(hw);
2224
2225 return 0;
2226 }
2227
2228 /**
2229 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2230 * @hw: pointer to hardware structure
2231 * @device_caps: the EEPROM word with the extra device capabilities
2232 *
2233 * This function will read the EEPROM location for the device capabilities,
2234 * and return the word through device_caps.
2235 **/
2236 static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
2237 {
2238 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2239
2240 return 0;
2241 }
2242
2243 /**
2244 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2245 * @hw: pointer to hardware structure
2246 *
2247 * Verifies that installed the firmware version is 0.6 or higher
2248 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2249 *
2250 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2251 * if the FW version is not supported.
2252 **/
2253 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2254 {
2255 s32 status = IXGBE_ERR_EEPROM_VERSION;
2256 u16 fw_offset, fw_ptp_cfg_offset;
2257 u16 fw_version = 0;
2258
2259 /* firmware check is only necessary for SFI devices */
2260 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2261 status = 0;
2262 goto fw_version_out;
2263 }
2264
2265 /* get the offset to the Firmware Module block */
2266 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2267
2268 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2269 goto fw_version_out;
2270
2271 /* get the offset to the Pass Through Patch Configuration block */
2272 hw->eeprom.ops.read(hw, (fw_offset +
2273 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2274 &fw_ptp_cfg_offset);
2275
2276 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2277 goto fw_version_out;
2278
2279 /* get the firmware version */
2280 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2281 IXGBE_FW_PATCH_VERSION_4),
2282 &fw_version);
2283
2284 if (fw_version > 0x5)
2285 status = 0;
2286
2287 fw_version_out:
2288 return status;
2289 }
2290
2291 /**
2292 * ixgbe_get_wwn_prefix_82599 - Get alternative WWNN/WWPN prefix from
2293 * the EEPROM
2294 * @hw: pointer to hardware structure
2295 * @wwnn_prefix: the alternative WWNN prefix
2296 * @wwpn_prefix: the alternative WWPN prefix
2297 *
2298 * This function will read the EEPROM from the alternative SAN MAC address
2299 * block to check the support for the alternative WWNN/WWPN prefix support.
2300 **/
2301 static s32 ixgbe_get_wwn_prefix_82599(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2302 u16 *wwpn_prefix)
2303 {
2304 u16 offset, caps;
2305 u16 alt_san_mac_blk_offset;
2306
2307 /* clear output first */
2308 *wwnn_prefix = 0xFFFF;
2309 *wwpn_prefix = 0xFFFF;
2310
2311 /* check if alternative SAN MAC is supported */
2312 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2313 &alt_san_mac_blk_offset);
2314
2315 if ((alt_san_mac_blk_offset == 0) ||
2316 (alt_san_mac_blk_offset == 0xFFFF))
2317 goto wwn_prefix_out;
2318
2319 /* check capability in alternative san mac address block */
2320 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2321 hw->eeprom.ops.read(hw, offset, &caps);
2322 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2323 goto wwn_prefix_out;
2324
2325 /* get the corresponding prefix for WWNN/WWPN */
2326 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2327 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2328
2329 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2330 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
2331
2332 wwn_prefix_out:
2333 return 0;
2334 }
2335
2336 static struct ixgbe_mac_operations mac_ops_82599 = {
2337 .init_hw = &ixgbe_init_hw_generic,
2338 .reset_hw = &ixgbe_reset_hw_82599,
2339 .start_hw = &ixgbe_start_hw_82599,
2340 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2341 .get_media_type = &ixgbe_get_media_type_82599,
2342 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2343 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2344 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2345 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2346 .get_device_caps = &ixgbe_get_device_caps_82599,
2347 .get_wwn_prefix = &ixgbe_get_wwn_prefix_82599,
2348 .stop_adapter = &ixgbe_stop_adapter_generic,
2349 .get_bus_info = &ixgbe_get_bus_info_generic,
2350 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2351 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2352 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2353 .setup_link = &ixgbe_setup_mac_link_82599,
2354 .check_link = &ixgbe_check_mac_link_generic,
2355 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2356 .led_on = &ixgbe_led_on_generic,
2357 .led_off = &ixgbe_led_off_generic,
2358 .blink_led_start = &ixgbe_blink_led_start_generic,
2359 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2360 .set_rar = &ixgbe_set_rar_generic,
2361 .clear_rar = &ixgbe_clear_rar_generic,
2362 .set_vmdq = &ixgbe_set_vmdq_generic,
2363 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2364 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2365 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2366 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2367 .enable_mc = &ixgbe_enable_mc_generic,
2368 .disable_mc = &ixgbe_disable_mc_generic,
2369 .clear_vfta = &ixgbe_clear_vfta_generic,
2370 .set_vfta = &ixgbe_set_vfta_generic,
2371 .fc_enable = &ixgbe_fc_enable_generic,
2372 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2373 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2374 };
2375
2376 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2377 .init_params = &ixgbe_init_eeprom_params_generic,
2378 .read = &ixgbe_read_eerd_generic,
2379 .write = &ixgbe_write_eeprom_generic,
2380 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2381 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2382 };
2383
2384 static struct ixgbe_phy_operations phy_ops_82599 = {
2385 .identify = &ixgbe_identify_phy_82599,
2386 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2387 .init = &ixgbe_init_phy_ops_82599,
2388 .reset = &ixgbe_reset_phy_generic,
2389 .read_reg = &ixgbe_read_phy_reg_generic,
2390 .write_reg = &ixgbe_write_phy_reg_generic,
2391 .setup_link = &ixgbe_setup_phy_link_generic,
2392 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2393 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2394 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2395 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2396 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2397 .check_overtemp = &ixgbe_tn_check_overtemp,
2398 };
2399
2400 struct ixgbe_info ixgbe_82599_info = {
2401 .mac = ixgbe_mac_82599EB,
2402 .get_invariants = &ixgbe_get_invariants_82599,
2403 .mac_ops = &mac_ops_82599,
2404 .eeprom_ops = &eeprom_ops_82599,
2405 .phy_ops = &phy_ops_82599,
2406 .mbx_ops = &mbx_ops_82599,
2407 };
Tomato firmware and modifications.