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1 /* $Id: cassini.h,v 1.16 2004/08/17 21:15:16 Exp $
2 * cassini.h: Definitions for Sun Microsystems Cassini(+) ethernet driver.
3 *
4 * Copyright (C) 2004 Sun Microsystems Inc.
5 * Copyright (c) 2003 Adrian Sun (asun@darksunrising.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
20 * 02111-1307, USA.
21 *
22 * vendor id: 0x108E (Sun Microsystems, Inc.)
23 * device id: 0xabba (Cassini)
24 * revision ids: 0x01 = Cassini
25 * 0x02 = Cassini rev 2
26 * 0x10 = Cassini+
27 * 0x11 = Cassini+ 0.2u
28 *
29 * vendor id: 0x100b (National Semiconductor)
30 * device id: 0x0035 (DP83065/Saturn)
31 * revision ids: 0x30 = Saturn B2
32 *
33 * rings are all offset from 0.
34 *
35 * there are two clock domains:
36 * PCI: 33/66MHz clock
37 * chip: 125MHz clock
38 */
40 #ifndef _CASSINI_H
41 #define _CASSINI_H
43 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
44 * 32-bit words. there is no i/o port access. REG_ addresses are
45 * shared between cassini and cassini+. REG_PLUS_ addresses only
46 * appear in cassini+. REG_MINUS_ addresses only appear in cassini.
47 */
48 #define CAS_ID_REV2 0x02
49 #define CAS_ID_REVPLUS 0x10
50 #define CAS_ID_REVPLUS02u 0x11
51 #define CAS_ID_REVSATURNB2 0x30
53 /** global resources **/
55 /* this register sets the weights for the weighted round robin arbiter. e.g.,
56 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
57 * for its next turn to access the pci bus.
58 * map: 0x0 = x1, 0x1 = x2, 0x2 = x4, 0x3 = x8
59 * DEFAULT: 0x0, SIZE: 5 bits
60 */
62 #define CAWR_RX_DMA_WEIGHT_SHIFT 0
64 #define CAWR_TX_DMA_WEIGHT_SHIFT 2
68 /* if enabled, BIM can send bursts across PCI bus > cacheline size. burst
69 * sizes determined by length of packet or descriptor transfer and the
70 * max length allowed by the target.
71 * DEFAULT: 0x0, SIZE: 1 bit
72 */
76 /* top level interrupts [0-9] are auto-cleared to 0 when the status
77 * register is read. second level interrupts [13 - 18] are cleared at
78 * the source. tx completion register 3 is replicated in [19 - 31]
79 * DEFAULT: 0x00000000, SIZE: 29 bits
80 */
83 xferred from host queue to
84 TX FIFO */
86 TX FIFO. i.e.,
87 TX Kick == TX complete. if
88 PACED_MODE set, then TX FIFO
89 also empty */
91 FIFO */
93 corrupted. FATAL ERROR */
95 from RX FIFO to host mem.
96 RX completion reg updated.
97 may be delayed by recv
98 intr blanking. */
100 RX Kick == RX complete */
102 corrupted. FATAL ERROR */
104 ring to post descriptors.
105 RX complete head incr to
106 almost reach RX complete
107 tail */
109 programmable threshold #
110 of free descr avail for
111 hw use */
113 programmable threshold #
114 of descr spaces for hw
115 use in completion descr
116 ring */
118 len of non-reassembly pkt
119 from fifo during DMA or
120 header parser provides TCP
121 header and payload size >
122 MAC packet size.
123 FATAL ERROR */
125 bit will be set if an interrupt
126 generated on the pci bus. useful
127 when driver is polling for
128 interrupts */
131 least 1 unmasked interrupt set */
133 least 1 unmasked interrupt set */
135 at least 1 unmasked interrupt
136 set */
138 1 unmasked interrupt set */
140 BIF has at least 1 unmasked
141 interrupt set */
143 3 reg data */
144 #define INTR_TX_COMP_3_SHIFT 19
145 #define INTR_ERROR_MASK (INTR_MIF_STATUS | INTR_PCI_ERROR_STATUS | \
146 INTR_PCS_STATUS | INTR_RX_LEN_MISMATCH | \
147 INTR_TX_MAC_STATUS | INTR_RX_MAC_STATUS | \
148 INTR_TX_TAG_ERROR | INTR_RX_TAG_ERROR | \
149 INTR_MAC_CTRL_STATUS)
151 /* determines which status events will cause an interrupt. layout same
152 * as REG_INTR_STATUS.
153 * DEFAULT: 0xFFFFFFFF, SIZE: 16 bits
154 */
157 /* top level interrupt bits that are cleared during read of REG_INTR_STATUS_ALIAS.
158 * useful when driver is polling for interrupts. layout same as REG_INTR_MASK.
159 * DEFAULT: 0x00000000, SIZE: 12 bits
160 */
162 (used w/ status alias) */
163 /* same as REG_INTR_STATUS except that only bits cleared are those selected by
164 * REG_ALIAS_CLEAR
165 * DEFAULT: 0x00000000, SIZE: 29 bits
166 */
168 (selective clear) */
170 /* DEFAULT: 0x0, SIZE: 3 bits */
173 set if no ACK64# during ABS64 cycle
174 in Cassini. */
176 no read retry after 2^15 clocks */
179 unused in Cassini. */
181 unused in Cassini. */
183 DMA. unused in cassini. */
185 /* mask for PCI status events that will set PCI_ERR_STATUS. if cleared, event
186 * causes an interrupt to be generated.
187 * DEFAULT: 0x7, SIZE: 3 bits
188 */
191 /* used to configure PCI related parameters that are not in PCI config space.
192 * DEFAULT: 0bxx000, SIZE: 5 bits
193 */
205 reset. reserved in Cassini. */
207 reserved in Cassini. */
209 reserved in Cassini. */
211 /* DEFAULT: 0x00000000, SIZE: 32 bits */
214 machine bits [21:0] */
216 machine bits [6:0] */
218 /* writing to SW_RESET_TX and SW_RESET_RX will issue a global
219 * reset. poll until TX and RX read back as 0's for completion.
220 */
223 cleared to 0. */
225 cleared to 0. */
227 resets PHY and anything else
228 connected to RSTOUT#. RSTOUT#
229 is also activated by local PCI
230 reset when hot-swap is being
231 done. */
233 this bit set, PCS and SLINK
234 modules won't be reset.
235 i.e., link won't drop. */
238 0b000: ARB_IDLE1
239 0b001: ARB_IDLE2
240 0b010: ARB_WB_ACK
241 0b011: ARB_WB_WAT
242 0b100: ARB_RB_ACK
243 0b101: ARB_RB_WAT
244 0b110: ARB_RB_END
245 0b111: ARB_WB_END */
247 0b00: RD_PCI_WAT
248 0b01: RD_PCI_RDY
249 0b11: RD_PCI_ACK */
251 0b00: AD_IDL_RX
252 0b01: AD_ACK_RX
253 0b10: AD_ACK_TX
254 0b11: AD_IDL_TX */
256 0b00: WR_PCI_WAT
257 0b01: WR_PCI_RDY
258 0b11: WR_PCI_ACK */
260 0b000: ARB_IDLE1
261 0b001: ARB_IDLE2
262 0b010: ARB_TX_ACK
263 0b011: ARB_TX_WAT
264 0b100: ARB_RX_ACK
265 0b110: ARB_RX_WAT */
267 /* Cassini only. 64-bit register used to check PCI datapath. when read,
268 * value written has both lower and upper 32-bit halves rotated to the right
269 * one bit position. e.g., FFFFFFFF FFFFFFFF -> 7FFFFFFF 7FFFFFFF
270 */
272 Cassini+: reserved */
274 /* output enables are provided for each device's chip select and for the rest
275 * of the outputs from cassini to its local bus devices. two sw programmable
276 * bits are connected to general purpus control/status bits.
277 * DEFAULT: 0x7
278 */
280 output EN. default: 0x7 */
282 OE signal output enable on the
283 local bus interface. these
284 are shared between both local
285 bus devices. tristate when 0. */
288 select output enable */
293 /* access 24 entry BIM read and write buffers. put address in REG_BIM_BUFFER_ADDR
294 * and read/write from/to it REG_BIM_BUFFER_DATA_LOW and _DATA_HI.
295 * _DATA_HI should be the last access of the sequence.
296 * DEFAULT: undefined
297 */
299 purposes. */
302 read buffer access = 0 */
303 /* DEFAULT: undefined */
307 /* set BIM_RAM_BIST_START to start built-in self test for BIM read buffer.
308 * bit auto-clears when done with status read from _SUMMARY and _PASS bits.
309 */
311 control/status */
314 Cassini only. reserved in
315 Cassini+. */
317 buffer. */
319 buffer. Cassini only. reserved
320 in Cassini+. */
324 Cassini only. reserved in
325 Cassini+. */
327 Cassini only. reserved in
328 Cassini+. */
330 /* ASUN: i'm not sure what this does as it's not in the spec.
331 * DEFAULT: 0xFC
332 */
334 select register */
336 /* enable probe monitoring mode and select data appearing on the P_A* bus. bit
337 * values for _SEL_HI_MASK and _SEL_LOW_MASK:
338 * 0x0: internal probe[7:0] (pci arb state, wtc empty w, wtc full w, wtc empty w,
339 * wtc empty r, post pci)
340 * 0x1: internal probe[15:8] (pci wbuf comp, pci wpkt comp, pci rbuf comp,
341 * pci rpkt comp, txdma wr req, txdma wr ack,
342 * txdma wr rdy, txdma wr xfr done)
343 * 0x2: internal probe[23:16] (txdma rd req, txdma rd ack, txdma rd rdy, rxdma rd,
344 * rd arb state, rd pci state)
345 * 0x3: internal probe[31:24] (rxdma req, rxdma ack, rxdma rdy, wrarb state,
346 * wrpci state)
347 * 0x4: pci io probe[7:0] 0x5: pci io probe[15:8]
348 * 0x6: pci io probe[23:16] 0x7: pci io probe[31:24]
349 * 0x8: pci io probe[39:32] 0x9: pci io probe[47:40]
350 * 0xa: pci io probe[55:48] 0xb: pci io probe[63:56]
351 * the following are not available in Cassini:
352 * 0xc: rx probe[7:0] 0xd: tx probe[7:0]
353 * 0xe: hp probe[7:0] 0xf: mac probe[7:0]
354 */
357 driven on local bus P_A[15:0]
358 for debugging */
360 0x03 = mac[1:0]
361 0x0C = rx[1:0]
362 0x30 = tx[1:0]
363 0xC0 = hp[1:0] */
365 on P_A[15:8]. see above for
366 values. */
368 on P_A[7:0]. see above for
369 values. */
371 /* values mean the same thing as REG_INTR_MASK excep that it's for INTB.
372 DEFAULT: 0x1F */
374 register 2 for INTB */
375 #define REG_PLUS_INTRN_MASK(x) (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16)
376 /* bits correspond to both _MASK and _STATUS registers. _ALT corresponds to
377 * all of the alternate (2-4) INTR registers while _1 corresponds to only
378 * _MASK_1 and _STATUS_1 registers.
379 * DEFAULT: 0x7 for MASK registers, 0x0 for ALIAS_CLEAR registers
380 */
381 #define INTR_RX_DONE_ALT 0x01
382 #define INTR_RX_COMP_FULL_ALT 0x02
383 #define INTR_RX_COMP_AF_ALT 0x04
384 #define INTR_RX_BUF_UNAVAIL_1 0x08
386 #define INTRN_MASK_RX_EN 0x80
387 #define INTRN_MASK_CLEAR_ALL (INTR_RX_DONE_ALT | \
388 INTR_RX_COMP_FULL_ALT | \
389 INTR_RX_COMP_AF_ALT | \
390 INTR_RX_BUF_UNAVAIL_1 | \
391 INTR_RX_BUF_AE_1)
393 register 2 for INTB. default: 0x1F */
394 #define REG_PLUS_INTRN_STATUS(x) (REG_PLUS_INTR_STATUS_1 + ((x) - 1)*16)
396 flags are set. enables desc ring. */
399 register 2 for INTB */
400 #define REG_PLUS_ALIASN_CLEAR(x) (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16)
403 register alias 2 for INTB */
404 #define REG_PLUS_INTRN_STATUS_ALIAS(x) (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16)
407 integrated macphy */
415 0 = normal */
418 GMII on SERDES pins for
419 monitoring. */
421 pins configed as outputs.
422 for power saving when using
423 internal phy. */
425 polarity from strapping
426 value.
427 1 = mac core led ctrl
428 polarity active low. */
431 /** transmit dma registers **/
432 #define MAX_TX_RINGS_SHIFT 2
433 #define MAX_TX_RINGS (1 << MAX_TX_RINGS_SHIFT)
434 #define MAX_TX_RINGS_MASK (MAX_TX_RINGS - 1)
436 /* TX configuration.
437 * descr ring sizes size = 32 * (1 << n), n < 9. e.g., 0x8 = 8k. default: 0x8
438 * DEFAULT: 0x3F000001
439 */
442 will stop after xfer of current
443 buffer has been completed. */
445 accessed w/ FIFO addr
446 and data registers.
447 TX DMA should be
448 disabled. */
450 ring 1. */
451 #define TX_CFG_DESC_RING0_SHIFT 2
452 #define TX_CFG_DESC_RINGN_MASK(a) (TX_CFG_DESC_RING0_MASK << (a)*4)
453 #define TX_CFG_DESC_RINGN_SHIFT(a) (TX_CFG_DESC_RING0_SHIFT + (a)*4)
455 TX FIFO becomes empty.
456 if 0, TX_ALL set
457 if descr queue empty. */
460 the end of every packet kicked
461 through Q1. */
463 the end of every packet kicked
464 through Q2. */
466 the end of every packet kicked
467 through Q3 */
469 the end of every packet kicked
470 through Q4 */
472 writeback */
474 connection
475 0b00: tx mac req,
476 tx mac retry req,
477 tx ack and tx tag.
478 0b01: txdma rd req,
479 txdma rd ack,
480 txdma rd rdy,
481 txdma rd type0
482 0b11: txdma wr req,
483 txdma wr ack,
484 txdma wr rdy,
485 txdma wr xfr done. */
486 #define TX_CFG_CTX_SEL_SHIFT 30
488 /* 11-bit counters that point to next location in FIFO to be loaded/retrieved.
489 * used for diagnostics only.
490 */
493 pointer. temp hold reg.
494 diagnostics only. */
497 pointer */
499 /* (ro) 11-bit up/down counter w/ # of frames currently in TX FIFO */
502 /* current state of all state machines in TX */
507 = 0x01 when TX disabled. */
510 state machine */
518 /* 64-bit pointer to the transmit data buffer. only the 50 LSB are incremented
519 * while the upper 23 bits are taken from the TX descriptor
520 */
524 /* 13 bit registers written by driver w/ descriptor value that follows
525 * last valid xmit descriptor. kick # and complete # values are used by
526 * the xmit dma engine to control tx descr fetching. if > 1 valid
527 * tx descr is available within the cache line being read, cassini will
528 * internally cache up to 4 of them. 0 on reset. _KICK = rw, _COMP = ro.
529 */
531 #define REG_TX_KICKN(x) (REG_TX_KICK0 + (x)*4)
533 #define REG_TX_COMPN(x) (REG_TX_COMP0 + (x)*4)
535 /* values of TX_COMPLETE_1-4 are written. each completion register
536 * is 2bytes in size and contiguous. 8B allocation w/ 8B alignment.
537 * NOTE: completion reg values are only written back prior to TX_INTME and
538 * TX_ALL interrupts. at all other times, the most up-to-date index values
539 * should be obtained from the REG_TX_COMPLETE_# registers.
540 * here's the layout:
541 * offset from base addr completion # byte
542 * 0 TX_COMPLETE_1_MSB
543 * 1 TX_COMPLETE_1_LSB
544 * 2 TX_COMPLETE_2_MSB
545 * 3 TX_COMPLETE_2_LSB
546 * 4 TX_COMPLETE_3_MSB
547 * 5 TX_COMPLETE_3_LSB
548 * 6 TX_COMPLETE_4_MSB
549 * 7 TX_COMPLETE_4_LSB
550 */
551 #define TX_COMPWB_SIZE 8
553 base low */
555 base high */
556 #define TX_COMPWB_MSB_MASK 0x00000000000000FFULL
557 #define TX_COMPWB_MSB_SHIFT 0
558 #define TX_COMPWB_LSB_MASK 0x000000000000FF00ULL
559 #define TX_COMPWB_LSB_SHIFT 8
560 #define TX_COMPWB_NEXT(x) ((x) >> 16)
562 /* 53 MSB used as base address. 11 LSB assumed to be 0. TX desc pointer must
563 * be 2KB-aligned. */
566 #define REG_TX_DBN_LOW(x) (REG_TX_DB0_LOW + (x)*8)
567 #define REG_TX_DBN_HI(x) (REG_TX_DB0_HI + (x)*8)
569 /* 16-bit registers hold weights for the weighted round-robin of the
570 * four CBQ TX descr rings. weights correspond to # bytes xferred from
571 * host to TXFIFO in a round of WRR arbitration. can be set
572 * dynamically with new weights set upon completion of the current
573 * packet transfer from host memory to TXFIFO. a dummy write to any of
574 * these registers causes a queue1 pre-emption with all historical bw
575 * deficit data reset to 0 (useful when congestion requires a
576 * pre-emption/re-allocation of network bandwidth
577 */
583 /* diagnostics access to any TX FIFO location. every access is 65
584 * bits. _DATA_LOW = 32 LSB, _DATA_HI_T1/T0 = 32 MSB. _TAG = tag bit.
585 * writing _DATA_HI_T0 sets tag bit low, writing _DATA_HI_T1 sets tag
586 * bit high. TX_FIFO_PIO_SEL must be set for TX FIFO PIO access. if
587 * TX FIFO data integrity is desired, TX DMA should be
588 * disabled. _DATA_HI_Tx should be the last access of the sequence.
589 */
597 /* 9-bit register controls BIST of TX FIFO. bit set indicates that the BIST
598 * passed for the specified memory
599 */
602 controller state machine */
609 clears on completion. */
611 /** receive dma registers **/
612 #define MAX_RX_DESC_RINGS 2
613 #define MAX_RX_COMP_RINGS 4
615 /* receive DMA channel configuration. default: 0x80910
616 * free ring size = (1 << n)*32 -> [32 - 8k]
617 * completion ring size = (1 << n)*128 -> [128 - 32k], n < 9
618 * DEFAULT: 0x80910
619 */
622 channel as soon as current
623 frame xfer has completed.
624 driver should disable MAC
625 for 200ms before disabling
626 RX */
628 free desc ring.
629 def: 0x8 = 8k */
630 #define RX_CFG_DESC_RING_SHIFT 1
632 ring. def: 0x8 = 32k */
633 #define RX_CFG_COMP_RING_SHIFT 5
635 batching. def: 0x0 =
636 enabled */
638 data byte of the packet
639 w/in 8 byte boundares.
640 this swivels the data
641 DMA'ed to header
642 buffers, jumbo buffers
643 when header split is not
644 requested and MTU sized
645 buffers. def: 0x2 */
646 #define RX_CFG_SWIVEL_SHIFT 10
648 /* cassini+ only */
650 RX free desc ring 2.
651 def: 0x8 = 8k */
652 #define RX_CFG_DESC_RING1_SHIFT 16
655 /* the page size register allows cassini chips to do the following with
656 * received data:
657 * [--------------------------------------------------------------] page
658 * [off][buf1][pad][off][buf2][pad][off][buf3][pad][off][buf4][pad]
659 * |--------------| = PAGE_SIZE_BUFFER_STRIDE
660 * page = PAGE_SIZE
661 * offset = PAGE_SIZE_MTU_OFF
662 * for the above example, MTU_BUFFER_COUNT = 4.
663 * NOTE: as is apparent, you need to ensure that the following holds:
664 * MTU_BUFFER_COUNT <= PAGE_SIZE/PAGE_SIZE_BUFFER_STRIDE
665 * DEFAULT: 0x48002002 (8k pages)
666 */
669 by receive descriptors.
670 if jumbo buffers are
671 supported the page size
672 should not be < 8k.
673 0b00 = 2k, 0b01 = 4k
674 0b10 = 8k, 0b11 = 16k
675 DEFAULT: 8k */
676 #define RX_PAGE_SIZE_SHIFT 0
678 packs into a page.
679 DEFAULT: 4 */
680 #define RX_PAGE_SIZE_MTU_COUNT_SHIFT 11
682 each MTU buffer +
683 offset from each
684 other.
685 0b00 = 1k, 0b01 = 2k
686 0b10 = 4k, 0b11 = 8k
687 DEFAULT: 0x1 */
688 #define RX_PAGE_SIZE_MTU_STRIDE_SHIFT 27
690 hw writes the MTU buffer
691 into.
692 0b00 = 0,
693 0b01 = 64 bytes
694 0b10 = 96, 0b11 = 128
695 DEFAULT: 0x1 */
696 #define RX_PAGE_SIZE_MTU_OFF_SHIFT 30
698 /* 11-bit counter points to next location in RX FIFO to be loaded/read.
699 * shadow write pointers enable retries in case of early receive aborts.
700 * DEFAULT: 0x0. generated on 64-bit boundaries.
701 */
705 pointer */
707 pointer */
709 pointer. (8-bit counter) */
711 /* current state of RX DMA state engines + other info
712 * DEFAULT: 0x0
713 */
716 0x0 = idle, 0x1 = load_bop
717 0x2 = load 1, 0x3 = load 2
718 0x4 = load 3, 0x5 = load 4
719 0x6 = last detect
720 0x7 = wait req
721 0x8 = wait req statuss 1st
722 0x9 = load st
723 0xa = bubble mac
724 0xb = error */
726 RX FIFO:
727 0x0 = idle, 0x1 = hp xfr
728 0x2 = wait hp ready
729 0x3 = wait flow code
730 0x4 = fifo xfer
731 0x5 = make status
732 0x6 = csum ready
733 0x7 = error */
735 w/ MAC:
736 0x0 = idle
737 0x1 = wait xoff ack
738 0x2 = wait xon
739 0x3 = wait xon ack */
741 states:
742 0x0 = idle data
743 0x1 = header begin
744 0x2 = xfer header
745 0x3 = xfer header ld
746 0x4 = mtu begin
747 0x5 = xfer mtu
748 0x6 = xfer mtu ld
749 0x7 = jumbo begin
750 0x8 = xfer jumbo
751 0x9 = xfer jumbo ld
752 0xa = reas begin
753 0xb = xfer reas
754 0xc = flush tag
755 0xd = xfer reas ld
756 0xe = error
757 0xf = bubble idle */
759 states:
760 0x0 = idle desc
761 0x1 = wait ack
762 0x9 = wait ack 2
763 0x2 = fetch desc 1
764 0xa = fetch desc 2
765 0x3 = load ptrs
766 0x4 = wait dma
767 0x5 = wait ack batch
768 0x6 = post batch
769 0x7 = xfr done */
771 interrupt queue */
773 of the interrupt queue */
775 /* flow control frames are emmitted using two PAUSE thresholds:
776 * XOFF PAUSE uses pause time value pre-programmed in the Send PAUSE MAC reg
777 * XON PAUSE uses a pause time of 0. granularity of threshold is 64bytes.
778 * PAUSE thresholds defined in terms of FIFO occupancy and may be translated
779 * into FIFO vacancy using RX_FIFO_SIZE. setting ON will trigger XON frames
780 * when FIFO reaches 0. OFF threshold should not be > size of RX FIFO. max
781 * value is is 0x6F.
782 * DEFAULT: 0x00078
783 */
785 #define RX_PAUSE_THRESH_QUANTUM 64
787 RX FIFO occupancy >
788 value*64B */
789 #define RX_PAUSE_THRESH_OFF_SHIFT 0
791 emitting XOFF PAUSE when RX
792 FIFO occupancy falls below
793 this value*64B. must be
794 < XOFF threshold. if =
795 RX_FIFO_SIZE< XON frames are
796 never emitted. */
797 #define RX_PAUSE_THRESH_ON_SHIFT 12
799 /* 13-bit register used to control RX desc fetching and intr generation. if 4+
800 * valid RX descriptors are available, Cassini will read 4 at a time.
801 * writing N means that all desc up to *but* excluding N are available. N must
802 * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned.
803 * DEFAULT: 0 on reset
804 */
807 /* 8KB aligned 64-bit pointer to the base of the RX free/completion rings.
808 * lower 13 bits of the low register are hard-wired to 0.
809 */
811 base low */
813 base hi */
815 base low */
817 base hi */
818 /* 13-bit register indicate desc used by cassini for receive frames. used
819 * for diagnostic purposes.
820 * DEFAULT: 0 on reset
821 */
824 /* HEAD and TAIL are used to control RX desc posting and interrupt
825 * generation. hw moves the head register to pass ownership to sw. sw
826 * moves the tail register to pass ownership back to hw. to give all
827 * entries to hw, set TAIL = HEAD. if HEAD and TAIL indicate that no
828 * more entries are available, DMA will pause and an interrupt will be
829 * generated to indicate no more entries are available. sw can use
830 * this interrupt to reduce the # of times it must update the
831 * completion tail register.
832 * DEFAULT: 0 on reset
833 */
837 /* values used for receive interrupt blanking. loaded each time the ISR is read
838 * DEFAULT: 0x00000000
839 */
841 for ISR read */
843 this many sets of completion
844 writebacks (up to 2 packets)
845 occur since the last time
846 the ISR was read. 0 = no
847 packet blanking */
848 #define RX_BLANK_INTR_PKT_SHIFT 0
850 if that many clocks were
851 counted since last time the
852 ISR was read.
853 each count is 512 core
854 clocks (125MHz). 0 = no
855 time blanking */
856 #define RX_BLANK_INTR_TIME_SHIFT 12
858 /* values used for interrupt generation based on threshold values of how
859 * many free desc and completion entries are available for hw use.
860 * DEFAULT: 0x00000000
861 */
863 thresholds */
865 generated if # desc
866 avail for hw use <=
867 # */
868 #define RX_AE_THRESH_FREE_SHIFT 0
870 generated if # of
871 completion entries
872 avail for hw use <=
873 # */
874 #define RX_AE_THRESH_COMP_SHIFT 13
876 /* probabilities for random early drop (RED) thresholds on a FIFO threshold
877 * basis. probability should increase when the FIFO level increases. control
878 * packets are never dropped and not counted in stats. probability programmed
879 * on a 12.5% granularity. e.g., 0x1 = 1/8 packets dropped.
880 * DEFAULT: 0x00000000
881 */
888 /* FIFO fullness levels for RX FIFO, RX control FIFO, and RX IPP FIFO.
889 * RX control FIFO = # of packets in RX FIFO.
890 * DEFAULT: 0x0
891 */
899 high */
921 summary pass bit
922 contains AND of BIST
923 results of all 16
924 RAMS */
926 BIST. self clears
927 on completion. */
929 /* next location in RX CTRL FIFO that will be loaded w/ data from RX IPP/read
930 * from to retrieve packet control info.
931 * DEFAULT: 0
932 */
934 write ptr */
936 ptr */
938 /* receive interrupt blanking. loaded each time interrupt alias register is
939 * read.
940 * DEFAULT: 0x0
941 */
943 alias read */
945 completion writebacks
946 > # since last ISR
947 read. 0 = no
948 blanking. up to 2
949 packets per
950 completion wb. */
952 clocks > # since last
953 ISR read. each count
954 is 512 core clocks
955 (125MHz). 0 = no
956 blanking. */
958 /* diagnostic access to RX FIFO. 32 LSB accessed via DATA_LOW. 32 MSB accessed
959 * via DATA_HI_T0 or DATA_HI_T1. TAG reads the tag bit. writing HI_T0
960 * will unset the tag bit while writing HI_T1 will set the tag bit. to reset
961 * to normal operation after diagnostics, write to address location 0x0.
962 * RX_DMA_EN bit must be set to 0x0 for RX FIFO PIO access. DATA_HI should
963 * be the last write access of a write sequence.
964 * DEFAULT: undefined
965 */
972 /* diagnostic assess to RX CTRL FIFO. 8-bit FIFO_ADDR holds address of
973 * 81 bit control entry and 6 bit flow id. LOW and MID are both 32-bit
974 * accesses. HI is 7-bits with 6-bit flow id and 1 bit control
975 * word. RX_DMA_EN must be 0 for RX CTRL FIFO PIO access. DATA_HI
976 * should be last write access of the write sequence.
977 * DEFAULT: undefined
978 */
980 Batching FIFO addr */
982 low */
984 mid */
986 hi and flow id */
990 /* diagnostic access to RX IPP FIFO. same semantics as RX_FIFO.
991 * DEFAULT: undefined
992 */
997 T0 */
999 T1 */
1001 /* 64-bit pointer to receive data buffer in host memory used for headers and
1002 * small packets. MSB in high register. loaded by DMA state machine and
1003 * increments as DMA writes receive data. only 50 LSB are incremented. top
1004 * 13 bits taken from RX descriptor.
1005 * DEFAULT: undefined
1006 */
1008 low */
1010 high */
1012 low */
1014 high */
1016 /* PIO diagnostic access to RX reassembly DMA Table RAM. 6-bit register holds
1017 * one of 64 79-bit locations in the RX Reassembly DMA table and the addr of
1018 * one of the 64 byte locations in the Batching table. LOW holds 32 LSB.
1019 * MID holds the next 32 LSB. HIGH holds the 15 MSB. RX_DMA_EN must be set
1020 * to 0 for PIO access. DATA_HIGH should be last write of write sequence.
1021 * layout:
1022 * reassmbl ptr [78:15] | reassmbl index [14:1] | reassmbl entry valid [0]
1023 * DEFAULT: undefined
1024 */
1026 address */
1030 data low */
1032 data mid */
1034 data high */
1036 /* cassini+ only */
1037 /* 8KB aligned 64-bit pointer to base of RX rings. lower 13 bits hardwired to
1038 * 0. same semantics as primary desc/complete rings.
1039 */
1041 2 base low */
1043 2 base high */
1045 2 base low. 4 total */
1047 2 base high. 4 total */
1048 #define REG_PLUS_RX_CBN_LOW(x) (REG_PLUS_RX_CB1_LOW + 8*((x) - 1))
1049 #define REG_PLUS_RX_CBN_HI(x) (REG_PLUS_RX_CB1_HI + 8*((x) - 1))
1052 reg */
1054 head reg. 4 total. */
1056 tail reg. 4 total. */
1057 #define REG_PLUS_RX_COMPN_HEAD(x) (REG_PLUS_RX_COMP1_HEAD + 8*((x) - 1))
1058 #define REG_PLUS_RX_COMPN_TAIL(x) (REG_PLUS_RX_COMP1_TAIL + 8*((x) - 1))
1060 thresholds */
1061 #define RX_AE1_THRESH_FREE_MASK RX_AE_THRESH_FREE_MASK
1062 #define RX_AE1_THRESH_FREE_SHIFT RX_AE_THRESH_FREE_SHIFT
1064 /** header parser registers **/
1066 /* RX parser configuration register.
1067 * DEFAULT: 0x1651004
1068 */
1070 configuration reg */
1073 0 = 64. 0x3f = 63 */
1074 #define HP_CFG_NUM_CPU_SHIFT 2
1076 TCP seq # by one when
1077 stored in FDBM */
1079 needed to be considered
1080 for reassembly */
1081 #define HP_CFG_TCP_THRESH_SHIFT 9
1083 /* access to RX Instruction RAM. 5-bit register/counter holds addr
1084 * of 39 bit entry to be read/written. 32 LSB in _DATA_LOW. 7 MSB in _DATA_HI.
1085 * RX_DMA_EN must be 0 for RX instr PIO access. DATA_HI should be last access
1086 * of sequence.
1087 * DEFAULT: undefined
1088 */
1090 address */
1093 data low */
1094 #define HP_INSTR_RAM_LOW_OUTMASK_MASK 0x0000FFFF
1095 #define HP_INSTR_RAM_LOW_OUTMASK_SHIFT 0
1096 #define HP_INSTR_RAM_LOW_OUTSHIFT_MASK 0x000F0000
1097 #define HP_INSTR_RAM_LOW_OUTSHIFT_SHIFT 16
1098 #define HP_INSTR_RAM_LOW_OUTEN_MASK 0x00300000
1099 #define HP_INSTR_RAM_LOW_OUTEN_SHIFT 20
1100 #define HP_INSTR_RAM_LOW_OUTARG_MASK 0xFFC00000
1101 #define HP_INSTR_RAM_LOW_OUTARG_SHIFT 22
1103 data mid */
1104 #define HP_INSTR_RAM_MID_OUTARG_MASK 0x00000003
1105 #define HP_INSTR_RAM_MID_OUTARG_SHIFT 0
1106 #define HP_INSTR_RAM_MID_OUTOP_MASK 0x0000003C
1107 #define HP_INSTR_RAM_MID_OUTOP_SHIFT 2
1108 #define HP_INSTR_RAM_MID_FNEXT_MASK 0x000007C0
1109 #define HP_INSTR_RAM_MID_FNEXT_SHIFT 6
1110 #define HP_INSTR_RAM_MID_FOFF_MASK 0x0003F800
1111 #define HP_INSTR_RAM_MID_FOFF_SHIFT 11
1112 #define HP_INSTR_RAM_MID_SNEXT_MASK 0x007C0000
1113 #define HP_INSTR_RAM_MID_SNEXT_SHIFT 18
1114 #define HP_INSTR_RAM_MID_SOFF_MASK 0x3F800000
1115 #define HP_INSTR_RAM_MID_SOFF_SHIFT 23
1116 #define HP_INSTR_RAM_MID_OP_MASK 0xC0000000
1117 #define HP_INSTR_RAM_MID_OP_SHIFT 30
1119 data high */
1120 #define HP_INSTR_RAM_HI_VAL_MASK 0x0000FFFF
1121 #define HP_INSTR_RAM_HI_VAL_SHIFT 0
1122 #define HP_INSTR_RAM_HI_MASK_MASK 0xFFFF0000
1123 #define HP_INSTR_RAM_HI_MASK_SHIFT 16
1125 /* PIO access into RX Header parser data RAM and flow database.
1126 * 11-bit register. Data fills the LSB portion of bus if less than 32 bits.
1127 * DATA_RAM: write RAM_FDB_DATA with index to access DATA_RAM.
1128 * RAM bytes = 4*(x - 1) + [3:0]. e.g., 0 -> [3:0], 31 -> [123:120]
1129 * FLOWDB: write DATA_RAM_FDB register and then read/write FDB1-12 to access
1130 * flow database.
1131 * RX_DMA_EN must be 0 for RX parser RAM PIO access. RX Parser RAM data reg
1132 * should be the last write access of the write sequence.
1133 * DEFAULT: undefined
1134 */
1136 RAM address */
1138 locations in header
1139 parser data ram to
1140 read/write */
1142 in the flow database */
1145 /* HP flow database registers: 1 - 12, 0x415C - 0x4188, 4 8-bit bytes
1146 * FLOW_DB(1) = IP_SA[127:96], FLOW_DB(2) = IP_SA[95:64]
1147 * FLOW_DB(3) = IP_SA[63:32], FLOW_DB(4) = IP_SA[31:0]
1148 * FLOW_DB(5) = IP_DA[127:96], FLOW_DB(6) = IP_DA[95:64]
1149 * FLOW_DB(7) = IP_DA[63:32], FLOW_DB(8) = IP_DA[31:0]
1150 * FLOW_DB(9) = {TCP_SP[15:0],TCP_DP[15:0]}
1151 * FLOW_DB(10) = bit 0 has value for flow valid
1152 * FLOW_DB(11) = TCP_SEQ[63:32], FLOW_DB(12) = TCP_SEQ[31:0]
1153 */
1155 #define REG_HP_FLOW_DBN(x) (REG_HP_FLOW_DB0 + (x)*4)
1157 /* diagnostics for RX Header Parser block.
1158 * ASUN: the header parser state machine register is used for diagnostics
1159 * purposes. however, the spec doesn't have any details on it.
1160 */
1166 number */
1178 start offset */
1182 reassembly */
1184 enable */
1186 check */
1188 equal to zero */
1190 chk */
1192 threshold */
1200 /* BIST for header parser(HP) and flow database memories (FDBM). set _START
1201 * to start BIST. controller clears _START on completion. _START can also
1202 * be cleared to force termination of BIST. a bit set indicates that that
1203 * memory passed its BIST.
1204 */
1213 bank 0 */
1215 bank 0 */
1217 bank 0 */
1219 bank 0 */
1221 bank 1 */
1223 bank 2 */
1225 bank 1 */
1227 bank 1 */
1229 RAM */
1234 /** MAC registers. **/
1235 /* reset bits are set using a PIO write and self-cleared after the command
1236 * execution has completed.
1237 */
1239 command (default: 0x0) */
1241 command (default: 0x0) */
1242 /* execute a pause flow control frame transmission
1243 DEFAULT: 0x0XXXX */
1246 to be sent on network
1247 in units of slot
1248 times */
1250 frame on network */
1252 /* bit set indicates that event occurred. auto-cleared when status register
1253 * is read and have corresponding mask bits in mask register. events will
1254 * trigger an interrupt if the corresponding mask bit is 0.
1255 * status register default: 0x00000000
1256 * mask register default = 0xFFFFFFFF on reset
1257 */
1260 transmision */
1262 transmission due to
1263 data starvation in the
1264 xmit data path */
1266 length passed to TX MAC
1267 by the DMA engine */
1269 collision counter */
1271 collision counter */
1273 collision counter */
1275 collision counter */
1277 timer */
1279 attempts counter */
1283 a frame */
1285 RX FIFO overflow */
1287 counter */
1289 error counter */
1291 counter */
1293 error counter */
1295 violation error */
1297 /* DEFAULT: 0xXXXX0000 on reset */
1300 reception of a
1301 pause control
1302 frame */
1304 transition from
1305 "not paused" to
1306 "paused" */
1308 transition from
1309 "paused" to "not
1310 paused" */
1312 operand that was
1313 received in the last
1314 pause flow control
1315 frame */
1317 /* layout identical to TX MAC[8:0] */
1319 /* layout identical to RX MAC[6:0] */
1321 /* layout identical to CTRL MAC[2:0] */
1324 /* to ensure proper operation, CFG_EN must be cleared to 0 and a delay
1325 * imposed before writes to other bits in the TX_MAC_CFG register or any of
1326 * the MAC parameters is performed. delay dependent upon time required to
1327 * transmit a maximum size frame (= MAC_FRAMESIZE_MAX*8/Mbps). e.g.,
1328 * the delay for a 1518-byte frame on a 100Mbps network is 125us.
1329 * alternatively, just poll TX_CFG_EN until it reads back as 0.
1330 * NOTE: on half-duplex 1Gbps, TX_CFG_CARRIER_EXTEND and
1331 * RX_CFG_CARRIER_EXTEND should be set and the SLOT_TIME register should
1332 * be 0x200 (slot time of 512 bytes)
1333 */
1336 force TXMAC state
1337 machine to remain in
1338 idle state or to
1339 transition to idle state
1340 on completion of an
1341 ongoing packet. */
1343 process. set to 1 when
1344 full duplex and 0 when
1345 half duplex */
1347 algorithm. set to 1 when
1348 full duplex and 0 when
1349 half duplex */
1351 Rx-to-TX IPG. after
1352 receiving a frame, TX
1353 MAC will reset its
1354 deferral process to
1355 carrier sense for the
1356 amount of time = IPG0 +
1357 IPG1 and commit to
1358 transmission for time
1359 specified in IPG2. when
1360 0 or when xmitting frames
1361 back-to-pack (Tx-to-Tx
1362 IPG), TX MAC ignores
1363 IPG0 and will only use
1364 IPG1 for deferral time.
1365 IPG2 still used. */
1367 give up on frame
1368 xmission. if backoff
1369 algorithm reaches the
1370 ATTEMPT_LIMIT, it will
1371 clear attempts counter
1372 and continue trying to
1373 send the frame as
1374 specified by
1375 GIVE_UP_LIM. when 0,
1376 TX MAC will execute
1377 standard CSMA/CD prot. */
1379 continue to try to xmit
1380 until successful. when
1381 0, TX MAC will continue
1382 to try xmitting until
1383 successful or backoff
1384 algorithm reaches
1385 ATTEMPT_LIMIT*16 */
1387 backoff algorithm. TX
1388 MAC will not back off
1389 after a xmission attempt
1390 that resulted in a
1391 collision. */
1393 deferral process is reset
1394 in response to carrier
1395 sense during the entire
1396 duration of IPG. TX MAC
1397 will only commit to frame
1398 xmission after frame
1399 xmission has actually
1400 begun. */
1402 CRC for all xmitted
1403 packets. when clear, CRC
1404 generation is dependent
1405 upon NO_CRC bit in the
1406 xmit control word from
1407 TX DMA */
1409 carrier extension
1410 feature. this allows for
1411 longer collision domains
1412 by extending the carrier
1413 and collision window
1414 from the end of FCS until
1415 the end of the slot time
1416 if necessary. Required
1417 for half-duplex at 1Gbps,
1418 clear otherwise. */
1420 /* when CRC is not stripped, reassembly packets will not contain the CRC.
1421 * these will be stripped by HRP because it reassembles layer 4 data, and the
1422 * CRC is layer 2. however, non-reassembly packets will still contain the CRC
1423 * when passed to the host. to ensure proper operation, need to wait 3.2ms
1424 * after clearing RX_CFG_EN before writing to any other RX MAC registers
1425 * or other MAC parameters. alternatively, poll RX_CFG_EN until it clears
1426 * to 0. similary, HASH_FILTER_EN and ADDR_FILTER_EN have the same
1427 * restrictions as CFG_EN.
1428 */
1432 feature not supported */
1434 last 4 bytes of a
1435 received frame. */
1438 multicast frames (group
1439 bit in DA field set) */
1441 multicast addresses */
1443 address filtering regs
1444 to filter both unicast
1445 and multicast
1446 addresses */
1448 RX DMA by setting BAD
1449 bit but not Abort bit
1450 in the status. CRC,
1451 framing, and length errs
1452 will not increment
1453 error counters. frames
1454 which don't match dest
1455 addr will be passed up
1456 w/ BAD bit set. */
1458 packet bursts generated
1459 by carrier extension
1460 with packet bursting
1461 senders. only applies
1462 to half-duplex 1Gbps */
1464 /* DEFAULT: 0x0 */
1467 sending pause flow ctrl
1468 frames */
1470 pause flow ctrl frames */
1472 packets to RX DMA */
1474 /* to ensure proper operation, a global initialization sequence should be
1475 * performed when a loopback config is entered or exited. if programmed after
1476 * a hw or global sw reset, RX/TX MAC software reset and initialization
1477 * should be done to ensure stable clocking.
1478 * DEFAULT: 0x0
1479 */
1482 on MII xmit bus */
1484 path to GMII recv data
1485 path. phy mode register
1486 clock selection must be
1487 set to GMII mode and
1488 GMII_MODE should be set
1489 to 1. in loopback mode,
1490 REFCLK will drive the
1491 entire mac core. 0 for
1492 normal operation. */
1494 path during packet
1495 xmission. clear to 0
1496 in any full duplex mode,
1497 in any loopback mode,
1498 or in half-duplex SERDES
1499 or SLINK modes. set when
1500 in half-duplex when
1501 using external phy. */
1503 clocks and datapath */
1505 external tristate buffer
1506 on the MII receive
1507 bus. */
1512 recommended: 0x00 */
1514 recommended: 0x08 */
1516 recommended: 0x04 */
1518 recommended: 0x40 */
1520 recommended: 0x40 */
1522 /* FRAMESIZE_MAX holds both the max frame size as well as the max burst size.
1523 * recommended value: 0x2000.05EE
1524 */
1527 #define MAC_FRAMESIZE_MAX_BURST_SHIFT 16
1529 #define MAC_FRAMESIZE_MAX_FRAME_SHIFT 0
1531 preamble bytes that the
1532 TX MAC will xmit at the
1533 beginning of each frame
1534 value should be 2 or
1535 greater. recommended
1536 value: 0x07 */
1538 of jam in units of media
1539 byte time. recommended
1540 value: 0x04 */
1542 of attempts TX MAC will
1543 make to xmit a frame
1544 before it resets its
1545 attempts counter. after
1546 the limit has been
1547 reached, TX MAC may or
1548 may not drop the frame
1549 dependent upon value
1550 in TX_MAC_CFG.
1551 recommended
1552 value: 0x10 */
1554 type field of a MAC
1555 ctrl frame. recommended
1556 value: 0x8808 */
1558 /* mac address registers: 0 - 44, 0x6080 - 0x6130, 4 8-bit bytes.
1559 * register contains comparison
1560 * 0 16 MSB of primary MAC addr [47:32] of DA field
1561 * 1 16 middle bits "" [31:16] of DA field
1562 * 2 16 LSB "" [15:0] of DA field
1563 * 3*x 16MSB of alt MAC addr 1-15 [47:32] of DA field
1564 * 4*x 16 middle bits "" [31:16]
1565 * 5*x 16 LSB "" [15:0]
1566 * 42 16 MSB of MAC CTRL addr [47:32] of DA.
1567 * 43 16 middle bits "" [31:16]
1568 * 44 16 LSB "" [15:0]
1569 * MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames.
1570 * if there is a match, MAC will set the bit for alternative address
1571 * filter pass [15]
1573 * here is the map of registers given MAC address notation: a:b:c:d:e:f
1574 * ab cd ef
1575 * primary addr reg 2 reg 1 reg 0
1576 * alt addr 1 reg 5 reg 4 reg 3
1577 * alt addr x reg 5*x reg 4*x reg 3*x
1578 * ctrl addr reg 44 reg 43 reg 42
1579 */
1581 #define REG_MAC_ADDRN(x) (REG_MAC_ADDR0 + (x)*4)
1583 [47:32] */
1585 [31:16] */
1587 [15:0] */
1589 mask reg. 8-bit reg
1590 contains nibble mask for
1591 reg 2 and 1. */
1593 reg */
1595 /* hash table registers: 0 - 15, 0x6160 - 0x619C, 4 8-bit bytes
1596 * 16-bit registers contain bits of the hash table.
1597 * reg x -> [16*(15 - x) + 15 : 16*(15 - x)].
1598 * e.g., 15 -> [15:0], 0 -> [255:240]
1599 */
1601 #define REG_MAC_HASH_TABLEN(x) (REG_MAC_HASH_TABLE0 + (x)*4)
1603 /* statistics registers. these registers generate an interrupt on
1604 * overflow. recommended initialization: 0x0000. most are 16-bits except
1605 * for PEAK_ATTEMPTS register which is 8 bits.
1606 */
1608 counter. */
1610 successful collision
1611 counter */
1613 counter */
1616 is the media byte
1617 clock/256 */
1624 error counter */
1626 /* misc registers */
1628 10-bit register used as a
1629 seed for the random number
1630 generator for the CSMA/CD
1631 backoff algorithm. only
1632 programmed after power-on
1633 reset and should be a
1634 random value which has a
1635 high likelihood of being
1636 unique for each MAC
1637 attached to a network
1638 segment (e.g., 10 LSB of
1639 MAC address) */
1641 /* ASUN: there's a PAUSE_TIMER (ro) described, but it's not in the address
1642 * map
1643 */
1645 /* 27-bit register has the current state for key state machines in the MAC */
1647 #define MAC_SM_RLM_MASK 0x07800000
1648 #define MAC_SM_RLM_SHIFT 23
1649 #define MAC_SM_RX_FC_MASK 0x00700000
1650 #define MAC_SM_RX_FC_SHIFT 20
1651 #define MAC_SM_TLM_MASK 0x000F0000
1652 #define MAC_SM_TLM_SHIFT 16
1653 #define MAC_SM_ENCAP_SM_MASK 0x0000F000
1654 #define MAC_SM_ENCAP_SM_SHIFT 12
1655 #define MAC_SM_TX_REQ_MASK 0x00000C00
1656 #define MAC_SM_TX_REQ_SHIFT 10
1657 #define MAC_SM_TX_FC_MASK 0x000003C0
1658 #define MAC_SM_TX_FC_SHIFT 6
1659 #define MAC_SM_FIFO_WRITE_SEL_MASK 0x00000038
1660 #define MAC_SM_FIFO_WRITE_SEL_SHIFT 3
1661 #define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007
1662 #define MAC_SM_TX_FIFO_EMPTY_SHIFT 0
1664 /** MIF registers. the MIF can be programmed in either bit-bang or
1665 * frame mode.
1666 **/
1668 1 -> 0 will generate a
1669 rising edge. 0 -> 1 will
1670 generate a falling edge. */
1672 register generates data */
1674 enable. enable when
1675 xmitting data from MIF to
1676 transceiver. */
1678 /* 32-bit register serves as an instruction register when the MIF is
1679 * programmed in frame mode. load this register w/ a valid instruction
1680 * (as per IEEE 802.3u MII spec). poll this register to check for instruction
1681 * execution completion. during a read operation, this register will also
1682 * contain the 16-bit data returned by the tranceiver. unless specified
1683 * otherwise, fields are considered "don't care" when polling for
1684 * completion.
1685 */
1688 load w/ 01 when
1689 issuing an instr */
1692 write. 10 for a
1693 read */
1697 issuing an instr,
1698 this field should be
1699 loaded w/ the XCVR
1700 addr */
1701 #define MIF_FRAME_PHY_ADDR_SHIFT 23
1703 when issuing an instr,
1704 addr of register
1705 to be read/written */
1706 #define MIF_FRAME_REG_ADDR_SHIFT 18
1708 when issuing an instr,
1709 set this bit to 1 */
1711 when issuing an instr,
1712 set this bit to 0.
1713 when polling for
1714 completion, 1 means
1715 that instr execution
1716 has been completed */
1718 load with 16-bit data
1719 to be written in
1720 transceiver reg for a
1721 write. doesn't matter
1722 in a read. when
1723 polling for
1724 completion, field is
1725 "don't care" for write
1726 and 16-bit data
1727 returned by the
1728 transceiver for a
1729 read (if valid bit
1730 is set) */
1733 0 -> select MDIO_0 */
1735 mechanism. if set,
1736 BB_MODE should be 0 */
1738 0 -> frame mode */
1740 used by polling mode.
1741 only meaningful if POLL_EN
1742 is set to 1 */
1743 #define MIF_CFG_POLL_REG_SHIFT 3
1745 when MDIO_0 is idle,
1746 1 -> tranceiver is
1747 connected to MDIO_0.
1748 when MIF is communicating
1749 w/ MDIO_0 in bit-bang
1750 mode, this bit indicates
1751 the incoming bit stream
1752 during a read op */
1754 when MDIO_1 is idle,
1755 1 -> transceiver is
1756 connected to MDIO_1.
1757 when MIF is communicating
1758 w/ MDIO_1 in bit-bang
1759 mode, this bit indicates
1760 the incoming bit stream
1761 during a read op */
1763 be polled */
1764 #define MIF_CFG_POLL_PHY_SHIFT 10
1766 /* 16-bit register used to determine which bits in the POLL_STATUS portion of
1767 * the MIF_STATUS register will cause an interrupt. if a mask bit is 0,
1768 * corresponding bit of the POLL_STATUS will generate a MIF interrupt when
1769 * set. DEFAULT: 0xFFFF
1770 */
1773 /* 32-bit register used when in poll mode. auto-cleared after being read */
1776 the "latest image"
1777 update of the XCVR
1778 reg being read */
1779 #define MIF_STATUS_POLL_DATA_SHIFT 16
1781 which bits in the
1782 POLL_DATA field have
1783 changed since the
1784 MIF_STATUS reg was
1785 last read */
1786 #define MIF_STATUS_POLL_STATUS_SHIFT 0
1788 /* 7-bit register has current state for all state machines in the MIF */
1791 state */
1793 state */
1795 /** PCS/Serialink. the following registers are equivalent to the standard
1796 * MII management registers except that they're directly mapped in
1797 * Cassini's register space.
1798 **/
1800 /* the auto-negotiation enable bit should be programmed the same at
1801 * the link partner as in the local device to enable auto-negotiation to
1802 * complete. when that bit is reprogrammed, auto-neg/manual config is
1803 * restarted automatically.
1804 * DEFAULT: 0x1040
1805 */
1808 writes */
1810 to MAC interface is
1811 activated regardless
1812 of activity */
1814 behaviour same for
1815 half and full dplx */
1817 restart auto-
1818 negotiation */
1820 on writes */
1822 on writes */
1824 through automatic
1825 link config before it
1826 can be used. when 0,
1827 link can be used
1828 w/out any link config
1829 phase */
1831 writes */
1833 when done */
1835 /* DEFAULT: 0x0108 */
1840 0 -> link down. 0 is
1841 latched so that 0 is
1842 kept until read. read
1843 2x to determine if the
1844 link has gone up again */
1846 auto-neg) */
1848 from received link code
1849 word. only valid after
1850 auto-neg completed */
1852 completed
1853 0 -> auto-negotiation not
1854 completed */
1856 indication that this is
1857 a 1000 Base-X PHY. writes
1858 to it are ignored */
1860 /* used during auto-negotiation.
1861 * DEFAULT: 0x00E0
1862 */
1864 reg */
1866 1000 Base-X */
1868 1000 Base-X */
1870 symmetric capability */
1872 asymmetric capability */
1874 to optionally indicate to
1875 link partner that chip is
1876 going off-line. bit12 will
1877 get set when signal
1878 detect == FAIL and will
1879 remain set until
1880 successful negotiation */
1884 /* contents updated as a result of autonegotiation. layout and definitions
1885 * identical to PCS_MII_ADVERT
1886 */
1888 ability reg */
1889 #define PCS_MII_LPA_FD PCS_MII_ADVERT_FD
1890 #define PCS_MII_LPA_HD PCS_MII_ADVERT_HD
1891 #define PCS_MII_LPA_SYM_PAUSE PCS_MII_ADVERT_SYM_PAUSE
1892 #define PCS_MII_LPA_ASYM_PAUSE PCS_MII_ADVERT_ASYM_PAUSE
1893 #define PCS_MII_LPA_RF_MASK PCS_MII_ADVERT_RF_MASK
1894 #define PCS_MII_LPA_ACK PCS_MII_ADVERT_ACK
1895 #define PCS_MII_LPA_NEXT_PAGE PCS_MII_ADVERT_NEXT_PAGE
1897 /* DEFAULT: 0x0 */
1900 0 when modifying
1901 PCS_MII_ADVERT */
1903 OK. bit is
1904 non-resettable */
1906 of optical signal to make
1907 signal detect okay when
1908 signal is low */
1910 measurements. a single
1911 code group is xmitted
1912 regularly.
1913 0x0 = normal operation
1914 0x1 = high freq test
1915 pattern, D21.5
1916 0x2 = low freq test
1917 pattern, K28.7
1918 0x3 = reserved */
1920 negotiation timer to
1921 a few cycles for test
1922 purposes */
1924 /* used for diagnostic purposes. bits 20-22 autoclear on read */
1926 and diagnostic reg */
1928 xmission of idle.
1929 otherwise, xmission of
1930 a packet */
1932 of idle. otherwise,
1933 reception of packet */
1935 sync */
1937 indicates reception of
1938 Config codes. cycling
1939 through 0-1 indicates
1940 reception of idles */
1941 #define PCS_SM_LINK_STATE_MASK 0x0001E000
1945 recept of Config
1946 codes */
1948 loss of sync */
1950 from OK to FAIL. bit29
1951 will also be set if
1952 this is set */
1954 receipt of breaklink
1955 C codes from partner.
1956 C codes w/ 0 content
1957 received triggering
1958 start/restart of
1959 autonegotiation.
1960 should be sent for
1961 no longer than 20ms */
1963 initialized. see serdes
1964 state reg */
1966 not received */
1968 achieved */
1970 w/ ack bit set */
1972 to send C codes
1973 instead of idle
1974 symbols or pkt data */
1976 /* this register indicates interrupt changes in specific PCS MII status bits.
1977 * PCS_INT may be masked at the ISR level. only a single bit is implemented
1978 * for link status change.
1979 */
1982 since last read */
1984 /* control which network interface is used. no more than one bit should
1985 * be set.
1986 * DEFAULT: none
1987 */
1990 MII/GMII is selected.
1991 selection between MII and
1992 GMII is controlled by
1993 XIF_CFG */
1995 10-bit interface */
1997 /* input to serdes chip or serialink block */
2000 serdes interface */
2002 detection. should be
2003 0x0 for normal
2004 operation */
2006 to REFCLK when set.
2007 when clear, receiver
2008 clock locks to incoming
2009 serial data */
2011 /* multiplex test outputs into the PROM address (PA_3 through PA_0) pins.
2012 * should be 0x0 for normal operations.
2013 * 0b000 normal operation, PROM address[3:0] selected
2014 * 0b001 rxdma req, rxdma ack, rxdma ready, rxdma read
2015 * 0b010 rxmac req, rx ack, rx tag, rx clk shared
2016 * 0b011 txmac req, tx ack, tx tag, tx retry req
2017 * 0b100 tx tp3, tx tp2, tx tp1, tx tp0
2018 * 0b101 R period RX, R period TX, R period HP, R period BIM
2019 * DEFAULT: 0x0
2020 */
2022 #define PCS_SOS_PROM_ADDR_MASK 0x0007
2024 /* used for diagnostics. this register indicates progress of the SERDES
2025 * boot up.
2026 * 0b00 undergoing reset
2027 * 0b01 waiting 500us while lockrefn is asserted
2028 * 0b10 waiting for comma detect
2029 * 0b11 receive data is synchronized
2030 * DEFAULT: 0x0
2031 */
2033 #define PCS_SERDES_STATE_MASK 0x03
2035 /* used for diagnostics. indicates number of packets transmitted or received.
2036 * counters rollover w/out generating an interrupt.
2037 * DEFAULT: 0x0
2038 */
2042 whether they
2043 encountered an error
2044 or not */
2046 /** LocalBus Devices. the following provides run-time access to the
2047 * Cassini's PROM
2048 ***/
2050 access */
2051 #define REG_EXPANSION_ROM_RUN_END 0x17FFFF
2054 device */
2055 #define REG_SECOND_LOCALBUS_END 0x1FFFFF
2057 /* entropy device */
2058 #define REG_ENTROPY_START REG_SECOND_LOCALBUS_START
2059 #define REG_ENTROPY_DATA (REG_ENTROPY_START + 0x00)
2060 #define REG_ENTROPY_STATUS (REG_ENTROPY_START + 0x04)
2061 #define ENTROPY_STATUS_DRDY 0x01
2062 #define ENTROPY_STATUS_BUSY 0x02
2063 #define ENTROPY_STATUS_CIPHER 0x04
2064 #define ENTROPY_STATUS_BYPASS_MASK 0x18
2065 #define REG_ENTROPY_MODE (REG_ENTROPY_START + 0x05)
2066 #define ENTROPY_MODE_KEY_MASK 0x07
2067 #define ENTROPY_MODE_ENCRYPT 0x40
2068 #define REG_ENTROPY_RAND_REG (REG_ENTROPY_START + 0x06)
2069 #define REG_ENTROPY_RESET (REG_ENTROPY_START + 0x07)
2070 #define ENTROPY_RESET_DES_IO 0x01
2071 #define ENTROPY_RESET_STC_MODE 0x02
2072 #define ENTROPY_RESET_KEY_CACHE 0x04
2073 #define ENTROPY_RESET_IV 0x08
2074 #define REG_ENTROPY_IV (REG_ENTROPY_START + 0x08)
2075 #define REG_ENTROPY_KEY0 (REG_ENTROPY_START + 0x10)
2076 #define REG_ENTROPY_KEYN(x) (REG_ENTROPY_KEY0 + 4*(x))
2078 /* phys of interest w/ their special mii registers */
2079 #define PHY_LUCENT_B0 0x00437421
2080 #define LUCENT_MII_REG 0x1F
2082 #define PHY_NS_DP83065 0x20005c78
2083 #define DP83065_MII_MEM 0x16
2084 #define DP83065_MII_REGD 0x1D
2085 #define DP83065_MII_REGE 0x1E
2087 #define PHY_BROADCOM_5411 0x00206071
2088 #define PHY_BROADCOM_B0 0x00206050
2089 #define BROADCOM_MII_REG4 0x14
2090 #define BROADCOM_MII_REG5 0x15
2091 #define BROADCOM_MII_REG7 0x17
2092 #define BROADCOM_MII_REG8 0x18
2094 #define CAS_MII_ANNPTR 0x07
2095 #define CAS_MII_ANNPRR 0x08
2096 #define CAS_MII_1000_CTRL 0x09
2097 #define CAS_MII_1000_STATUS 0x0A
2098 #define CAS_MII_1000_EXTEND 0x0F
2101 /*
2102 * if autoneg is disabled, here's the table:
2103 * BMCR_SPEED100 = 100Mbps
2104 * BMCR_SPEED1000 = 1000Mbps
2105 * ~(BMCR_SPEED100 | BMCR_SPEED1000) = 10Mbps
2106 */
2109 #define CAS_ADVERTISE_1000HALF 0x0100
2110 #define CAS_ADVERTISE_1000FULL 0x0200
2111 #define CAS_ADVERTISE_PAUSE 0x0400
2112 #define CAS_ADVERTISE_ASYM_PAUSE 0x0800
2114 /* regular lpa register */
2115 #define CAS_LPA_PAUSE CAS_ADVERTISE_PAUSE
2116 #define CAS_LPA_ASYM_PAUSE CAS_ADVERTISE_ASYM_PAUSE
2118 /* 1000_STATUS register */
2119 #define CAS_LPA_1000HALF 0x0400
2120 #define CAS_LPA_1000FULL 0x0800
2122 #define CAS_EXTEND_1000XFULL 0x8000
2123 #define CAS_EXTEND_1000XHALF 0x4000
2124 #define CAS_EXTEND_1000TFULL 0x2000
2125 #define CAS_EXTEND_1000THALF 0x1000
2127 /* cassini header parser firmware */
2133 u8 op;
2136 /* output info */
2141 2 = if !match, 3 = always */
2143 u16 outmask;
2146 /* comparison */
2152 /* output opcodes */
2153 #define CL_REG 0
2154 #define LD_FID 1
2155 #define LD_SEQ 2
2156 #define LD_CTL 3
2157 #define LD_SAP 4
2158 #define LD_R1 5
2159 #define LD_L3 6
2160 #define LD_SUM 7
2161 #define LD_HDR 8
2162 #define IM_FID 9
2163 #define IM_SEQ 10
2164 #define IM_SAP 11
2165 #define IM_R1 12
2166 #define IM_CTL 13
2167 #define LD_LEN 14
2168 #define ST_FLG 15
2170 /* match setp #s for IP4TCP4 */
2171 #define S1_PCKT 0
2172 #define S1_VLAN 1
2173 #define S1_CFI 2
2174 #define S1_8023 3
2175 #define S1_LLC 4
2176 #define S1_LLCc 5
2177 #define S1_IPV4 6
2178 #define S1_IPV4c 7
2179 #define S1_IPV4F 8
2180 #define S1_TCP44 9
2181 #define S1_IPV6 10
2182 #define S1_IPV6L 11
2183 #define S1_IPV6c 12
2184 #define S1_TCP64 13
2185 #define S1_TCPSQ 14
2186 #define S1_TCPFG 15
2187 #define S1_TCPHL 16
2188 #define S1_TCPHc 17
2189 #define S1_CLNP 18
2190 #define S1_CLNP2 19
2191 #define S1_DROP 20
2192 #define S2_HTTP 21
2193 #define S1_ESP4 22
2194 #define S1_AH4 23
2195 #define S1_ESP6 24
2196 #define S1_AH6 25
2198 #define CAS_PROG_IP46TCP4_PREAMBLE \
2200 CL_REG, 0x3ff, 1, 0x0, 0x0000}, \
2202 IM_CTL, 0x00a, 3, 0x0, 0xffff}, \
2204 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2206 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2208 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2210 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2212 LD_SAP, 0x100, 3, 0x0, 0xffff}, \
2214 LD_SUM, 0x00a, 1, 0x0, 0x0000}, \
2216 LD_LEN, 0x03e, 1, 0x0, 0xffff}, \
2220 LD_SUM, 0x015, 1, 0x0, 0x0000}, \
2222 IM_R1, 0x128, 1, 0x0, 0xffff}, \
2226 LD_LEN, 0x03f, 1, 0x0, 0xffff}
2228 #ifdef USE_HP_IP46TCP4
2230 CAS_PROG_IP46TCP4_PREAMBLE,
2247 };
2248 #ifdef HP_IP46TCP4_DEFAULT
2249 #define CAS_HP_FIRMWARE cas_prog_ip46tcp4tab
2250 #endif
2251 #endif
2253 /*
2254 * Alternate table load which excludes HTTP server traffic from reassembly.
2255 * It is substantially similar to the basic table, with one extra state
2256 * and a few extra compares. */
2257 #ifdef USE_HP_IP46TCP4NOHTTP
2259 CAS_PROG_IP46TCP4_PREAMBLE,
2278 };
2279 #ifdef HP_IP46TCP4NOHTTP_DEFAULT
2280 #define CAS_HP_FIRMWARE cas_prog_ip46tcp4nohttptab
2281 #endif
2282 #endif
2284 /* match step #s for IP4FRAG */
2285 #define S3_IPV6c 11
2286 #define S3_TCP64 12
2287 #define S3_TCPSQ 13
2288 #define S3_TCPFG 14
2289 #define S3_TCPHL 15
2290 #define S3_TCPHc 16
2291 #define S3_FRAG 17
2292 #define S3_FOFF 18
2293 #define S3_CLNP 19
2295 #ifdef USE_HP_IP4FRAG
2339 };
2340 #ifdef HP_IP4FRAG_DEFAULT
2341 #define CAS_HP_FIRMWARE cas_prog_ip4fragtab
2342 #endif
2343 #endif
2345 /*
2346 * Alternate table which does batching without reassembly
2347 */
2348 #ifdef USE_HP_IP46TCP4BATCH
2350 CAS_PROG_IP46TCP4_PREAMBLE,
2365 };
2366 #ifdef HP_IP46TCP4BATCH_DEFAULT
2367 #define CAS_HP_FIRMWARE cas_prog_ip46tcp4batchtab
2368 #endif
2369 #endif
2371 #ifdef USE_HP_WORKAROUND
2415 };
2416 #ifdef HP_WORKAROUND_DEFAULT
2417 #define CAS_HP_FIRMWARE cas_prog_workaroundtab
2418 #endif
2419 #endif
2421 #ifdef USE_HP_ENCRYPT
2483 };
2484 #ifdef HP_ENCRYPT_DEFAULT
2485 #define CAS_HP_FIRMWARE cas_prog_encryptiontab
2486 #endif
2487 #endif
2490 #ifdef HP_NULL_DEFAULT
2491 #define CAS_HP_FIRMWARE cas_prog_null
2492 #endif
2494 /* phy types */
2495 #define CAS_PHY_UNKNOWN 0x00
2496 #define CAS_PHY_SERDES 0x01
2497 #define CAS_PHY_MII_MDIO0 0x02
2498 #define CAS_PHY_MII_MDIO1 0x04
2499 #define CAS_PHY_MII(x) ((x) & (CAS_PHY_MII_MDIO0 | CAS_PHY_MII_MDIO1))
2501 /* _RING_INDEX is the index for the ring sizes to be used. _RING_SIZE
2502 * is the actual size. the default index for the various rings is
2503 * 8. NOTE: there a bunch of alignment constraints for the rings. to
2504 * deal with that, i just allocate rings to create the desired
2505 * alignment. here are the constraints:
2506 * RX DESC and COMP rings must be 8KB aligned
2507 * TX DESC must be 2KB aligned.
2508 * if you change the numbers, be cognizant of how the alignment will change
2509 * in INIT_BLOCK as well.
2510 */
2512 #define DESC_RING_I_TO_S(x) (32*(1 << (x)))
2513 #define COMP_RING_I_TO_S(x) (128*(1 << (x)))
2518 #if (TX_DESC_RING_INDEX > 8) || (TX_DESC_RING_INDEX < 0)
2519 #error TX_DESC_RING_INDEX must be between 0 and 8
2520 #endif
2522 #if (RX_DESC_RING_INDEX > 8) || (RX_DESC_RING_INDEX < 0)
2523 #error RX_DESC_RING_INDEX must be between 0 and 8
2524 #endif
2526 #if (RX_COMP_RING_INDEX > 8) || (RX_COMP_RING_INDEX < 0)
2527 #error RX_COMP_RING_INDEX must be between 0 and 8
2528 #endif
2531 #define N_TX_RINGS_MASK MAX_TX_RINGS_MASK
2535 /* number of flows that can go through re-assembly */
2536 #define N_RX_FLOWS 64
2538 #define TX_DESC_RING_SIZE DESC_RING_I_TO_S(TX_DESC_RING_INDEX)
2539 #define RX_DESC_RING_SIZE DESC_RING_I_TO_S(RX_DESC_RING_INDEX)
2540 #define RX_COMP_RING_SIZE COMP_RING_I_TO_S(RX_COMP_RING_INDEX)
2541 #define TX_DESC_RINGN_INDEX(x) TX_DESC_RING_INDEX
2542 #define RX_DESC_RINGN_INDEX(x) RX_DESC_RING_INDEX
2543 #define RX_COMP_RINGN_INDEX(x) RX_COMP_RING_INDEX
2544 #define TX_DESC_RINGN_SIZE(x) TX_DESC_RING_SIZE
2545 #define RX_DESC_RINGN_SIZE(x) RX_DESC_RING_SIZE
2546 #define RX_COMP_RINGN_SIZE(x) RX_COMP_RING_SIZE
2548 /* convert values */
2549 #define CAS_BASE(x, y) (((y) << (x ## _SHIFT)) & (x ## _MASK))
2550 #define CAS_VAL(x, y) (((y) & (x ## _MASK)) >> (x ## _SHIFT))
2551 #define CAS_TX_RINGN_BASE(y) ((TX_DESC_RINGN_INDEX(y) << \
2552 TX_CFG_DESC_RINGN_SHIFT(y)) & \
2553 TX_CFG_DESC_RINGN_MASK(y))
2555 /* min is 2k, but we can't do jumbo frames unless it's at least 8k */
2561 bytes. 0 - 9256 */
2562 #define TX_DESC_BUFLEN_SHIFT 0
2564 of bytes to be
2565 skipped before
2566 csum calc begins.
2567 value must be
2568 even */
2569 #define TX_DESC_CSUM_START_SHIFT 15
2571 byte offset w/in
2572 the pkt for the
2573 1st csum byte.
2574 must be > 8 */
2575 #define TX_DESC_CSUM_STUFF_SHIFT 21
2581 CRC will not be
2582 inserted into
2583 outgoing frame. */
2585 __le64 control;
2586 __le64 buffer;
2587 };
2589 /* descriptor ring for free buffers contains page-sized buffers. the index
2590 * value is not used by the hw in any way. it's just stored and returned in
2591 * the completion ring.
2592 */
2594 __le64 index;
2595 __le64 buffer;
2596 };
2598 /* received packets are put on the completion ring. */
2599 /* word 1 */
2600 #define RX_COMP1_DATA_SIZE_MASK 0x0000000007FFE000ULL
2601 #define RX_COMP1_DATA_SIZE_SHIFT 13
2602 #define RX_COMP1_DATA_OFF_MASK 0x000001FFF8000000ULL
2603 #define RX_COMP1_DATA_OFF_SHIFT 27
2604 #define RX_COMP1_DATA_INDEX_MASK 0x007FFE0000000000ULL
2605 #define RX_COMP1_DATA_INDEX_SHIFT 41
2606 #define RX_COMP1_SKIP_MASK 0x0180000000000000ULL
2607 #define RX_COMP1_SKIP_SHIFT 55
2608 #define RX_COMP1_RELEASE_NEXT 0x0200000000000000ULL
2609 #define RX_COMP1_SPLIT_PKT 0x0400000000000000ULL
2610 #define RX_COMP1_RELEASE_FLOW 0x0800000000000000ULL
2611 #define RX_COMP1_RELEASE_DATA 0x1000000000000000ULL
2612 #define RX_COMP1_RELEASE_HDR 0x2000000000000000ULL
2613 #define RX_COMP1_TYPE_MASK 0xC000000000000000ULL
2614 #define RX_COMP1_TYPE_SHIFT 62
2616 /* word 2 */
2617 #define RX_COMP2_NEXT_INDEX_MASK 0x00000007FFE00000ULL
2618 #define RX_COMP2_NEXT_INDEX_SHIFT 21
2619 #define RX_COMP2_HDR_SIZE_MASK 0x00000FF800000000ULL
2620 #define RX_COMP2_HDR_SIZE_SHIFT 35
2621 #define RX_COMP2_HDR_OFF_MASK 0x0003F00000000000ULL
2622 #define RX_COMP2_HDR_OFF_SHIFT 44
2623 #define RX_COMP2_HDR_INDEX_MASK 0xFFFC000000000000ULL
2624 #define RX_COMP2_HDR_INDEX_SHIFT 50
2626 /* word 3 */
2627 #define RX_COMP3_SMALL_PKT 0x0000000000000001ULL
2628 #define RX_COMP3_JUMBO_PKT 0x0000000000000002ULL
2629 #define RX_COMP3_JUMBO_HDR_SPLIT_EN 0x0000000000000004ULL
2630 #define RX_COMP3_CSUM_START_MASK 0x000000000007F000ULL
2631 #define RX_COMP3_CSUM_START_SHIFT 12
2632 #define RX_COMP3_FLOWID_MASK 0x0000000001F80000ULL
2633 #define RX_COMP3_FLOWID_SHIFT 19
2634 #define RX_COMP3_OPCODE_MASK 0x000000000E000000ULL
2635 #define RX_COMP3_OPCODE_SHIFT 25
2636 #define RX_COMP3_FORCE_FLAG 0x0000000010000000ULL
2637 #define RX_COMP3_NO_ASSIST 0x0000000020000000ULL
2638 #define RX_COMP3_LOAD_BAL_MASK 0x000001F800000000ULL
2639 #define RX_COMP3_LOAD_BAL_SHIFT 35
2642 #define RX_COMP3_L3_HEAD_OFF_SHIFT 41
2644 #define RX_PLUS_COMP_L3_HEAD_OFF_SHIFT 42
2645 #define RX_COMP3_SAP_MASK 0xFFFF000000000000ULL
2646 #define RX_COMP3_SAP_SHIFT 48
2648 /* word 4 */
2649 #define RX_COMP4_TCP_CSUM_MASK 0x000000000000FFFFULL
2650 #define RX_COMP4_TCP_CSUM_SHIFT 0
2651 #define RX_COMP4_PKT_LEN_MASK 0x000000003FFF0000ULL
2652 #define RX_COMP4_PKT_LEN_SHIFT 16
2653 #define RX_COMP4_PERFECT_MATCH_MASK 0x00000003C0000000ULL
2654 #define RX_COMP4_PERFECT_MATCH_SHIFT 30
2655 #define RX_COMP4_ZERO 0x0000080000000000ULL
2656 #define RX_COMP4_HASH_VAL_MASK 0x0FFFF00000000000ULL
2657 #define RX_COMP4_HASH_VAL_SHIFT 44
2658 #define RX_COMP4_HASH_PASS 0x1000000000000000ULL
2659 #define RX_COMP4_BAD 0x4000000000000000ULL
2660 #define RX_COMP4_LEN_MISMATCH 0x8000000000000000ULL
2662 /* we encode the following: ring/index/release. only 14 bits
2663 * are usable.
2664 * NOTE: the encoding is dependent upon RX_DESC_RING_SIZE and
2665 * MAX_RX_DESC_RINGS. */
2666 #define RX_INDEX_NUM_MASK 0x0000000000000FFFULL
2667 #define RX_INDEX_NUM_SHIFT 0
2668 #define RX_INDEX_RING_MASK 0x0000000000001000ULL
2669 #define RX_INDEX_RING_SHIFT 12
2670 #define RX_INDEX_RELEASE 0x0000000000002000ULL
2673 __le64 word1;
2674 __le64 word2;
2675 __le64 word3;
2676 __le64 word4;
2677 };
2685 link_up /* Link is up */
2686 };
2691 dma_addr_t dma_addr;
2696 /* some alignment constraints:
2697 * TX DESC, RX DESC, and RX COMP must each be 8K aligned.
2698 * TX COMPWB must be 8-byte aligned.
2699 * to accomplish this, here's what we do:
2700 *
2701 * INIT_BLOCK_RX_COMP = 64k (already aligned)
2702 * INIT_BLOCK_RX_DESC = 8k
2703 * INIT_BLOCK_TX = 8k
2704 * INIT_BLOCK_RX1_DESC = 8k
2705 * TX COMPWB
2706 */
2707 #define INIT_BLOCK_TX (TX_DESC_RING_SIZE)
2708 #define INIT_BLOCK_RX_DESC (RX_DESC_RING_SIZE)
2709 #define INIT_BLOCK_RX_COMP (RX_COMP_RING_SIZE)
2715 __le64 tx_compwb;
2716 };
2718 /* tiny buffers to deal with target abort issue. we allocate a bit
2719 * over so that we don't have target abort issues with these buffers
2720 * as well.
2721 */
2722 #define TX_TINY_BUF_LEN 0x100
2723 #define TX_TINY_BUF_BLOCK ((INIT_BLOCK_TX + 1)*TX_TINY_BUF_LEN)
2728 };
2745 /* Set when chip is actually in operational state
2746 * (ie. not power managed) */
2756 /* we use sk_buffs for tx and pages for rx. the rx skbuffs
2757 * are there for flow re-assembly. */
2764 /* for small packets when copying would be quicker than
2765 mapping */
2769 u32 msg_enable;
2771 /* N_TX_RINGS must be >= N_RX_DESC_RINGS */
2775 u8 pci_revision;
2779 u32 phy_id;
2780 #define CAS_FLAG_1000MB_CAP 0x00000001
2781 #define CAS_FLAG_REG_PLUS 0x00000002
2782 #define CAS_FLAG_TARGET_ABORT 0x00000004
2783 #define CAS_FLAG_SATURN 0x00000008
2784 #define CAS_FLAG_RXD_POST_MASK 0x000000F0
2785 #define CAS_FLAG_RXD_POST_SHIFT 4
2786 #define CAS_FLAG_RXD_POST(x) ((1 << (CAS_FLAG_RXD_POST_SHIFT + (x))) & \
2787 CAS_FLAG_RXD_POST_MASK)
2788 #define CAS_FLAG_ENTROPY_DEV 0x00000100
2789 #define CAS_FLAG_NO_HW_CSUM 0x00000200
2790 u32 cas_flags;
2801 /* page size allocation */
2806 u32 mac_rx_cfg;
2808 /* Autoneg & PHY control */
2815 atomic_t reset_task_pending;
2816 atomic_t reset_task_pending_mtu;
2817 atomic_t reset_task_pending_spare;
2818 atomic_t reset_task_pending_all;
2820 #define LINK_TRANSITION_UNKNOWN 0
2821 #define LINK_TRANSITION_ON_FAILURE 1
2822 #define LINK_TRANSITION_STILL_FAILED 2
2823 #define LINK_TRANSITION_LINK_UP 3
2824 #define LINK_TRANSITION_LINK_CONFIG 4
2825 #define LINK_TRANSITION_LINK_DOWN 5
2826 #define LINK_TRANSITION_REQUESTED_RESET 6
2831 /* Tuning */
2835 /* Diagnostic counters and state. */
2837 u64 pause_entered;
2838 u16 pause_last_time_recvd;
2844 /* Firmware Info */
2845 u16 fw_load_addr;
2846 u32 fw_size;
2848 };
2850 #define TX_DESC_NEXT(r, x) (((x) + 1) & (TX_DESC_RINGN_SIZE(r) - 1))
2851 #define RX_DESC_ENTRY(r, x) ((x) & (RX_DESC_RINGN_SIZE(r) - 1))
2852 #define RX_COMP_ENTRY(r, x) ((x) & (RX_COMP_RINGN_SIZE(r) - 1))
2854 #define TX_BUFF_COUNT(r, x, y) ((x) <= (y) ? ((y) - (x)) : \
2855 (TX_DESC_RINGN_SIZE(r) - (x) + (y)))
2857 #define TX_BUFFS_AVAIL(cp, i) ((cp)->tx_old[(i)] <= (cp)->tx_new[(i)] ? \
2858 (cp)->tx_old[(i)] + (TX_DESC_RINGN_SIZE(i) - 1) - (cp)->tx_new[(i)] : \
2859 (cp)->tx_old[(i)] - (cp)->tx_new[(i)] - 1)
2861 #define CAS_ALIGN(addr, align) \
2862 (((unsigned long) (addr) + ((align) - 1UL)) & ~((align) - 1))
2864 #define RX_FIFO_SIZE 16384
2865 #define EXPANSION_ROM_SIZE 65536
2867 #define CAS_MC_EXACT_MATCH_SIZE 15
2868 #define CAS_MC_HASH_SIZE 256
2869 #define CAS_MC_HASH_MAX (CAS_MC_EXACT_MATCH_SIZE + \
2870 CAS_MC_HASH_SIZE)
2872 #define TX_TARGET_ABORT_LEN 0x20
2873 #define RX_SWIVEL_OFF_VAL 0x2
2874 #define RX_AE_FREEN_VAL(x) (RX_DESC_RINGN_SIZE(x) >> 1)
2875 #define RX_AE_COMP_VAL (RX_COMP_RING_SIZE >> 1)
2876 #define RX_BLANK_INTR_PKT_VAL 0x05
2877 #define RX_BLANK_INTR_TIME_VAL 0x0F
2880 #define RX_SPARE_COUNT (RX_DESC_RING_SIZE >> 1)
2881 #define RX_SPARE_RECOVER_VAL (RX_SPARE_COUNT >> 2)