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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / bnx2x / bnx2x_ethtool.c
blob5067fb6af7b8ba047a67265edaa5f5e3abec5ff1
1
2 #include <linux/ethtool.h>
3 #include <linux/netdevice.h>
4 #include <linux/types.h>
5 #include <linux/sched.h>
6 #include <linux/crc32.h>
7
8
9 #include "bnx2x.h"
10 #include "bnx2x_cmn.h"
11 #include "bnx2x_dump.h"
12
13
14 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
15 {
16 struct bnx2x *bp = netdev_priv(dev);
17
18 cmd->supported = bp->port.supported;
19 cmd->advertising = bp->port.advertising;
20
21 if ((bp->state == BNX2X_STATE_OPEN) &&
22 !(bp->flags & MF_FUNC_DIS) &&
23 (bp->link_vars.link_up)) {
24 cmd->speed = bp->link_vars.line_speed;
25 cmd->duplex = bp->link_vars.duplex;
26 if (IS_E1HMF(bp)) {
27 u16 vn_max_rate;
28
29 vn_max_rate =
30 ((bp->mf_config & FUNC_MF_CFG_MAX_BW_MASK) >>
31 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
32 if (vn_max_rate < cmd->speed)
33 cmd->speed = vn_max_rate;
34 }
35 } else {
36 cmd->speed = -1;
37 cmd->duplex = -1;
38 }
39
40 if (bp->link_params.switch_cfg == SWITCH_CFG_10G) {
41 u32 ext_phy_type =
42 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
43
44 switch (ext_phy_type) {
45 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
46 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
47 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
48 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
49 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
50 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
51 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
52 cmd->port = PORT_FIBRE;
53 break;
54
55 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
56 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
57 cmd->port = PORT_TP;
58 break;
59
60 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
61 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
62 bp->link_params.ext_phy_config);
63 break;
64
65 default:
66 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
67 bp->link_params.ext_phy_config);
68 break;
69 }
70 } else
71 cmd->port = PORT_TP;
72
73 cmd->phy_address = bp->mdio.prtad;
74 cmd->transceiver = XCVR_INTERNAL;
75
76 if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
77 cmd->autoneg = AUTONEG_ENABLE;
78 else
79 cmd->autoneg = AUTONEG_DISABLE;
80
81 cmd->maxtxpkt = 0;
82 cmd->maxrxpkt = 0;
83
84 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
85 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
86 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
87 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
88 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
89 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
90 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
91
92 return 0;
93 }
94
95 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
96 {
97 struct bnx2x *bp = netdev_priv(dev);
98 u32 advertising;
99
100 if (IS_E1HMF(bp))
101 return 0;
102
103 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
104 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
105 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
106 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
107 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
108 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
109 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
110
111 if (cmd->autoneg == AUTONEG_ENABLE) {
112 if (!(bp->port.supported & SUPPORTED_Autoneg)) {
113 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
114 return -EINVAL;
115 }
116
117 /* advertise the requested speed and duplex if supported */
118 cmd->advertising &= bp->port.supported;
119
120 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
121 bp->link_params.req_duplex = DUPLEX_FULL;
122 bp->port.advertising |= (ADVERTISED_Autoneg |
123 cmd->advertising);
124
125 } else { /* forced speed */
126 /* advertise the requested speed and duplex if supported */
127 switch (cmd->speed) {
128 case SPEED_10:
129 if (cmd->duplex == DUPLEX_FULL) {
130 if (!(bp->port.supported &
131 SUPPORTED_10baseT_Full)) {
132 DP(NETIF_MSG_LINK,
133 "10M full not supported\n");
134 return -EINVAL;
135 }
136
137 advertising = (ADVERTISED_10baseT_Full |
138 ADVERTISED_TP);
139 } else {
140 if (!(bp->port.supported &
141 SUPPORTED_10baseT_Half)) {
142 DP(NETIF_MSG_LINK,
143 "10M half not supported\n");
144 return -EINVAL;
145 }
146
147 advertising = (ADVERTISED_10baseT_Half |
148 ADVERTISED_TP);
149 }
150 break;
151
152 case SPEED_100:
153 if (cmd->duplex == DUPLEX_FULL) {
154 if (!(bp->port.supported &
155 SUPPORTED_100baseT_Full)) {
156 DP(NETIF_MSG_LINK,
157 "100M full not supported\n");
158 return -EINVAL;
159 }
160
161 advertising = (ADVERTISED_100baseT_Full |
162 ADVERTISED_TP);
163 } else {
164 if (!(bp->port.supported &
165 SUPPORTED_100baseT_Half)) {
166 DP(NETIF_MSG_LINK,
167 "100M half not supported\n");
168 return -EINVAL;
169 }
170
171 advertising = (ADVERTISED_100baseT_Half |
172 ADVERTISED_TP);
173 }
174 break;
175
176 case SPEED_1000:
177 if (cmd->duplex != DUPLEX_FULL) {
178 DP(NETIF_MSG_LINK, "1G half not supported\n");
179 return -EINVAL;
180 }
181
182 if (!(bp->port.supported & SUPPORTED_1000baseT_Full)) {
183 DP(NETIF_MSG_LINK, "1G full not supported\n");
184 return -EINVAL;
185 }
186
187 advertising = (ADVERTISED_1000baseT_Full |
188 ADVERTISED_TP);
189 break;
190
191 case SPEED_2500:
192 if (cmd->duplex != DUPLEX_FULL) {
193 DP(NETIF_MSG_LINK,
194 "2.5G half not supported\n");
195 return -EINVAL;
196 }
197
198 if (!(bp->port.supported & SUPPORTED_2500baseX_Full)) {
199 DP(NETIF_MSG_LINK,
200 "2.5G full not supported\n");
201 return -EINVAL;
202 }
203
204 advertising = (ADVERTISED_2500baseX_Full |
205 ADVERTISED_TP);
206 break;
207
208 case SPEED_10000:
209 if (cmd->duplex != DUPLEX_FULL) {
210 DP(NETIF_MSG_LINK, "10G half not supported\n");
211 return -EINVAL;
212 }
213
214 if (!(bp->port.supported & SUPPORTED_10000baseT_Full)) {
215 DP(NETIF_MSG_LINK, "10G full not supported\n");
216 return -EINVAL;
217 }
218
219 advertising = (ADVERTISED_10000baseT_Full |
220 ADVERTISED_FIBRE);
221 break;
222
223 default:
224 DP(NETIF_MSG_LINK, "Unsupported speed\n");
225 return -EINVAL;
226 }
227
228 bp->link_params.req_line_speed = cmd->speed;
229 bp->link_params.req_duplex = cmd->duplex;
230 bp->port.advertising = advertising;
231 }
232
233 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
234 DP_LEVEL " req_duplex %d advertising 0x%x\n",
235 bp->link_params.req_line_speed, bp->link_params.req_duplex,
236 bp->port.advertising);
237
238 if (netif_running(dev)) {
239 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
240 bnx2x_link_set(bp);
241 }
242
243 return 0;
244 }
245
246 #define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
247 #define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
248
249 static int bnx2x_get_regs_len(struct net_device *dev)
250 {
251 struct bnx2x *bp = netdev_priv(dev);
252 int regdump_len = 0;
253 int i;
254
255 if (CHIP_IS_E1(bp)) {
256 for (i = 0; i < REGS_COUNT; i++)
257 if (IS_E1_ONLINE(reg_addrs[i].info))
258 regdump_len += reg_addrs[i].size;
259
260 for (i = 0; i < WREGS_COUNT_E1; i++)
261 if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
262 regdump_len += wreg_addrs_e1[i].size *
263 (1 + wreg_addrs_e1[i].read_regs_count);
264
265 } else { /* E1H */
266 for (i = 0; i < REGS_COUNT; i++)
267 if (IS_E1H_ONLINE(reg_addrs[i].info))
268 regdump_len += reg_addrs[i].size;
269
270 for (i = 0; i < WREGS_COUNT_E1H; i++)
271 if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
272 regdump_len += wreg_addrs_e1h[i].size *
273 (1 + wreg_addrs_e1h[i].read_regs_count);
274 }
275 regdump_len *= 4;
276 regdump_len += sizeof(struct dump_hdr);
277
278 return regdump_len;
279 }
280
281 static void bnx2x_get_regs(struct net_device *dev,
282 struct ethtool_regs *regs, void *_p)
283 {
284 u32 *p = _p, i, j;
285 struct bnx2x *bp = netdev_priv(dev);
286 struct dump_hdr dump_hdr = {0};
287
288 regs->version = 0;
289 memset(p, 0, regs->len);
290
291 if (!netif_running(bp->dev))
292 return;
293
294 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
295 dump_hdr.dump_sign = dump_sign_all;
296 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
297 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
298 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
299 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
300 dump_hdr.info = CHIP_IS_E1(bp) ? RI_E1_ONLINE : RI_E1H_ONLINE;
301
302 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
303 p += dump_hdr.hdr_size + 1;
304
305 if (CHIP_IS_E1(bp)) {
306 for (i = 0; i < REGS_COUNT; i++)
307 if (IS_E1_ONLINE(reg_addrs[i].info))
308 for (j = 0; j < reg_addrs[i].size; j++)
309 *p++ = REG_RD(bp,
310 reg_addrs[i].addr + j*4);
311
312 } else { /* E1H */
313 for (i = 0; i < REGS_COUNT; i++)
314 if (IS_E1H_ONLINE(reg_addrs[i].info))
315 for (j = 0; j < reg_addrs[i].size; j++)
316 *p++ = REG_RD(bp,
317 reg_addrs[i].addr + j*4);
318 }
319 }
320
321 #define PHY_FW_VER_LEN 10
322
323 static void bnx2x_get_drvinfo(struct net_device *dev,
324 struct ethtool_drvinfo *info)
325 {
326 struct bnx2x *bp = netdev_priv(dev);
327 u8 phy_fw_ver[PHY_FW_VER_LEN];
328
329 strcpy(info->driver, DRV_MODULE_NAME);
330 strcpy(info->version, DRV_MODULE_VERSION);
331
332 phy_fw_ver[0] = '\0';
333 if (bp->port.pmf) {
334 bnx2x_acquire_phy_lock(bp);
335 bnx2x_get_ext_phy_fw_version(&bp->link_params,
336 (bp->state != BNX2X_STATE_CLOSED),
337 phy_fw_ver, PHY_FW_VER_LEN);
338 bnx2x_release_phy_lock(bp);
339 }
340
341 strncpy(info->fw_version, bp->fw_ver, 32);
342 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
343 "bc %d.%d.%d%s%s",
344 (bp->common.bc_ver & 0xff0000) >> 16,
345 (bp->common.bc_ver & 0xff00) >> 8,
346 (bp->common.bc_ver & 0xff),
347 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
348 strcpy(info->bus_info, pci_name(bp->pdev));
349 info->n_stats = BNX2X_NUM_STATS;
350 info->testinfo_len = BNX2X_NUM_TESTS;
351 info->eedump_len = bp->common.flash_size;
352 info->regdump_len = bnx2x_get_regs_len(dev);
353 }
354
355 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
356 {
357 struct bnx2x *bp = netdev_priv(dev);
358
359 if (bp->flags & NO_WOL_FLAG) {
360 wol->supported = 0;
361 wol->wolopts = 0;
362 } else {
363 wol->supported = WAKE_MAGIC;
364 if (bp->wol)
365 wol->wolopts = WAKE_MAGIC;
366 else
367 wol->wolopts = 0;
368 }
369 memset(&wol->sopass, 0, sizeof(wol->sopass));
370 }
371
372 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
373 {
374 struct bnx2x *bp = netdev_priv(dev);
375
376 if (wol->wolopts & ~WAKE_MAGIC)
377 return -EINVAL;
378
379 if (wol->wolopts & WAKE_MAGIC) {
380 if (bp->flags & NO_WOL_FLAG)
381 return -EINVAL;
382
383 bp->wol = 1;
384 } else
385 bp->wol = 0;
386
387 return 0;
388 }
389
390 static u32 bnx2x_get_msglevel(struct net_device *dev)
391 {
392 struct bnx2x *bp = netdev_priv(dev);
393
394 return bp->msg_enable;
395 }
396
397 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
398 {
399 struct bnx2x *bp = netdev_priv(dev);
400
401 if (capable(CAP_NET_ADMIN))
402 bp->msg_enable = level;
403 }
404
405 static int bnx2x_nway_reset(struct net_device *dev)
406 {
407 struct bnx2x *bp = netdev_priv(dev);
408
409 if (!bp->port.pmf)
410 return 0;
411
412 if (netif_running(dev)) {
413 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
414 bnx2x_link_set(bp);
415 }
416
417 return 0;
418 }
419
420 static u32 bnx2x_get_link(struct net_device *dev)
421 {
422 struct bnx2x *bp = netdev_priv(dev);
423
424 if (bp->flags & MF_FUNC_DIS)
425 return 0;
426
427 return bp->link_vars.link_up;
428 }
429
430 static int bnx2x_get_eeprom_len(struct net_device *dev)
431 {
432 struct bnx2x *bp = netdev_priv(dev);
433
434 return bp->common.flash_size;
435 }
436
437 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
438 {
439 int port = BP_PORT(bp);
440 int count, i;
441 u32 val = 0;
442
443 /* adjust timeout for emulation/FPGA */
444 count = NVRAM_TIMEOUT_COUNT;
445 if (CHIP_REV_IS_SLOW(bp))
446 count *= 100;
447
448 /* request access to nvram interface */
449 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
450 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
451
452 for (i = 0; i < count*10; i++) {
453 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
454 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
455 break;
456
457 udelay(5);
458 }
459
460 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
461 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
462 return -EBUSY;
463 }
464
465 return 0;
466 }
467
468 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
469 {
470 int port = BP_PORT(bp);
471 int count, i;
472 u32 val = 0;
473
474 /* adjust timeout for emulation/FPGA */
475 count = NVRAM_TIMEOUT_COUNT;
476 if (CHIP_REV_IS_SLOW(bp))
477 count *= 100;
478
479 /* relinquish nvram interface */
480 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
481 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
482
483 for (i = 0; i < count*10; i++) {
484 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
485 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
486 break;
487
488 udelay(5);
489 }
490
491 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
492 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
493 return -EBUSY;
494 }
495
496 return 0;
497 }
498
499 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
500 {
501 u32 val;
502
503 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
504
505 /* enable both bits, even on read */
506 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
507 (val | MCPR_NVM_ACCESS_ENABLE_EN |
508 MCPR_NVM_ACCESS_ENABLE_WR_EN));
509 }
510
511 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
512 {
513 u32 val;
514
515 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
516
517 /* disable both bits, even after read */
518 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
519 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
520 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
521 }
522
523 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
524 u32 cmd_flags)
525 {
526 int count, i, rc;
527 u32 val;
528
529 /* build the command word */
530 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
531
532 /* need to clear DONE bit separately */
533 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
534
535 /* address of the NVRAM to read from */
536 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
537 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
538
539 /* issue a read command */
540 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
541
542 /* adjust timeout for emulation/FPGA */
543 count = NVRAM_TIMEOUT_COUNT;
544 if (CHIP_REV_IS_SLOW(bp))
545 count *= 100;
546
547 /* wait for completion */
548 *ret_val = 0;
549 rc = -EBUSY;
550 for (i = 0; i < count; i++) {
551 udelay(5);
552 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
553
554 if (val & MCPR_NVM_COMMAND_DONE) {
555 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
556 /* we read nvram data in cpu order
557 * but ethtool sees it as an array of bytes
558 * converting to big-endian will do the work */
559 *ret_val = cpu_to_be32(val);
560 rc = 0;
561 break;
562 }
563 }
564
565 return rc;
566 }
567
568 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
569 int buf_size)
570 {
571 int rc;
572 u32 cmd_flags;
573 __be32 val;
574
575 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
576 DP(BNX2X_MSG_NVM,
577 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
578 offset, buf_size);
579 return -EINVAL;
580 }
581
582 if (offset + buf_size > bp->common.flash_size) {
583 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
584 " buf_size (0x%x) > flash_size (0x%x)\n",
585 offset, buf_size, bp->common.flash_size);
586 return -EINVAL;
587 }
588
589 /* request access to nvram interface */
590 rc = bnx2x_acquire_nvram_lock(bp);
591 if (rc)
592 return rc;
593
594 /* enable access to nvram interface */
595 bnx2x_enable_nvram_access(bp);
596
597 /* read the first word(s) */
598 cmd_flags = MCPR_NVM_COMMAND_FIRST;
599 while ((buf_size > sizeof(u32)) && (rc == 0)) {
600 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
601 memcpy(ret_buf, &val, 4);
602
603 /* advance to the next dword */
604 offset += sizeof(u32);
605 ret_buf += sizeof(u32);
606 buf_size -= sizeof(u32);
607 cmd_flags = 0;
608 }
609
610 if (rc == 0) {
611 cmd_flags |= MCPR_NVM_COMMAND_LAST;
612 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
613 memcpy(ret_buf, &val, 4);
614 }
615
616 /* disable access to nvram interface */
617 bnx2x_disable_nvram_access(bp);
618 bnx2x_release_nvram_lock(bp);
619
620 return rc;
621 }
622
623 static int bnx2x_get_eeprom(struct net_device *dev,
624 struct ethtool_eeprom *eeprom, u8 *eebuf)
625 {
626 struct bnx2x *bp = netdev_priv(dev);
627 int rc;
628
629 if (!netif_running(dev))
630 return -EAGAIN;
631
632 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
633 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
634 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
635 eeprom->len, eeprom->len);
636
637 /* parameters already validated in ethtool_get_eeprom */
638
639 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
640
641 return rc;
642 }
643
644 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
645 u32 cmd_flags)
646 {
647 int count, i, rc;
648
649 /* build the command word */
650 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
651
652 /* need to clear DONE bit separately */
653 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
654
655 /* write the data */
656 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
657
658 /* address of the NVRAM to write to */
659 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
660 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
661
662 /* issue the write command */
663 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
664
665 /* adjust timeout for emulation/FPGA */
666 count = NVRAM_TIMEOUT_COUNT;
667 if (CHIP_REV_IS_SLOW(bp))
668 count *= 100;
669
670 /* wait for completion */
671 rc = -EBUSY;
672 for (i = 0; i < count; i++) {
673 udelay(5);
674 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
675 if (val & MCPR_NVM_COMMAND_DONE) {
676 rc = 0;
677 break;
678 }
679 }
680
681 return rc;
682 }
683
684 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
685
686 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
687 int buf_size)
688 {
689 int rc;
690 u32 cmd_flags;
691 u32 align_offset;
692 __be32 val;
693
694 if (offset + buf_size > bp->common.flash_size) {
695 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
696 " buf_size (0x%x) > flash_size (0x%x)\n",
697 offset, buf_size, bp->common.flash_size);
698 return -EINVAL;
699 }
700
701 /* request access to nvram interface */
702 rc = bnx2x_acquire_nvram_lock(bp);
703 if (rc)
704 return rc;
705
706 /* enable access to nvram interface */
707 bnx2x_enable_nvram_access(bp);
708
709 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
710 align_offset = (offset & ~0x03);
711 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
712
713 if (rc == 0) {
714 val &= ~(0xff << BYTE_OFFSET(offset));
715 val |= (*data_buf << BYTE_OFFSET(offset));
716
717 /* nvram data is returned as an array of bytes
718 * convert it back to cpu order */
719 val = be32_to_cpu(val);
720
721 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
722 cmd_flags);
723 }
724
725 /* disable access to nvram interface */
726 bnx2x_disable_nvram_access(bp);
727 bnx2x_release_nvram_lock(bp);
728
729 return rc;
730 }
731
732 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
733 int buf_size)
734 {
735 int rc;
736 u32 cmd_flags;
737 u32 val;
738 u32 written_so_far;
739
740 if (buf_size == 1) /* ethtool */
741 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
742
743 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
744 DP(BNX2X_MSG_NVM,
745 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
746 offset, buf_size);
747 return -EINVAL;
748 }
749
750 if (offset + buf_size > bp->common.flash_size) {
751 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
752 " buf_size (0x%x) > flash_size (0x%x)\n",
753 offset, buf_size, bp->common.flash_size);
754 return -EINVAL;
755 }
756
757 /* request access to nvram interface */
758 rc = bnx2x_acquire_nvram_lock(bp);
759 if (rc)
760 return rc;
761
762 /* enable access to nvram interface */
763 bnx2x_enable_nvram_access(bp);
764
765 written_so_far = 0;
766 cmd_flags = MCPR_NVM_COMMAND_FIRST;
767 while ((written_so_far < buf_size) && (rc == 0)) {
768 if (written_so_far == (buf_size - sizeof(u32)))
769 cmd_flags |= MCPR_NVM_COMMAND_LAST;
770 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
771 cmd_flags |= MCPR_NVM_COMMAND_LAST;
772 else if ((offset % NVRAM_PAGE_SIZE) == 0)
773 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
774
775 memcpy(&val, data_buf, 4);
776
777 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
778
779 /* advance to the next dword */
780 offset += sizeof(u32);
781 data_buf += sizeof(u32);
782 written_so_far += sizeof(u32);
783 cmd_flags = 0;
784 }
785
786 /* disable access to nvram interface */
787 bnx2x_disable_nvram_access(bp);
788 bnx2x_release_nvram_lock(bp);
789
790 return rc;
791 }
792
793 static int bnx2x_set_eeprom(struct net_device *dev,
794 struct ethtool_eeprom *eeprom, u8 *eebuf)
795 {
796 struct bnx2x *bp = netdev_priv(dev);
797 int port = BP_PORT(bp);
798 int rc = 0;
799
800 if (!netif_running(dev))
801 return -EAGAIN;
802
803 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
804 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
805 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
806 eeprom->len, eeprom->len);
807
808 /* parameters already validated in ethtool_set_eeprom */
809
810 /* PHY eeprom can be accessed only by the PMF */
811 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
812 !bp->port.pmf)
813 return -EINVAL;
814
815 if (eeprom->magic == 0x50485950) {
816 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
817 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
818
819 bnx2x_acquire_phy_lock(bp);
820 rc |= bnx2x_link_reset(&bp->link_params,
821 &bp->link_vars, 0);
822 if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) ==
823 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
824 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
825 MISC_REGISTERS_GPIO_HIGH, port);
826 bnx2x_release_phy_lock(bp);
827 bnx2x_link_report(bp);
828
829 } else if (eeprom->magic == 0x50485952) {
830 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
831 if (bp->state == BNX2X_STATE_OPEN) {
832 bnx2x_acquire_phy_lock(bp);
833 rc |= bnx2x_link_reset(&bp->link_params,
834 &bp->link_vars, 1);
835
836 rc |= bnx2x_phy_init(&bp->link_params,
837 &bp->link_vars);
838 bnx2x_release_phy_lock(bp);
839 bnx2x_calc_fc_adv(bp);
840 }
841 } else if (eeprom->magic == 0x53985943) {
842 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
843 if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) ==
844 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
845 u8 ext_phy_addr =
846 XGXS_EXT_PHY_ADDR(bp->link_params.ext_phy_config);
847
848 /* DSP Remove Download Mode */
849 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
850 MISC_REGISTERS_GPIO_LOW, port);
851
852 bnx2x_acquire_phy_lock(bp);
853
854 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
855
856 /* wait 0.5 sec to allow it to run */
857 msleep(500);
858 bnx2x_ext_phy_hw_reset(bp, port);
859 msleep(500);
860 bnx2x_release_phy_lock(bp);
861 }
862 } else
863 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
864
865 return rc;
866 }
867 static int bnx2x_get_coalesce(struct net_device *dev,
868 struct ethtool_coalesce *coal)
869 {
870 struct bnx2x *bp = netdev_priv(dev);
871
872 memset(coal, 0, sizeof(struct ethtool_coalesce));
873
874 coal->rx_coalesce_usecs = bp->rx_ticks;
875 coal->tx_coalesce_usecs = bp->tx_ticks;
876
877 return 0;
878 }
879
880 static int bnx2x_set_coalesce(struct net_device *dev,
881 struct ethtool_coalesce *coal)
882 {
883 struct bnx2x *bp = netdev_priv(dev);
884
885 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
886 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
887 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
888
889 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
890 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
891 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
892
893 if (netif_running(dev))
894 bnx2x_update_coalesce(bp);
895
896 return 0;
897 }
898
899 static void bnx2x_get_ringparam(struct net_device *dev,
900 struct ethtool_ringparam *ering)
901 {
902 struct bnx2x *bp = netdev_priv(dev);
903
904 ering->rx_max_pending = MAX_RX_AVAIL;
905 ering->rx_mini_max_pending = 0;
906 ering->rx_jumbo_max_pending = 0;
907
908 ering->rx_pending = bp->rx_ring_size;
909 ering->rx_mini_pending = 0;
910 ering->rx_jumbo_pending = 0;
911
912 ering->tx_max_pending = MAX_TX_AVAIL;
913 ering->tx_pending = bp->tx_ring_size;
914 }
915
916 static int bnx2x_set_ringparam(struct net_device *dev,
917 struct ethtool_ringparam *ering)
918 {
919 struct bnx2x *bp = netdev_priv(dev);
920 int rc = 0;
921
922 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
923 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
924 return -EAGAIN;
925 }
926
927 if ((ering->rx_pending > MAX_RX_AVAIL) ||
928 (ering->tx_pending > MAX_TX_AVAIL) ||
929 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
930 return -EINVAL;
931
932 bp->rx_ring_size = ering->rx_pending;
933 bp->tx_ring_size = ering->tx_pending;
934
935 if (netif_running(dev)) {
936 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
937 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
938 }
939
940 return rc;
941 }
942
943 static void bnx2x_get_pauseparam(struct net_device *dev,
944 struct ethtool_pauseparam *epause)
945 {
946 struct bnx2x *bp = netdev_priv(dev);
947
948 epause->autoneg = (bp->link_params.req_flow_ctrl ==
949 BNX2X_FLOW_CTRL_AUTO) &&
950 (bp->link_params.req_line_speed == SPEED_AUTO_NEG);
951
952 epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
953 BNX2X_FLOW_CTRL_RX);
954 epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
955 BNX2X_FLOW_CTRL_TX);
956
957 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
958 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
959 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
960 }
961
962 static int bnx2x_set_pauseparam(struct net_device *dev,
963 struct ethtool_pauseparam *epause)
964 {
965 struct bnx2x *bp = netdev_priv(dev);
966
967 if (IS_E1HMF(bp))
968 return 0;
969
970 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
971 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
972 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
973
974 bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
975
976 if (epause->rx_pause)
977 bp->link_params.req_flow_ctrl |= BNX2X_FLOW_CTRL_RX;
978
979 if (epause->tx_pause)
980 bp->link_params.req_flow_ctrl |= BNX2X_FLOW_CTRL_TX;
981
982 if (bp->link_params.req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO)
983 bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
984
985 if (epause->autoneg) {
986 if (!(bp->port.supported & SUPPORTED_Autoneg)) {
987 DP(NETIF_MSG_LINK, "autoneg not supported\n");
988 return -EINVAL;
989 }
990
991 if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
992 bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
993 }
994
995 DP(NETIF_MSG_LINK,
996 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl);
997
998 if (netif_running(dev)) {
999 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1000 bnx2x_link_set(bp);
1001 }
1002
1003 return 0;
1004 }
1005
1006 static int bnx2x_set_flags(struct net_device *dev, u32 data)
1007 {
1008 struct bnx2x *bp = netdev_priv(dev);
1009 int changed = 0;
1010 int rc = 0;
1011
1012 if (data & ~(ETH_FLAG_LRO | ETH_FLAG_RXHASH))
1013 return -EINVAL;
1014
1015 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1016 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1017 return -EAGAIN;
1018 }
1019
1020 /* TPA requires Rx CSUM offloading */
1021 if ((data & ETH_FLAG_LRO) && bp->rx_csum) {
1022 if (!bp->disable_tpa) {
1023 if (!(dev->features & NETIF_F_LRO)) {
1024 dev->features |= NETIF_F_LRO;
1025 bp->flags |= TPA_ENABLE_FLAG;
1026 changed = 1;
1027 }
1028 } else
1029 rc = -EINVAL;
1030 } else if (dev->features & NETIF_F_LRO) {
1031 dev->features &= ~NETIF_F_LRO;
1032 bp->flags &= ~TPA_ENABLE_FLAG;
1033 changed = 1;
1034 }
1035
1036 if (data & ETH_FLAG_RXHASH)
1037 dev->features |= NETIF_F_RXHASH;
1038 else
1039 dev->features &= ~NETIF_F_RXHASH;
1040
1041 if (changed && netif_running(dev)) {
1042 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1043 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1044 }
1045
1046 return rc;
1047 }
1048
1049 static u32 bnx2x_get_rx_csum(struct net_device *dev)
1050 {
1051 struct bnx2x *bp = netdev_priv(dev);
1052
1053 return bp->rx_csum;
1054 }
1055
1056 static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
1057 {
1058 struct bnx2x *bp = netdev_priv(dev);
1059 int rc = 0;
1060
1061 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1062 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1063 return -EAGAIN;
1064 }
1065
1066 bp->rx_csum = data;
1067
1068 /* Disable TPA, when Rx CSUM is disabled. Otherwise all
1069 TPA'ed packets will be discarded due to wrong TCP CSUM */
1070 if (!data) {
1071 u32 flags = ethtool_op_get_flags(dev);
1072
1073 rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO));
1074 }
1075
1076 return rc;
1077 }
1078
1079 static int bnx2x_set_tso(struct net_device *dev, u32 data)
1080 {
1081 if (data) {
1082 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
1083 dev->features |= NETIF_F_TSO6;
1084 } else {
1085 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
1086 dev->features &= ~NETIF_F_TSO6;
1087 }
1088
1089 return 0;
1090 }
1091
1092 static const struct {
1093 char string[ETH_GSTRING_LEN];
1094 } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1095 { "register_test (offline)" },
1096 { "memory_test (offline)" },
1097 { "loopback_test (offline)" },
1098 { "nvram_test (online)" },
1099 { "interrupt_test (online)" },
1100 { "link_test (online)" },
1101 { "idle check (online)" }
1102 };
1103
1104 static int bnx2x_test_registers(struct bnx2x *bp)
1105 {
1106 int idx, i, rc = -ENODEV;
1107 u32 wr_val = 0;
1108 int port = BP_PORT(bp);
1109 static const struct {
1110 u32 offset0;
1111 u32 offset1;
1112 u32 mask;
1113 } reg_tbl[] = {
1114 /* 0 */ { BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1115 { DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1116 { HC_REG_AGG_INT_0, 4, 0x000003ff },
1117 { PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1118 { PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1119 { PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1120 { PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1121 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1122 { PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1123 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1124 /* 10 */ { PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1125 { QM_REG_CONNNUM_0, 4, 0x000fffff },
1126 { TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1127 { SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1128 { SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1129 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1130 { XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1131 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1132 { NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1133 { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1134 /* 20 */ { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1135 { NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1136 { NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1137 { NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1138 { NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1139 { NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1140 { NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1141 { NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1142 { NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1143 { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1144 /* 30 */ { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1145 { NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1146 { NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1147 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
1148 { NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1149 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1150 { NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1151
1152 { 0xffffffff, 0, 0x00000000 }
1153 };
1154
1155 if (!netif_running(bp->dev))
1156 return rc;
1157
1158 /* Repeat the test twice:
1159 First by writing 0x00000000, second by writing 0xffffffff */
1160 for (idx = 0; idx < 2; idx++) {
1161
1162 switch (idx) {
1163 case 0:
1164 wr_val = 0;
1165 break;
1166 case 1:
1167 wr_val = 0xffffffff;
1168 break;
1169 }
1170
1171 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1172 u32 offset, mask, save_val, val;
1173
1174 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1175 mask = reg_tbl[i].mask;
1176
1177 save_val = REG_RD(bp, offset);
1178
1179 REG_WR(bp, offset, (wr_val & mask));
1180 val = REG_RD(bp, offset);
1181
1182 /* Restore the original register's value */
1183 REG_WR(bp, offset, save_val);
1184
1185 /* verify value is as expected */
1186 if ((val & mask) != (wr_val & mask)) {
1187 DP(NETIF_MSG_PROBE,
1188 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1189 offset, val, wr_val, mask);
1190 goto test_reg_exit;
1191 }
1192 }
1193 }
1194
1195 rc = 0;
1196
1197 test_reg_exit:
1198 return rc;
1199 }
1200
1201 static int bnx2x_test_memory(struct bnx2x *bp)
1202 {
1203 int i, j, rc = -ENODEV;
1204 u32 val;
1205 static const struct {
1206 u32 offset;
1207 int size;
1208 } mem_tbl[] = {
1209 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1210 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1211 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1212 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1213 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1214 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1215 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1216
1217 { 0xffffffff, 0 }
1218 };
1219 static const struct {
1220 char *name;
1221 u32 offset;
1222 u32 e1_mask;
1223 u32 e1h_mask;
1224 } prty_tbl[] = {
1225 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0x3ffc0, 0 },
1226 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0x2, 0x2 },
1227 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0, 0 },
1228 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0x3ffc0, 0 },
1229 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0x3ffc0, 0 },
1230 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x3ffc1, 0 },
1231
1232 { NULL, 0xffffffff, 0, 0 }
1233 };
1234
1235 if (!netif_running(bp->dev))
1236 return rc;
1237
1238 /* Go through all the memories */
1239 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1240 for (j = 0; j < mem_tbl[i].size; j++)
1241 REG_RD(bp, mem_tbl[i].offset + j*4);
1242
1243 /* Check the parity status */
1244 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1245 val = REG_RD(bp, prty_tbl[i].offset);
1246 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1247 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask)))) {
1248 DP(NETIF_MSG_HW,
1249 "%s is 0x%x\n", prty_tbl[i].name, val);
1250 goto test_mem_exit;
1251 }
1252 }
1253
1254 rc = 0;
1255
1256 test_mem_exit:
1257 return rc;
1258 }
1259
1260 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up)
1261 {
1262 int cnt = 1000;
1263
1264 if (link_up)
1265 while (bnx2x_link_test(bp) && cnt--)
1266 msleep(10);
1267 }
1268
1269 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
1270 {
1271 unsigned int pkt_size, num_pkts, i;
1272 struct sk_buff *skb;
1273 unsigned char *packet;
1274 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1275 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1276 u16 tx_start_idx, tx_idx;
1277 u16 rx_start_idx, rx_idx;
1278 u16 pkt_prod, bd_prod;
1279 struct sw_tx_bd *tx_buf;
1280 struct eth_tx_start_bd *tx_start_bd;
1281 struct eth_tx_parse_bd *pbd = NULL;
1282 dma_addr_t mapping;
1283 union eth_rx_cqe *cqe;
1284 u8 cqe_fp_flags;
1285 struct sw_rx_bd *rx_buf;
1286 u16 len;
1287 int rc = -ENODEV;
1288
1289 /* check the loopback mode */
1290 switch (loopback_mode) {
1291 case BNX2X_PHY_LOOPBACK:
1292 if (bp->link_params.loopback_mode != LOOPBACK_XGXS_10)
1293 return -EINVAL;
1294 break;
1295 case BNX2X_MAC_LOOPBACK:
1296 bp->link_params.loopback_mode = LOOPBACK_BMAC;
1297 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1298 break;
1299 default:
1300 return -EINVAL;
1301 }
1302
1303 /* prepare the loopback packet */
1304 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1305 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1306 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1307 if (!skb) {
1308 rc = -ENOMEM;
1309 goto test_loopback_exit;
1310 }
1311 packet = skb_put(skb, pkt_size);
1312 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1313 memset(packet + ETH_ALEN, 0, ETH_ALEN);
1314 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1315 for (i = ETH_HLEN; i < pkt_size; i++)
1316 packet[i] = (unsigned char) (i & 0xff);
1317
1318 /* send the loopback packet */
1319 num_pkts = 0;
1320 tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1321 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1322
1323 pkt_prod = fp_tx->tx_pkt_prod++;
1324 tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
1325 tx_buf->first_bd = fp_tx->tx_bd_prod;
1326 tx_buf->skb = skb;
1327 tx_buf->flags = 0;
1328
1329 bd_prod = TX_BD(fp_tx->tx_bd_prod);
1330 tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
1331 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1332 skb_headlen(skb), DMA_TO_DEVICE);
1333 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1334 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1335 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1336 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
1337 tx_start_bd->vlan = cpu_to_le16(pkt_prod);
1338 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
1339 tx_start_bd->general_data = ((UNICAST_ADDRESS <<
1340 ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT) | 1);
1341
1342 /* turn on parsing and get a BD */
1343 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
1344 pbd = &fp_tx->tx_desc_ring[bd_prod].parse_bd;
1345
1346 memset(pbd, 0, sizeof(struct eth_tx_parse_bd));
1347
1348 wmb();
1349
1350 fp_tx->tx_db.data.prod += 2;
1351 barrier();
1352 DOORBELL(bp, fp_tx->index, fp_tx->tx_db.raw);
1353
1354 mmiowb();
1355
1356 num_pkts++;
1357 fp_tx->tx_bd_prod += 2; /* start + pbd */
1358
1359 udelay(100);
1360
1361 tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1362 if (tx_idx != tx_start_idx + num_pkts)
1363 goto test_loopback_exit;
1364
1365 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1366 if (rx_idx != rx_start_idx + num_pkts)
1367 goto test_loopback_exit;
1368
1369 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
1370 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1371 if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1372 goto test_loopback_rx_exit;
1373
1374 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1375 if (len != pkt_size)
1376 goto test_loopback_rx_exit;
1377
1378 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1379 skb = rx_buf->skb;
1380 skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1381 for (i = ETH_HLEN; i < pkt_size; i++)
1382 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1383 goto test_loopback_rx_exit;
1384
1385 rc = 0;
1386
1387 test_loopback_rx_exit:
1388
1389 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1390 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1391 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1392 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1393
1394 /* Update producers */
1395 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1396 fp_rx->rx_sge_prod);
1397
1398 test_loopback_exit:
1399 bp->link_params.loopback_mode = LOOPBACK_NONE;
1400
1401 return rc;
1402 }
1403
1404 static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
1405 {
1406 int rc = 0, res;
1407
1408 if (BP_NOMCP(bp))
1409 return rc;
1410
1411 if (!netif_running(bp->dev))
1412 return BNX2X_LOOPBACK_FAILED;
1413
1414 bnx2x_netif_stop(bp, 1);
1415 bnx2x_acquire_phy_lock(bp);
1416
1417 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
1418 if (res) {
1419 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res);
1420 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1421 }
1422
1423 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
1424 if (res) {
1425 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res);
1426 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1427 }
1428
1429 bnx2x_release_phy_lock(bp);
1430 bnx2x_netif_start(bp);
1431
1432 return rc;
1433 }
1434
1435 #define CRC32_RESIDUAL 0xdebb20e3
1436
1437 static int bnx2x_test_nvram(struct bnx2x *bp)
1438 {
1439 static const struct {
1440 int offset;
1441 int size;
1442 } nvram_tbl[] = {
1443 { 0, 0x14 }, /* bootstrap */
1444 { 0x14, 0xec }, /* dir */
1445 { 0x100, 0x350 }, /* manuf_info */
1446 { 0x450, 0xf0 }, /* feature_info */
1447 { 0x640, 0x64 }, /* upgrade_key_info */
1448 { 0x6a4, 0x64 },
1449 { 0x708, 0x70 }, /* manuf_key_info */
1450 { 0x778, 0x70 },
1451 { 0, 0 }
1452 };
1453 __be32 buf[0x350 / 4];
1454 u8 *data = (u8 *)buf;
1455 int i, rc;
1456 u32 magic, crc;
1457
1458 if (BP_NOMCP(bp))
1459 return 0;
1460
1461 rc = bnx2x_nvram_read(bp, 0, data, 4);
1462 if (rc) {
1463 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1464 goto test_nvram_exit;
1465 }
1466
1467 magic = be32_to_cpu(buf[0]);
1468 if (magic != 0x669955aa) {
1469 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1470 rc = -ENODEV;
1471 goto test_nvram_exit;
1472 }
1473
1474 for (i = 0; nvram_tbl[i].size; i++) {
1475
1476 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1477 nvram_tbl[i].size);
1478 if (rc) {
1479 DP(NETIF_MSG_PROBE,
1480 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1481 goto test_nvram_exit;
1482 }
1483
1484 crc = ether_crc_le(nvram_tbl[i].size, data);
1485 if (crc != CRC32_RESIDUAL) {
1486 DP(NETIF_MSG_PROBE,
1487 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1488 rc = -ENODEV;
1489 goto test_nvram_exit;
1490 }
1491 }
1492
1493 test_nvram_exit:
1494 return rc;
1495 }
1496
1497 static int bnx2x_test_intr(struct bnx2x *bp)
1498 {
1499 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
1500 int i, rc;
1501
1502 if (!netif_running(bp->dev))
1503 return -ENODEV;
1504
1505 config->hdr.length = 0;
1506 if (CHIP_IS_E1(bp))
1507 /* use last unicast entries */
1508 config->hdr.offset = (BP_PORT(bp) ? 63 : 31);
1509 else
1510 config->hdr.offset = BP_FUNC(bp);
1511 config->hdr.client_id = bp->fp->cl_id;
1512 config->hdr.reserved1 = 0;
1513
1514 bp->set_mac_pending++;
1515 smp_wmb();
1516 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
1517 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
1518 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
1519 if (rc == 0) {
1520 for (i = 0; i < 10; i++) {
1521 if (!bp->set_mac_pending)
1522 break;
1523 smp_rmb();
1524 msleep_interruptible(10);
1525 }
1526 if (i == 10)
1527 rc = -ENODEV;
1528 }
1529
1530 return rc;
1531 }
1532
1533 static void bnx2x_self_test(struct net_device *dev,
1534 struct ethtool_test *etest, u64 *buf)
1535 {
1536 struct bnx2x *bp = netdev_priv(dev);
1537
1538 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1539 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1540 etest->flags |= ETH_TEST_FL_FAILED;
1541 return;
1542 }
1543
1544 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
1545
1546 if (!netif_running(dev))
1547 return;
1548
1549 /* offline tests are not supported in MF mode */
1550 if (IS_E1HMF(bp))
1551 etest->flags &= ~ETH_TEST_FL_OFFLINE;
1552
1553 if (etest->flags & ETH_TEST_FL_OFFLINE) {
1554 int port = BP_PORT(bp);
1555 u32 val;
1556 u8 link_up;
1557
1558 /* save current value of input enable for TX port IF */
1559 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
1560 /* disable input for TX port IF */
1561 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
1562
1563 link_up = (bnx2x_link_test(bp) == 0);
1564 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1565 bnx2x_nic_load(bp, LOAD_DIAG);
1566 /* wait until link state is restored */
1567 bnx2x_wait_for_link(bp, link_up);
1568
1569 if (bnx2x_test_registers(bp) != 0) {
1570 buf[0] = 1;
1571 etest->flags |= ETH_TEST_FL_FAILED;
1572 }
1573 if (bnx2x_test_memory(bp) != 0) {
1574 buf[1] = 1;
1575 etest->flags |= ETH_TEST_FL_FAILED;
1576 }
1577 buf[2] = bnx2x_test_loopback(bp, link_up);
1578 if (buf[2] != 0)
1579 etest->flags |= ETH_TEST_FL_FAILED;
1580
1581 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1582
1583 /* restore input for TX port IF */
1584 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
1585
1586 bnx2x_nic_load(bp, LOAD_NORMAL);
1587 /* wait until link state is restored */
1588 bnx2x_wait_for_link(bp, link_up);
1589 }
1590 if (bnx2x_test_nvram(bp) != 0) {
1591 buf[3] = 1;
1592 etest->flags |= ETH_TEST_FL_FAILED;
1593 }
1594 if (bnx2x_test_intr(bp) != 0) {
1595 buf[4] = 1;
1596 etest->flags |= ETH_TEST_FL_FAILED;
1597 }
1598 if (bp->port.pmf)
1599 if (bnx2x_link_test(bp) != 0) {
1600 buf[5] = 1;
1601 etest->flags |= ETH_TEST_FL_FAILED;
1602 }
1603
1604 #ifdef BNX2X_EXTRA_DEBUG
1605 bnx2x_panic_dump(bp);
1606 #endif
1607 }
1608
1609 static const struct {
1610 long offset;
1611 int size;
1612 u8 string[ETH_GSTRING_LEN];
1613 } bnx2x_q_stats_arr[BNX2X_NUM_Q_STATS] = {
1614 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%d]: rx_bytes" },
1615 { Q_STATS_OFFSET32(error_bytes_received_hi),
1616 8, "[%d]: rx_error_bytes" },
1617 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
1618 8, "[%d]: rx_ucast_packets" },
1619 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
1620 8, "[%d]: rx_mcast_packets" },
1621 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
1622 8, "[%d]: rx_bcast_packets" },
1623 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%d]: rx_discards" },
1624 { Q_STATS_OFFSET32(rx_err_discard_pkt),
1625 4, "[%d]: rx_phy_ip_err_discards"},
1626 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
1627 4, "[%d]: rx_skb_alloc_discard" },
1628 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%d]: rx_csum_offload_errors" },
1629
1630 /* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%d]: tx_bytes" },
1631 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
1632 8, "[%d]: tx_ucast_packets" },
1633 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
1634 8, "[%d]: tx_mcast_packets" },
1635 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
1636 8, "[%d]: tx_bcast_packets" }
1637 };
1638
1639 static const struct {
1640 long offset;
1641 int size;
1642 u32 flags;
1643 #define STATS_FLAGS_PORT 1
1644 #define STATS_FLAGS_FUNC 2
1645 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
1646 u8 string[ETH_GSTRING_LEN];
1647 } bnx2x_stats_arr[BNX2X_NUM_STATS] = {
1648 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
1649 8, STATS_FLAGS_BOTH, "rx_bytes" },
1650 { STATS_OFFSET32(error_bytes_received_hi),
1651 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
1652 { STATS_OFFSET32(total_unicast_packets_received_hi),
1653 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
1654 { STATS_OFFSET32(total_multicast_packets_received_hi),
1655 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
1656 { STATS_OFFSET32(total_broadcast_packets_received_hi),
1657 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
1658 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
1659 8, STATS_FLAGS_PORT, "rx_crc_errors" },
1660 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
1661 8, STATS_FLAGS_PORT, "rx_align_errors" },
1662 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
1663 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
1664 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
1665 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
1666 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
1667 8, STATS_FLAGS_PORT, "rx_fragments" },
1668 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
1669 8, STATS_FLAGS_PORT, "rx_jabbers" },
1670 { STATS_OFFSET32(no_buff_discard_hi),
1671 8, STATS_FLAGS_BOTH, "rx_discards" },
1672 { STATS_OFFSET32(mac_filter_discard),
1673 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
1674 { STATS_OFFSET32(xxoverflow_discard),
1675 4, STATS_FLAGS_PORT, "rx_fw_discards" },
1676 { STATS_OFFSET32(brb_drop_hi),
1677 8, STATS_FLAGS_PORT, "rx_brb_discard" },
1678 { STATS_OFFSET32(brb_truncate_hi),
1679 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
1680 { STATS_OFFSET32(pause_frames_received_hi),
1681 8, STATS_FLAGS_PORT, "rx_pause_frames" },
1682 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
1683 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
1684 { STATS_OFFSET32(nig_timer_max),
1685 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
1686 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
1687 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
1688 { STATS_OFFSET32(rx_skb_alloc_failed),
1689 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
1690 { STATS_OFFSET32(hw_csum_err),
1691 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
1692
1693 { STATS_OFFSET32(total_bytes_transmitted_hi),
1694 8, STATS_FLAGS_BOTH, "tx_bytes" },
1695 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
1696 8, STATS_FLAGS_PORT, "tx_error_bytes" },
1697 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
1698 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
1699 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
1700 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
1701 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
1702 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
1703 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
1704 8, STATS_FLAGS_PORT, "tx_mac_errors" },
1705 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
1706 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
1707 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
1708 8, STATS_FLAGS_PORT, "tx_single_collisions" },
1709 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
1710 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
1711 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
1712 8, STATS_FLAGS_PORT, "tx_deferred" },
1713 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
1714 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
1715 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
1716 8, STATS_FLAGS_PORT, "tx_late_collisions" },
1717 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
1718 8, STATS_FLAGS_PORT, "tx_total_collisions" },
1719 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
1720 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
1721 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
1722 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
1723 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
1724 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
1725 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
1726 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
1727 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
1728 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
1729 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
1730 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
1731 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
1732 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
1733 { STATS_OFFSET32(pause_frames_sent_hi),
1734 8, STATS_FLAGS_PORT, "tx_pause_frames" }
1735 };
1736
1737 #define IS_PORT_STAT(i) \
1738 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
1739 #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
1740 #define IS_E1HMF_MODE_STAT(bp) \
1741 (IS_E1HMF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
1742
1743 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
1744 {
1745 struct bnx2x *bp = netdev_priv(dev);
1746 int i, num_stats;
1747
1748 switch (stringset) {
1749 case ETH_SS_STATS:
1750 if (is_multi(bp)) {
1751 num_stats = BNX2X_NUM_Q_STATS * bp->num_queues;
1752 if (!IS_E1HMF_MODE_STAT(bp))
1753 num_stats += BNX2X_NUM_STATS;
1754 } else {
1755 if (IS_E1HMF_MODE_STAT(bp)) {
1756 num_stats = 0;
1757 for (i = 0; i < BNX2X_NUM_STATS; i++)
1758 if (IS_FUNC_STAT(i))
1759 num_stats++;
1760 } else
1761 num_stats = BNX2X_NUM_STATS;
1762 }
1763 return num_stats;
1764
1765 case ETH_SS_TEST:
1766 return BNX2X_NUM_TESTS;
1767
1768 default:
1769 return -EINVAL;
1770 }
1771 }
1772
1773 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1774 {
1775 struct bnx2x *bp = netdev_priv(dev);
1776 int i, j, k;
1777
1778 switch (stringset) {
1779 case ETH_SS_STATS:
1780 if (is_multi(bp)) {
1781 k = 0;
1782 for_each_queue(bp, i) {
1783 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
1784 sprintf(buf + (k + j)*ETH_GSTRING_LEN,
1785 bnx2x_q_stats_arr[j].string, i);
1786 k += BNX2X_NUM_Q_STATS;
1787 }
1788 if (IS_E1HMF_MODE_STAT(bp))
1789 break;
1790 for (j = 0; j < BNX2X_NUM_STATS; j++)
1791 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
1792 bnx2x_stats_arr[j].string);
1793 } else {
1794 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
1795 if (IS_E1HMF_MODE_STAT(bp) && IS_PORT_STAT(i))
1796 continue;
1797 strcpy(buf + j*ETH_GSTRING_LEN,
1798 bnx2x_stats_arr[i].string);
1799 j++;
1800 }
1801 }
1802 break;
1803
1804 case ETH_SS_TEST:
1805 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
1806 break;
1807 }
1808 }
1809
1810 static void bnx2x_get_ethtool_stats(struct net_device *dev,
1811 struct ethtool_stats *stats, u64 *buf)
1812 {
1813 struct bnx2x *bp = netdev_priv(dev);
1814 u32 *hw_stats, *offset;
1815 int i, j, k;
1816
1817 if (is_multi(bp)) {
1818 k = 0;
1819 for_each_queue(bp, i) {
1820 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
1821 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
1822 if (bnx2x_q_stats_arr[j].size == 0) {
1823 /* skip this counter */
1824 buf[k + j] = 0;
1825 continue;
1826 }
1827 offset = (hw_stats +
1828 bnx2x_q_stats_arr[j].offset);
1829 if (bnx2x_q_stats_arr[j].size == 4) {
1830 /* 4-byte counter */
1831 buf[k + j] = (u64) *offset;
1832 continue;
1833 }
1834 /* 8-byte counter */
1835 buf[k + j] = HILO_U64(*offset, *(offset + 1));
1836 }
1837 k += BNX2X_NUM_Q_STATS;
1838 }
1839 if (IS_E1HMF_MODE_STAT(bp))
1840 return;
1841 hw_stats = (u32 *)&bp->eth_stats;
1842 for (j = 0; j < BNX2X_NUM_STATS; j++) {
1843 if (bnx2x_stats_arr[j].size == 0) {
1844 /* skip this counter */
1845 buf[k + j] = 0;
1846 continue;
1847 }
1848 offset = (hw_stats + bnx2x_stats_arr[j].offset);
1849 if (bnx2x_stats_arr[j].size == 4) {
1850 /* 4-byte counter */
1851 buf[k + j] = (u64) *offset;
1852 continue;
1853 }
1854 /* 8-byte counter */
1855 buf[k + j] = HILO_U64(*offset, *(offset + 1));
1856 }
1857 } else {
1858 hw_stats = (u32 *)&bp->eth_stats;
1859 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
1860 if (IS_E1HMF_MODE_STAT(bp) && IS_PORT_STAT(i))
1861 continue;
1862 if (bnx2x_stats_arr[i].size == 0) {
1863 /* skip this counter */
1864 buf[j] = 0;
1865 j++;
1866 continue;
1867 }
1868 offset = (hw_stats + bnx2x_stats_arr[i].offset);
1869 if (bnx2x_stats_arr[i].size == 4) {
1870 /* 4-byte counter */
1871 buf[j] = (u64) *offset;
1872 j++;
1873 continue;
1874 }
1875 /* 8-byte counter */
1876 buf[j] = HILO_U64(*offset, *(offset + 1));
1877 j++;
1878 }
1879 }
1880 }
1881
1882 static int bnx2x_phys_id(struct net_device *dev, u32 data)
1883 {
1884 struct bnx2x *bp = netdev_priv(dev);
1885 int i;
1886
1887 if (!netif_running(dev))
1888 return 0;
1889
1890 if (!bp->port.pmf)
1891 return 0;
1892
1893 if (data == 0)
1894 data = 2;
1895
1896 for (i = 0; i < (data * 2); i++) {
1897 if ((i % 2) == 0)
1898 bnx2x_set_led(&bp->link_params, LED_MODE_OPER,
1899 SPEED_1000);
1900 else
1901 bnx2x_set_led(&bp->link_params, LED_MODE_OFF, 0);
1902
1903 msleep_interruptible(500);
1904 if (signal_pending(current))
1905 break;
1906 }
1907
1908 if (bp->link_vars.link_up)
1909 bnx2x_set_led(&bp->link_params, LED_MODE_OPER,
1910 bp->link_vars.line_speed);
1911
1912 return 0;
1913 }
1914
1915 static const struct ethtool_ops bnx2x_ethtool_ops = {
1916 .get_settings = bnx2x_get_settings,
1917 .set_settings = bnx2x_set_settings,
1918 .get_drvinfo = bnx2x_get_drvinfo,
1919 .get_regs_len = bnx2x_get_regs_len,
1920 .get_regs = bnx2x_get_regs,
1921 .get_wol = bnx2x_get_wol,
1922 .set_wol = bnx2x_set_wol,
1923 .get_msglevel = bnx2x_get_msglevel,
1924 .set_msglevel = bnx2x_set_msglevel,
1925 .nway_reset = bnx2x_nway_reset,
1926 .get_link = bnx2x_get_link,
1927 .get_eeprom_len = bnx2x_get_eeprom_len,
1928 .get_eeprom = bnx2x_get_eeprom,
1929 .set_eeprom = bnx2x_set_eeprom,
1930 .get_coalesce = bnx2x_get_coalesce,
1931 .set_coalesce = bnx2x_set_coalesce,
1932 .get_ringparam = bnx2x_get_ringparam,
1933 .set_ringparam = bnx2x_set_ringparam,
1934 .get_pauseparam = bnx2x_get_pauseparam,
1935 .set_pauseparam = bnx2x_set_pauseparam,
1936 .get_rx_csum = bnx2x_get_rx_csum,
1937 .set_rx_csum = bnx2x_set_rx_csum,
1938 .get_tx_csum = ethtool_op_get_tx_csum,
1939 .set_tx_csum = ethtool_op_set_tx_hw_csum,
1940 .set_flags = bnx2x_set_flags,
1941 .get_flags = ethtool_op_get_flags,
1942 .get_sg = ethtool_op_get_sg,
1943 .set_sg = ethtool_op_set_sg,
1944 .get_tso = ethtool_op_get_tso,
1945 .set_tso = bnx2x_set_tso,
1946 .self_test = bnx2x_self_test,
1947 .get_sset_count = bnx2x_get_sset_count,
1948 .get_strings = bnx2x_get_strings,
1949 .phys_id = bnx2x_phys_id,
1950 .get_ethtool_stats = bnx2x_get_ethtool_stats,
1951 };
1952
1953 void bnx2x_set_ethtool_ops(struct net_device *netdev)
1954 {
1955 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
1956 }
Tomato firmware and modifications.