2 * drivers/mmc/host/via-sdmmc.c - VIA SD/MMC Card Reader driver
3 * Copyright (c) 2008, VIA Technologies Inc. All Rights Reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
11 #include <linux/pci.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/highmem.h>
14 #include <linux/delay.h>
16 #include <linux/mmc/host.h>
18 #define DRV_NAME "via_sdmmc"
20 #define PCI_DEVICE_ID_VIA_9530 0x9530
22 #define VIA_CRDR_SDC_OFF 0x200
23 #define VIA_CRDR_DDMA_OFF 0x400
24 #define VIA_CRDR_PCICTRL_OFF 0x600
26 #define VIA_CRDR_MIN_CLOCK 375000
27 #define VIA_CRDR_MAX_CLOCK 48000000
33 #define VIA_CRDR_PCI_WORK_MODE 0x40
34 #define VIA_CRDR_PCI_DBG_MODE 0x41
40 #define VIA_CRDR_SDCTRL 0x0
41 #define VIA_CRDR_SDCTRL_START 0x01
42 #define VIA_CRDR_SDCTRL_WRITE 0x04
43 #define VIA_CRDR_SDCTRL_SINGLE_WR 0x10
44 #define VIA_CRDR_SDCTRL_SINGLE_RD 0x20
45 #define VIA_CRDR_SDCTRL_MULTI_WR 0x30
46 #define VIA_CRDR_SDCTRL_MULTI_RD 0x40
47 #define VIA_CRDR_SDCTRL_STOP 0x70
49 #define VIA_CRDR_SDCTRL_RSP_NONE 0x0
50 #define VIA_CRDR_SDCTRL_RSP_R1 0x10000
51 #define VIA_CRDR_SDCTRL_RSP_R2 0x20000
52 #define VIA_CRDR_SDCTRL_RSP_R3 0x30000
53 #define VIA_CRDR_SDCTRL_RSP_R1B 0x90000
55 #define VIA_CRDR_SDCARG 0x4
57 #define VIA_CRDR_SDBUSMODE 0x8
58 #define VIA_CRDR_SDMODE_4BIT 0x02
59 #define VIA_CRDR_SDMODE_CLK_ON 0x40
61 #define VIA_CRDR_SDBLKLEN 0xc
63 * Bit 0 -Bit 10 : Block length. So, the maximum block length should be 2048.
64 * Bit 11 - Bit 13 : Reserved.
65 * GPIDET : Select GPI pin to detect card, GPI means CR_CD# in top design.
66 * INTEN : Enable SD host interrupt.
67 * Bit 16 - Bit 31 : Block count. So, the maximun block count should be 65536.
69 #define VIA_CRDR_SDBLKLEN_GPIDET 0x2000
70 #define VIA_CRDR_SDBLKLEN_INTEN 0x8000
71 #define VIA_CRDR_MAX_BLOCK_COUNT 65536
72 #define VIA_CRDR_MAX_BLOCK_LENGTH 2048
74 #define VIA_CRDR_SDRESP0 0x10
75 #define VIA_CRDR_SDRESP1 0x14
76 #define VIA_CRDR_SDRESP2 0x18
77 #define VIA_CRDR_SDRESP3 0x1c
79 #define VIA_CRDR_SDCURBLKCNT 0x20
81 #define VIA_CRDR_SDINTMASK 0x24
83 * MBDIE : Multiple Blocks transfer Done Interrupt Enable
84 * BDDIE : Block Data transfer Done Interrupt Enable
85 * CIRIE : Card Insertion or Removal Interrupt Enable
86 * CRDIE : Command-Response transfer Done Interrupt Enable
87 * CRTOIE : Command-Response response TimeOut Interrupt Enable
88 * ASCRDIE : Auto Stop Command-Response transfer Done Interrupt Enable
89 * DTIE : Data access Timeout Interrupt Enable
90 * SCIE : reSponse CRC error Interrupt Enable
91 * RCIE : Read data CRC error Interrupt Enable
92 * WCIE : Write data CRC error Interrupt Enable
94 #define VIA_CRDR_SDINTMASK_MBDIE 0x10
95 #define VIA_CRDR_SDINTMASK_BDDIE 0x20
96 #define VIA_CRDR_SDINTMASK_CIRIE 0x80
97 #define VIA_CRDR_SDINTMASK_CRDIE 0x200
98 #define VIA_CRDR_SDINTMASK_CRTOIE 0x400
99 #define VIA_CRDR_SDINTMASK_ASCRDIE 0x800
100 #define VIA_CRDR_SDINTMASK_DTIE 0x1000
101 #define VIA_CRDR_SDINTMASK_SCIE 0x2000
102 #define VIA_CRDR_SDINTMASK_RCIE 0x4000
103 #define VIA_CRDR_SDINTMASK_WCIE 0x8000
105 #define VIA_CRDR_SDACTIVE_INTMASK \
106 (VIA_CRDR_SDINTMASK_MBDIE | VIA_CRDR_SDINTMASK_CIRIE \
107 | VIA_CRDR_SDINTMASK_CRDIE | VIA_CRDR_SDINTMASK_CRTOIE \
108 | VIA_CRDR_SDINTMASK_DTIE | VIA_CRDR_SDINTMASK_SCIE \
109 | VIA_CRDR_SDINTMASK_RCIE | VIA_CRDR_SDINTMASK_WCIE)
111 #define VIA_CRDR_SDSTATUS 0x28
114 * WP : SD card Write Protect status
116 * SLOTG : SD SLOT status(Gpi pin status)
117 * MBD : Multiple Blocks transfer Done interrupt status
118 * BDD : Block Data transfer Done interrupt status
120 * CIR : Card Insertion or Removal interrupt detected on GPI pin
122 * CRD : Command-Response transfer Done interrupt status
123 * CRTO : Command-Response response TimeOut interrupt status
124 * ASCRDIE : Auto Stop Command-Response transfer Done interrupt status
125 * DT : Data access Timeout interrupt status
126 * SC : reSponse CRC error interrupt status
127 * RC : Read data CRC error interrupt status
128 * WC : Write data CRC error interrupt status
130 #define VIA_CRDR_SDSTS_CECC 0x01
131 #define VIA_CRDR_SDSTS_WP 0x02
132 #define VIA_CRDR_SDSTS_SLOTD 0x04
133 #define VIA_CRDR_SDSTS_SLOTG 0x08
134 #define VIA_CRDR_SDSTS_MBD 0x10
135 #define VIA_CRDR_SDSTS_BDD 0x20
136 #define VIA_CRDR_SDSTS_CD 0x40
137 #define VIA_CRDR_SDSTS_CIR 0x80
138 #define VIA_CRDR_SDSTS_IO 0x100
139 #define VIA_CRDR_SDSTS_CRD 0x200
140 #define VIA_CRDR_SDSTS_CRTO 0x400
141 #define VIA_CRDR_SDSTS_ASCRDIE 0x800
142 #define VIA_CRDR_SDSTS_DT 0x1000
143 #define VIA_CRDR_SDSTS_SC 0x2000
144 #define VIA_CRDR_SDSTS_RC 0x4000
145 #define VIA_CRDR_SDSTS_WC 0x8000
147 #define VIA_CRDR_SDSTS_IGN_MASK\
148 (VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_IO)
149 #define VIA_CRDR_SDSTS_INT_MASK \
150 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_CD \
151 | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_IO | VIA_CRDR_SDSTS_CRD \
152 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
153 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
154 #define VIA_CRDR_SDSTS_W1C_MASK \
155 (VIA_CRDR_SDSTS_CECC | VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD \
156 | VIA_CRDR_SDSTS_CD | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_CRD \
157 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
158 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
159 #define VIA_CRDR_SDSTS_CMD_MASK \
160 (VIA_CRDR_SDSTS_CRD | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_SC)
161 #define VIA_CRDR_SDSTS_DATA_MASK\
162 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_DT \
163 | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
165 #define VIA_CRDR_SDSTATUS2 0x2a
167 * CFE : Enable SD host automatic Clock FReezing
169 #define VIA_CRDR_SDSTS_CFE 0x80
171 #define VIA_CRDR_SDRSPTMO 0x2C
173 #define VIA_CRDR_SDCLKSEL 0x30
175 #define VIA_CRDR_SDEXTCTRL 0x34
176 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD 0x01
177 #define VIS_CRDR_SDEXTCTRL_SHIFT_9 0x02
178 #define VIS_CRDR_SDEXTCTRL_MMC_8BIT 0x04
179 #define VIS_CRDR_SDEXTCTRL_RELD_BLK 0x08
180 #define VIS_CRDR_SDEXTCTRL_BAD_CMDA 0x10
181 #define VIS_CRDR_SDEXTCTRL_BAD_DATA 0x20
182 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI 0x40
183 #define VIA_CRDR_SDEXTCTRL_HISPD 0x80
184 /* 0x38-0xFF reserved */
187 * Data DMA Control Registers
190 #define VIA_CRDR_DMABASEADD 0x0
191 #define VIA_CRDR_DMACOUNTER 0x4
193 #define VIA_CRDR_DMACTRL 0x8
195 * DIR :Transaction Direction
196 * 0 : From card to memory
197 * 1 : From memory to card
199 #define VIA_CRDR_DMACTRL_DIR 0x100
200 #define VIA_CRDR_DMACTRL_ENIRQ 0x10000
201 #define VIA_CRDR_DMACTRL_SFTRST 0x1000000
203 #define VIA_CRDR_DMASTS 0xc
205 #define VIA_CRDR_DMASTART 0x10
206 /*0x14-0xFF reserved*/
209 * PCI Control Registers
212 /*0x0 - 0x1 reserved*/
213 #define VIA_CRDR_PCICLKGATT 0x2
216 * 0 : Soft reset all the controller and it will be de-asserted automatically
217 * 1 : Soft reset is de-asserted
219 #define VIA_CRDR_PCICLKGATT_SFTRST 0x01
221 * 3V3 : Pad power select
224 * NOTE : No mater what the actual value should be, this bit always
225 * read as 0. This is a hardware bug.
227 #define VIA_CRDR_PCICLKGATT_3V3 0x10
229 * PAD_PWRON : Pad Power on/off select
232 * NOTE : No mater what the actual value should be, this bit always
233 * read as 0. This is a hardware bug.
235 #define VIA_CRDR_PCICLKGATT_PAD_PWRON 0x20
237 #define VIA_CRDR_PCISDCCLK 0x5
239 #define VIA_CRDR_PCIDMACLK 0x7
240 #define VIA_CRDR_PCIDMACLK_SDC 0x2
242 #define VIA_CRDR_PCIINTCTRL 0x8
243 #define VIA_CRDR_PCIINTCTRL_SDCIRQEN 0x04
245 #define VIA_CRDR_PCIINTSTATUS 0x9
246 #define VIA_CRDR_PCIINTSTATUS_SDC 0x04
248 #define VIA_CRDR_PCITMOCTRL 0xa
249 #define VIA_CRDR_PCITMOCTRL_NO 0x0
250 #define VIA_CRDR_PCITMOCTRL_32US 0x1
251 #define VIA_CRDR_PCITMOCTRL_256US 0x2
252 #define VIA_CRDR_PCITMOCTRL_1024US 0x3
253 #define VIA_CRDR_PCITMOCTRL_256MS 0x4
254 #define VIA_CRDR_PCITMOCTRL_512MS 0x5
255 #define VIA_CRDR_PCITMOCTRL_1024MS 0x6
257 /*0xB-0xFF reserved*/
259 enum PCI_HOST_CLK_CONTROL
{
297 struct via_crdr_mmc_host
{
298 struct mmc_host
*mmc
;
299 struct mmc_request
*mrq
;
300 struct mmc_command
*cmd
;
301 struct mmc_data
*data
;
303 void __iomem
*mmiobase
;
304 void __iomem
*sdhc_mmiobase
;
305 void __iomem
*ddma_mmiobase
;
306 void __iomem
*pcictrl_mmiobase
;
308 struct pcictrlreg pm_pcictrl_reg
;
309 struct sdhcreg pm_sdhc_reg
;
311 struct work_struct carddet_work
;
312 struct tasklet_struct finish_tasklet
;
314 struct timer_list timer
;
321 /* some devices need a very long delay for power to stabilize */
322 #define VIA_CRDR_QUIRK_300MS_PWRDELAY 0x0001
324 static struct pci_device_id via_ids
[] = {
325 {PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_9530
,
326 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0,},
330 MODULE_DEVICE_TABLE(pci
, via_ids
);
332 static void via_print_sdchc(struct via_crdr_mmc_host
*host
)
334 void __iomem
*addrbase
= host
->sdhc_mmiobase
;
336 pr_debug("SDC MMIO Registers:\n");
337 pr_debug("SDCONTROL=%08x, SDCMDARG=%08x, SDBUSMODE=%08x\n",
338 readl(addrbase
+ VIA_CRDR_SDCTRL
),
339 readl(addrbase
+ VIA_CRDR_SDCARG
),
340 readl(addrbase
+ VIA_CRDR_SDBUSMODE
));
341 pr_debug("SDBLKLEN=%08x, SDCURBLKCNT=%08x, SDINTMASK=%08x\n",
342 readl(addrbase
+ VIA_CRDR_SDBLKLEN
),
343 readl(addrbase
+ VIA_CRDR_SDCURBLKCNT
),
344 readl(addrbase
+ VIA_CRDR_SDINTMASK
));
345 pr_debug("SDSTATUS=%08x, SDCLKSEL=%08x, SDEXTCTRL=%08x\n",
346 readl(addrbase
+ VIA_CRDR_SDSTATUS
),
347 readl(addrbase
+ VIA_CRDR_SDCLKSEL
),
348 readl(addrbase
+ VIA_CRDR_SDEXTCTRL
));
351 static void via_print_pcictrl(struct via_crdr_mmc_host
*host
)
353 void __iomem
*addrbase
= host
->pcictrl_mmiobase
;
355 pr_debug("PCI Control Registers:\n");
356 pr_debug("PCICLKGATT=%02x, PCISDCCLK=%02x, PCIDMACLK=%02x\n",
357 readb(addrbase
+ VIA_CRDR_PCICLKGATT
),
358 readb(addrbase
+ VIA_CRDR_PCISDCCLK
),
359 readb(addrbase
+ VIA_CRDR_PCIDMACLK
));
360 pr_debug("PCIINTCTRL=%02x, PCIINTSTATUS=%02x\n",
361 readb(addrbase
+ VIA_CRDR_PCIINTCTRL
),
362 readb(addrbase
+ VIA_CRDR_PCIINTSTATUS
));
365 static void via_save_pcictrlreg(struct via_crdr_mmc_host
*host
)
367 struct pcictrlreg
*pm_pcictrl_reg
;
368 void __iomem
*addrbase
;
370 pm_pcictrl_reg
= &(host
->pm_pcictrl_reg
);
371 addrbase
= host
->pcictrl_mmiobase
;
373 pm_pcictrl_reg
->pciclkgat_reg
= readb(addrbase
+ VIA_CRDR_PCICLKGATT
);
374 pm_pcictrl_reg
->pciclkgat_reg
|=
375 VIA_CRDR_PCICLKGATT_3V3
| VIA_CRDR_PCICLKGATT_PAD_PWRON
;
376 pm_pcictrl_reg
->pcisdclk_reg
= readb(addrbase
+ VIA_CRDR_PCISDCCLK
);
377 pm_pcictrl_reg
->pcidmaclk_reg
= readb(addrbase
+ VIA_CRDR_PCIDMACLK
);
378 pm_pcictrl_reg
->pciintctrl_reg
= readb(addrbase
+ VIA_CRDR_PCIINTCTRL
);
379 pm_pcictrl_reg
->pciintstatus_reg
=
380 readb(addrbase
+ VIA_CRDR_PCIINTSTATUS
);
381 pm_pcictrl_reg
->pcitmoctrl_reg
= readb(addrbase
+ VIA_CRDR_PCITMOCTRL
);
384 static void via_restore_pcictrlreg(struct via_crdr_mmc_host
*host
)
386 struct pcictrlreg
*pm_pcictrl_reg
;
387 void __iomem
*addrbase
;
389 pm_pcictrl_reg
= &(host
->pm_pcictrl_reg
);
390 addrbase
= host
->pcictrl_mmiobase
;
392 writeb(pm_pcictrl_reg
->pciclkgat_reg
, addrbase
+ VIA_CRDR_PCICLKGATT
);
393 writeb(pm_pcictrl_reg
->pcisdclk_reg
, addrbase
+ VIA_CRDR_PCISDCCLK
);
394 writeb(pm_pcictrl_reg
->pcidmaclk_reg
, addrbase
+ VIA_CRDR_PCIDMACLK
);
395 writeb(pm_pcictrl_reg
->pciintctrl_reg
, addrbase
+ VIA_CRDR_PCIINTCTRL
);
396 writeb(pm_pcictrl_reg
->pciintstatus_reg
,
397 addrbase
+ VIA_CRDR_PCIINTSTATUS
);
398 writeb(pm_pcictrl_reg
->pcitmoctrl_reg
, addrbase
+ VIA_CRDR_PCITMOCTRL
);
401 static void via_save_sdcreg(struct via_crdr_mmc_host
*host
)
403 struct sdhcreg
*pm_sdhc_reg
;
404 void __iomem
*addrbase
;
406 pm_sdhc_reg
= &(host
->pm_sdhc_reg
);
407 addrbase
= host
->sdhc_mmiobase
;
409 pm_sdhc_reg
->sdcontrol_reg
= readl(addrbase
+ VIA_CRDR_SDCTRL
);
410 pm_sdhc_reg
->sdcmdarg_reg
= readl(addrbase
+ VIA_CRDR_SDCARG
);
411 pm_sdhc_reg
->sdbusmode_reg
= readl(addrbase
+ VIA_CRDR_SDBUSMODE
);
412 pm_sdhc_reg
->sdblklen_reg
= readl(addrbase
+ VIA_CRDR_SDBLKLEN
);
413 pm_sdhc_reg
->sdcurblkcnt_reg
= readl(addrbase
+ VIA_CRDR_SDCURBLKCNT
);
414 pm_sdhc_reg
->sdintmask_reg
= readl(addrbase
+ VIA_CRDR_SDINTMASK
);
415 pm_sdhc_reg
->sdstatus_reg
= readl(addrbase
+ VIA_CRDR_SDSTATUS
);
416 pm_sdhc_reg
->sdrsptmo_reg
= readl(addrbase
+ VIA_CRDR_SDRSPTMO
);
417 pm_sdhc_reg
->sdclksel_reg
= readl(addrbase
+ VIA_CRDR_SDCLKSEL
);
418 pm_sdhc_reg
->sdextctrl_reg
= readl(addrbase
+ VIA_CRDR_SDEXTCTRL
);
421 static void via_restore_sdcreg(struct via_crdr_mmc_host
*host
)
423 struct sdhcreg
*pm_sdhc_reg
;
424 void __iomem
*addrbase
;
426 pm_sdhc_reg
= &(host
->pm_sdhc_reg
);
427 addrbase
= host
->sdhc_mmiobase
;
429 writel(pm_sdhc_reg
->sdcontrol_reg
, addrbase
+ VIA_CRDR_SDCTRL
);
430 writel(pm_sdhc_reg
->sdcmdarg_reg
, addrbase
+ VIA_CRDR_SDCARG
);
431 writel(pm_sdhc_reg
->sdbusmode_reg
, addrbase
+ VIA_CRDR_SDBUSMODE
);
432 writel(pm_sdhc_reg
->sdblklen_reg
, addrbase
+ VIA_CRDR_SDBLKLEN
);
433 writel(pm_sdhc_reg
->sdcurblkcnt_reg
, addrbase
+ VIA_CRDR_SDCURBLKCNT
);
434 writel(pm_sdhc_reg
->sdintmask_reg
, addrbase
+ VIA_CRDR_SDINTMASK
);
435 writel(pm_sdhc_reg
->sdstatus_reg
, addrbase
+ VIA_CRDR_SDSTATUS
);
436 writel(pm_sdhc_reg
->sdrsptmo_reg
, addrbase
+ VIA_CRDR_SDRSPTMO
);
437 writel(pm_sdhc_reg
->sdclksel_reg
, addrbase
+ VIA_CRDR_SDCLKSEL
);
438 writel(pm_sdhc_reg
->sdextctrl_reg
, addrbase
+ VIA_CRDR_SDEXTCTRL
);
441 static void via_pwron_sleep(struct via_crdr_mmc_host
*sdhost
)
443 if (sdhost
->quirks
& VIA_CRDR_QUIRK_300MS_PWRDELAY
)
449 static void via_set_ddma(struct via_crdr_mmc_host
*host
,
450 dma_addr_t dmaaddr
, u32 count
, int dir
, int enirq
)
452 void __iomem
*addrbase
;
456 ctrl_data
|= VIA_CRDR_DMACTRL_ENIRQ
;
459 ctrl_data
|= VIA_CRDR_DMACTRL_DIR
;
461 addrbase
= host
->ddma_mmiobase
;
463 writel(dmaaddr
, addrbase
+ VIA_CRDR_DMABASEADD
);
464 writel(count
, addrbase
+ VIA_CRDR_DMACOUNTER
);
465 writel(ctrl_data
, addrbase
+ VIA_CRDR_DMACTRL
);
466 writel(0x01, addrbase
+ VIA_CRDR_DMASTART
);
468 /* It seems that our DMA can not work normally with 375kHz clock */
469 addrbase
= host
->pcictrl_mmiobase
;
470 if (readb(addrbase
+ VIA_CRDR_PCISDCCLK
) == PCI_CLK_375K
) {
471 dev_info(host
->mmc
->parent
, "forcing card speed to 8MHz\n");
472 writeb(PCI_CLK_8M
, addrbase
+ VIA_CRDR_PCISDCCLK
);
476 static void via_sdc_preparedata(struct via_crdr_mmc_host
*host
,
477 struct mmc_data
*data
)
479 void __iomem
*addrbase
;
486 BUG_ON(data
->blksz
> host
->mmc
->max_blk_size
);
487 BUG_ON(data
->blocks
> host
->mmc
->max_blk_count
);
491 count
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
, data
->sg_len
,
492 ((data
->flags
& MMC_DATA_READ
) ?
493 PCI_DMA_FROMDEVICE
: PCI_DMA_TODEVICE
));
496 via_set_ddma(host
, sg_dma_address(data
->sg
), sg_dma_len(data
->sg
),
497 (data
->flags
& MMC_DATA_WRITE
) ? 1 : 0, 1);
499 addrbase
= host
->sdhc_mmiobase
;
501 blk_reg
= data
->blksz
- 1;
502 blk_reg
|= VIA_CRDR_SDBLKLEN_GPIDET
| VIA_CRDR_SDBLKLEN_INTEN
;
503 blk_reg
|= (data
->blocks
) << 16;
505 writel(blk_reg
, addrbase
+ VIA_CRDR_SDBLKLEN
);
508 static void via_sdc_get_response(struct via_crdr_mmc_host
*host
,
509 struct mmc_command
*cmd
)
511 void __iomem
*addrbase
= host
->sdhc_mmiobase
;
512 u32 dwdata0
= readl(addrbase
+ VIA_CRDR_SDRESP0
);
513 u32 dwdata1
= readl(addrbase
+ VIA_CRDR_SDRESP1
);
514 u32 dwdata2
= readl(addrbase
+ VIA_CRDR_SDRESP2
);
515 u32 dwdata3
= readl(addrbase
+ VIA_CRDR_SDRESP3
);
517 if (cmd
->flags
& MMC_RSP_136
) {
518 cmd
->resp
[0] = ((u8
) (dwdata1
)) |
519 (((u8
) (dwdata0
>> 24)) << 8) |
520 (((u8
) (dwdata0
>> 16)) << 16) |
521 (((u8
) (dwdata0
>> 8)) << 24);
523 cmd
->resp
[1] = ((u8
) (dwdata2
)) |
524 (((u8
) (dwdata1
>> 24)) << 8) |
525 (((u8
) (dwdata1
>> 16)) << 16) |
526 (((u8
) (dwdata1
>> 8)) << 24);
528 cmd
->resp
[2] = ((u8
) (dwdata3
)) |
529 (((u8
) (dwdata2
>> 24)) << 8) |
530 (((u8
) (dwdata2
>> 16)) << 16) |
531 (((u8
) (dwdata2
>> 8)) << 24);
533 cmd
->resp
[3] = 0xff |
534 ((((u8
) (dwdata3
>> 24))) << 8) |
535 (((u8
) (dwdata3
>> 16)) << 16) |
536 (((u8
) (dwdata3
>> 8)) << 24);
539 cmd
->resp
[0] = ((dwdata0
& 0xff) << 24) |
540 (((dwdata0
>> 8) & 0xff) << 16) |
541 (((dwdata0
>> 16) & 0xff) << 8) | (dwdata1
& 0xff);
544 cmd
->resp
[1] = ((dwdata1
& 0xff) << 24) |
545 (((dwdata1
>> 8) & 0xff) << 16) |
546 (((dwdata1
>> 16) & 0xff) << 8);
550 static void via_sdc_send_command(struct via_crdr_mmc_host
*host
,
551 struct mmc_command
*cmd
)
553 void __iomem
*addrbase
;
554 struct mmc_data
*data
;
560 mod_timer(&host
->timer
, jiffies
+ HZ
);
564 cmdctrl
= cmd
->opcode
<< 8;
567 switch (mmc_resp_type(cmd
)) {
569 cmdctrl
|= VIA_CRDR_SDCTRL_RSP_NONE
;
572 cmdctrl
|= VIA_CRDR_SDCTRL_RSP_R1
;
575 cmdctrl
|= VIA_CRDR_SDCTRL_RSP_R1B
;
578 cmdctrl
|= VIA_CRDR_SDCTRL_RSP_R2
;
581 cmdctrl
|= VIA_CRDR_SDCTRL_RSP_R3
;
584 pr_err("%s: cmd->flag is not valid\n", mmc_hostname(host
->mmc
));
591 via_sdc_preparedata(host
, data
);
594 if (data
->blocks
> 1) {
595 if (data
->flags
& MMC_DATA_WRITE
) {
596 cmdctrl
|= VIA_CRDR_SDCTRL_WRITE
;
597 cmdctrl
|= VIA_CRDR_SDCTRL_MULTI_WR
;
599 cmdctrl
|= VIA_CRDR_SDCTRL_MULTI_RD
;
602 if (data
->flags
& MMC_DATA_WRITE
) {
603 cmdctrl
|= VIA_CRDR_SDCTRL_WRITE
;
604 cmdctrl
|= VIA_CRDR_SDCTRL_SINGLE_WR
;
606 cmdctrl
|= VIA_CRDR_SDCTRL_SINGLE_RD
;
611 if (cmd
== host
->mrq
->stop
)
612 cmdctrl
|= VIA_CRDR_SDCTRL_STOP
;
614 cmdctrl
|= VIA_CRDR_SDCTRL_START
;
616 addrbase
= host
->sdhc_mmiobase
;
617 writel(cmd
->arg
, addrbase
+ VIA_CRDR_SDCARG
);
618 writel(cmdctrl
, addrbase
+ VIA_CRDR_SDCTRL
);
621 static void via_sdc_finish_data(struct via_crdr_mmc_host
*host
)
623 struct mmc_data
*data
;
631 data
->bytes_xfered
= 0;
633 data
->bytes_xfered
= data
->blocks
* data
->blksz
;
635 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
, data
->sg_len
,
636 ((data
->flags
& MMC_DATA_READ
) ?
637 PCI_DMA_FROMDEVICE
: PCI_DMA_TODEVICE
));
640 via_sdc_send_command(host
, data
->stop
);
642 tasklet_schedule(&host
->finish_tasklet
);
645 static void via_sdc_finish_command(struct via_crdr_mmc_host
*host
)
647 via_sdc_get_response(host
, host
->cmd
);
649 host
->cmd
->error
= 0;
651 if (!host
->cmd
->data
)
652 tasklet_schedule(&host
->finish_tasklet
);
657 static void via_sdc_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
659 void __iomem
*addrbase
;
660 struct via_crdr_mmc_host
*host
;
664 host
= mmc_priv(mmc
);
666 spin_lock_irqsave(&host
->lock
, flags
);
668 addrbase
= host
->pcictrl_mmiobase
;
669 writeb(VIA_CRDR_PCIDMACLK_SDC
, addrbase
+ VIA_CRDR_PCIDMACLK
);
671 status
= readw(host
->sdhc_mmiobase
+ VIA_CRDR_SDSTATUS
);
672 status
&= VIA_CRDR_SDSTS_W1C_MASK
;
673 writew(status
, host
->sdhc_mmiobase
+ VIA_CRDR_SDSTATUS
);
675 WARN_ON(host
->mrq
!= NULL
);
678 status
= readw(host
->sdhc_mmiobase
+ VIA_CRDR_SDSTATUS
);
679 if (!(status
& VIA_CRDR_SDSTS_SLOTG
) || host
->reject
) {
680 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
681 tasklet_schedule(&host
->finish_tasklet
);
683 via_sdc_send_command(host
, mrq
->cmd
);
687 spin_unlock_irqrestore(&host
->lock
, flags
);
690 static void via_sdc_set_power(struct via_crdr_mmc_host
*host
,
691 unsigned short power
, unsigned int on
)
696 spin_lock_irqsave(&host
->lock
, flags
);
698 host
->power
= (1 << power
);
700 gatt
= readb(host
->pcictrl_mmiobase
+ VIA_CRDR_PCICLKGATT
);
701 if (host
->power
== MMC_VDD_165_195
)
702 gatt
&= ~VIA_CRDR_PCICLKGATT_3V3
;
704 gatt
|= VIA_CRDR_PCICLKGATT_3V3
;
706 gatt
|= VIA_CRDR_PCICLKGATT_PAD_PWRON
;
708 gatt
&= ~VIA_CRDR_PCICLKGATT_PAD_PWRON
;
709 writeb(gatt
, host
->pcictrl_mmiobase
+ VIA_CRDR_PCICLKGATT
);
712 spin_unlock_irqrestore(&host
->lock
, flags
);
714 via_pwron_sleep(host
);
717 static void via_sdc_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
719 struct via_crdr_mmc_host
*host
;
721 void __iomem
*addrbase
;
722 u32 org_data
, sdextctrl
;
725 host
= mmc_priv(mmc
);
727 spin_lock_irqsave(&host
->lock
, flags
);
729 addrbase
= host
->sdhc_mmiobase
;
730 org_data
= readl(addrbase
+ VIA_CRDR_SDBUSMODE
);
731 sdextctrl
= readl(addrbase
+ VIA_CRDR_SDEXTCTRL
);
733 if (ios
->bus_width
== MMC_BUS_WIDTH_1
)
734 org_data
&= ~VIA_CRDR_SDMODE_4BIT
;
736 org_data
|= VIA_CRDR_SDMODE_4BIT
;
738 if (ios
->power_mode
== MMC_POWER_OFF
)
739 org_data
&= ~VIA_CRDR_SDMODE_CLK_ON
;
741 org_data
|= VIA_CRDR_SDMODE_CLK_ON
;
743 if (ios
->timing
== MMC_TIMING_SD_HS
)
744 sdextctrl
|= VIA_CRDR_SDEXTCTRL_HISPD
;
746 sdextctrl
&= ~VIA_CRDR_SDEXTCTRL_HISPD
;
748 writel(org_data
, addrbase
+ VIA_CRDR_SDBUSMODE
);
749 writel(sdextctrl
, addrbase
+ VIA_CRDR_SDEXTCTRL
);
751 if (ios
->clock
>= 48000000)
753 else if (ios
->clock
>= 33000000)
755 else if (ios
->clock
>= 24000000)
757 else if (ios
->clock
>= 16000000)
759 else if (ios
->clock
>= 12000000)
761 else if (ios
->clock
>= 8000000)
764 clock
= PCI_CLK_375K
;
766 addrbase
= host
->pcictrl_mmiobase
;
767 if (readb(addrbase
+ VIA_CRDR_PCISDCCLK
) != clock
)
768 writeb(clock
, addrbase
+ VIA_CRDR_PCISDCCLK
);
771 spin_unlock_irqrestore(&host
->lock
, flags
);
773 if (ios
->power_mode
!= MMC_POWER_OFF
)
774 via_sdc_set_power(host
, ios
->vdd
, 1);
776 via_sdc_set_power(host
, ios
->vdd
, 0);
779 static int via_sdc_get_ro(struct mmc_host
*mmc
)
781 struct via_crdr_mmc_host
*host
;
785 host
= mmc_priv(mmc
);
787 spin_lock_irqsave(&host
->lock
, flags
);
789 status
= readw(host
->sdhc_mmiobase
+ VIA_CRDR_SDSTATUS
);
791 spin_unlock_irqrestore(&host
->lock
, flags
);
793 return !(status
& VIA_CRDR_SDSTS_WP
);
796 static const struct mmc_host_ops via_sdc_ops
= {
797 .request
= via_sdc_request
,
798 .set_ios
= via_sdc_set_ios
,
799 .get_ro
= via_sdc_get_ro
,
802 static void via_reset_pcictrl(struct via_crdr_mmc_host
*host
)
804 void __iomem
*addrbase
;
808 addrbase
= host
->pcictrl_mmiobase
;
810 spin_lock_irqsave(&host
->lock
, flags
);
812 via_save_pcictrlreg(host
);
813 via_save_sdcreg(host
);
815 spin_unlock_irqrestore(&host
->lock
, flags
);
817 gatt
= VIA_CRDR_PCICLKGATT_PAD_PWRON
;
818 if (host
->power
== MMC_VDD_165_195
)
819 gatt
&= VIA_CRDR_PCICLKGATT_3V3
;
821 gatt
|= VIA_CRDR_PCICLKGATT_3V3
;
822 writeb(gatt
, host
->pcictrl_mmiobase
+ VIA_CRDR_PCICLKGATT
);
823 via_pwron_sleep(host
);
824 gatt
|= VIA_CRDR_PCICLKGATT_SFTRST
;
825 writeb(gatt
, host
->pcictrl_mmiobase
+ VIA_CRDR_PCICLKGATT
);
828 spin_lock_irqsave(&host
->lock
, flags
);
830 via_restore_pcictrlreg(host
);
831 via_restore_sdcreg(host
);
834 spin_unlock_irqrestore(&host
->lock
, flags
);
837 static void via_sdc_cmd_isr(struct via_crdr_mmc_host
*host
, u16 intmask
)
839 BUG_ON(intmask
== 0);
842 pr_err("%s: Got command interrupt 0x%x even "
843 "though no command operation was in progress.\n",
844 mmc_hostname(host
->mmc
), intmask
);
848 if (intmask
& VIA_CRDR_SDSTS_CRTO
)
849 host
->cmd
->error
= -ETIMEDOUT
;
850 else if (intmask
& VIA_CRDR_SDSTS_SC
)
851 host
->cmd
->error
= -EILSEQ
;
853 if (host
->cmd
->error
)
854 tasklet_schedule(&host
->finish_tasklet
);
855 else if (intmask
& VIA_CRDR_SDSTS_CRD
)
856 via_sdc_finish_command(host
);
859 static void via_sdc_data_isr(struct via_crdr_mmc_host
*host
, u16 intmask
)
861 BUG_ON(intmask
== 0);
863 if (intmask
& VIA_CRDR_SDSTS_DT
)
864 host
->data
->error
= -ETIMEDOUT
;
865 else if (intmask
& (VIA_CRDR_SDSTS_RC
| VIA_CRDR_SDSTS_WC
))
866 host
->data
->error
= -EILSEQ
;
868 via_sdc_finish_data(host
);
871 static irqreturn_t
via_sdc_isr(int irq
, void *dev_id
)
873 struct via_crdr_mmc_host
*sdhost
= dev_id
;
874 void __iomem
*addrbase
;
882 spin_lock(&sdhost
->lock
);
884 addrbase
= sdhost
->pcictrl_mmiobase
;
885 pci_status
= readb(addrbase
+ VIA_CRDR_PCIINTSTATUS
);
886 if (!(pci_status
& VIA_CRDR_PCIINTSTATUS_SDC
)) {
891 addrbase
= sdhost
->sdhc_mmiobase
;
892 sd_status
= readw(addrbase
+ VIA_CRDR_SDSTATUS
);
893 sd_status
&= VIA_CRDR_SDSTS_INT_MASK
;
894 sd_status
&= ~VIA_CRDR_SDSTS_IGN_MASK
;
900 if (sd_status
& VIA_CRDR_SDSTS_CIR
) {
901 writew(sd_status
& VIA_CRDR_SDSTS_CIR
,
902 addrbase
+ VIA_CRDR_SDSTATUS
);
904 schedule_work(&sdhost
->carddet_work
);
907 sd_status
&= ~VIA_CRDR_SDSTS_CIR
;
908 if (sd_status
& VIA_CRDR_SDSTS_CMD_MASK
) {
909 writew(sd_status
& VIA_CRDR_SDSTS_CMD_MASK
,
910 addrbase
+ VIA_CRDR_SDSTATUS
);
911 via_sdc_cmd_isr(sdhost
, sd_status
& VIA_CRDR_SDSTS_CMD_MASK
);
913 if (sd_status
& VIA_CRDR_SDSTS_DATA_MASK
) {
914 writew(sd_status
& VIA_CRDR_SDSTS_DATA_MASK
,
915 addrbase
+ VIA_CRDR_SDSTATUS
);
916 via_sdc_data_isr(sdhost
, sd_status
& VIA_CRDR_SDSTS_DATA_MASK
);
919 sd_status
&= ~(VIA_CRDR_SDSTS_CMD_MASK
| VIA_CRDR_SDSTS_DATA_MASK
);
921 pr_err("%s: Unexpected interrupt 0x%x\n",
922 mmc_hostname(sdhost
->mmc
), sd_status
);
923 writew(sd_status
, addrbase
+ VIA_CRDR_SDSTATUS
);
926 result
= IRQ_HANDLED
;
930 spin_unlock(&sdhost
->lock
);
935 static void via_sdc_timeout(unsigned long ulongdata
)
937 struct via_crdr_mmc_host
*sdhost
;
940 sdhost
= (struct via_crdr_mmc_host
*)ulongdata
;
942 spin_lock_irqsave(&sdhost
->lock
, flags
);
945 pr_err("%s: Timeout waiting for hardware interrupt."
946 "cmd:0x%x\n", mmc_hostname(sdhost
->mmc
),
947 sdhost
->mrq
->cmd
->opcode
);
950 writel(VIA_CRDR_DMACTRL_SFTRST
,
951 sdhost
->ddma_mmiobase
+ VIA_CRDR_DMACTRL
);
952 sdhost
->data
->error
= -ETIMEDOUT
;
953 via_sdc_finish_data(sdhost
);
956 sdhost
->cmd
->error
= -ETIMEDOUT
;
958 sdhost
->mrq
->cmd
->error
= -ETIMEDOUT
;
959 tasklet_schedule(&sdhost
->finish_tasklet
);
964 spin_unlock_irqrestore(&sdhost
->lock
, flags
);
967 static void via_sdc_tasklet_finish(unsigned long param
)
969 struct via_crdr_mmc_host
*host
;
971 struct mmc_request
*mrq
;
973 host
= (struct via_crdr_mmc_host
*)param
;
975 spin_lock_irqsave(&host
->lock
, flags
);
977 del_timer(&host
->timer
);
983 spin_unlock_irqrestore(&host
->lock
, flags
);
985 mmc_request_done(host
->mmc
, mrq
);
988 static void via_sdc_card_detect(struct work_struct
*work
)
990 struct via_crdr_mmc_host
*host
;
991 void __iomem
*addrbase
;
995 host
= container_of(work
, struct via_crdr_mmc_host
, carddet_work
);
997 addrbase
= host
->ddma_mmiobase
;
998 writel(VIA_CRDR_DMACTRL_SFTRST
, addrbase
+ VIA_CRDR_DMACTRL
);
1000 spin_lock_irqsave(&host
->lock
, flags
);
1002 addrbase
= host
->pcictrl_mmiobase
;
1003 writeb(VIA_CRDR_PCIDMACLK_SDC
, addrbase
+ VIA_CRDR_PCIDMACLK
);
1005 addrbase
= host
->sdhc_mmiobase
;
1006 status
= readw(addrbase
+ VIA_CRDR_SDSTATUS
);
1007 if (!(status
& VIA_CRDR_SDSTS_SLOTG
)) {
1009 pr_err("%s: Card removed during transfer!\n",
1010 mmc_hostname(host
->mmc
));
1011 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1012 tasklet_schedule(&host
->finish_tasklet
);
1016 spin_unlock_irqrestore(&host
->lock
, flags
);
1018 via_reset_pcictrl(host
);
1020 spin_lock_irqsave(&host
->lock
, flags
);
1024 spin_unlock_irqrestore(&host
->lock
, flags
);
1026 via_print_pcictrl(host
);
1027 via_print_sdchc(host
);
1029 mmc_detect_change(host
->mmc
, msecs_to_jiffies(500));
1032 static void via_init_mmc_host(struct via_crdr_mmc_host
*host
)
1034 struct mmc_host
*mmc
= host
->mmc
;
1035 void __iomem
*addrbase
;
1039 init_timer(&host
->timer
);
1040 host
->timer
.data
= (unsigned long)host
;
1041 host
->timer
.function
= via_sdc_timeout
;
1043 spin_lock_init(&host
->lock
);
1045 mmc
->f_min
= VIA_CRDR_MIN_CLOCK
;
1046 mmc
->f_max
= VIA_CRDR_MAX_CLOCK
;
1047 mmc
->ocr_avail
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
1048 mmc
->caps
= MMC_CAP_4_BIT_DATA
| MMC_CAP_SD_HIGHSPEED
;
1049 mmc
->ops
= &via_sdc_ops
;
1051 /*Hardware cannot do scatter lists*/
1052 mmc
->max_hw_segs
= 1;
1053 mmc
->max_phys_segs
= 1;
1055 mmc
->max_blk_size
= VIA_CRDR_MAX_BLOCK_LENGTH
;
1056 mmc
->max_blk_count
= VIA_CRDR_MAX_BLOCK_COUNT
;
1058 mmc
->max_seg_size
= mmc
->max_blk_size
* mmc
->max_blk_count
;
1059 mmc
->max_req_size
= mmc
->max_seg_size
;
1061 INIT_WORK(&host
->carddet_work
, via_sdc_card_detect
);
1063 tasklet_init(&host
->finish_tasklet
, via_sdc_tasklet_finish
,
1064 (unsigned long)host
);
1066 addrbase
= host
->sdhc_mmiobase
;
1067 writel(0x0, addrbase
+ VIA_CRDR_SDINTMASK
);
1070 lenreg
= VIA_CRDR_SDBLKLEN_GPIDET
| VIA_CRDR_SDBLKLEN_INTEN
;
1071 writel(lenreg
, addrbase
+ VIA_CRDR_SDBLKLEN
);
1073 status
= readw(addrbase
+ VIA_CRDR_SDSTATUS
);
1074 status
&= VIA_CRDR_SDSTS_W1C_MASK
;
1075 writew(status
, addrbase
+ VIA_CRDR_SDSTATUS
);
1077 status
= readw(addrbase
+ VIA_CRDR_SDSTATUS2
);
1078 status
|= VIA_CRDR_SDSTS_CFE
;
1079 writew(status
, addrbase
+ VIA_CRDR_SDSTATUS2
);
1081 writeb(0x0, addrbase
+ VIA_CRDR_SDEXTCTRL
);
1083 writel(VIA_CRDR_SDACTIVE_INTMASK
, addrbase
+ VIA_CRDR_SDINTMASK
);
1087 static int __devinit
via_sd_probe(struct pci_dev
*pcidev
,
1088 const struct pci_device_id
*id
)
1090 struct mmc_host
*mmc
;
1091 struct via_crdr_mmc_host
*sdhost
;
1096 pci_read_config_byte(pcidev
, PCI_CLASS_REVISION
, &rev
);
1098 ": VIA SDMMC controller found at %s [%04x:%04x] (rev %x)\n",
1099 pci_name(pcidev
), (int)pcidev
->vendor
, (int)pcidev
->device
,
1102 ret
= pci_enable_device(pcidev
);
1106 ret
= pci_request_regions(pcidev
, DRV_NAME
);
1110 pci_write_config_byte(pcidev
, VIA_CRDR_PCI_WORK_MODE
, 0);
1111 pci_write_config_byte(pcidev
, VIA_CRDR_PCI_DBG_MODE
, 0);
1113 mmc
= mmc_alloc_host(sizeof(struct via_crdr_mmc_host
), &pcidev
->dev
);
1119 sdhost
= mmc_priv(mmc
);
1121 dev_set_drvdata(&pcidev
->dev
, sdhost
);
1123 len
= pci_resource_len(pcidev
, 0);
1124 base
= pci_resource_start(pcidev
, 0);
1125 sdhost
->mmiobase
= ioremap_nocache(base
, len
);
1126 if (!sdhost
->mmiobase
) {
1131 sdhost
->sdhc_mmiobase
=
1132 sdhost
->mmiobase
+ VIA_CRDR_SDC_OFF
;
1133 sdhost
->ddma_mmiobase
=
1134 sdhost
->mmiobase
+ VIA_CRDR_DDMA_OFF
;
1135 sdhost
->pcictrl_mmiobase
=
1136 sdhost
->mmiobase
+ VIA_CRDR_PCICTRL_OFF
;
1138 sdhost
->power
= MMC_VDD_165_195
;
1140 gatt
= VIA_CRDR_PCICLKGATT_3V3
| VIA_CRDR_PCICLKGATT_PAD_PWRON
;
1141 writeb(gatt
, sdhost
->pcictrl_mmiobase
+ VIA_CRDR_PCICLKGATT
);
1142 via_pwron_sleep(sdhost
);
1143 gatt
|= VIA_CRDR_PCICLKGATT_SFTRST
;
1144 writeb(gatt
, sdhost
->pcictrl_mmiobase
+ VIA_CRDR_PCICLKGATT
);
1147 via_init_mmc_host(sdhost
);
1150 request_irq(pcidev
->irq
, via_sdc_isr
, IRQF_SHARED
, DRV_NAME
,
1155 writeb(VIA_CRDR_PCIINTCTRL_SDCIRQEN
,
1156 sdhost
->pcictrl_mmiobase
+ VIA_CRDR_PCIINTCTRL
);
1157 writeb(VIA_CRDR_PCITMOCTRL_1024MS
,
1158 sdhost
->pcictrl_mmiobase
+ VIA_CRDR_PCITMOCTRL
);
1160 /* device-specific quirks */
1161 if (pcidev
->subsystem_vendor
== PCI_VENDOR_ID_LENOVO
&&
1162 pcidev
->subsystem_device
== 0x3891)
1163 sdhost
->quirks
= VIA_CRDR_QUIRK_300MS_PWRDELAY
;
1170 iounmap(sdhost
->mmiobase
);
1172 dev_set_drvdata(&pcidev
->dev
, NULL
);
1175 pci_release_regions(pcidev
);
1177 pci_disable_device(pcidev
);
1182 static void __devexit
via_sd_remove(struct pci_dev
*pcidev
)
1184 struct via_crdr_mmc_host
*sdhost
= pci_get_drvdata(pcidev
);
1185 unsigned long flags
;
1188 spin_lock_irqsave(&sdhost
->lock
, flags
);
1190 /* Ensure we don't accept more commands from mmc layer */
1193 /* Disable generating further interrupts */
1194 writeb(0x0, sdhost
->pcictrl_mmiobase
+ VIA_CRDR_PCIINTCTRL
);
1198 printk(KERN_ERR
"%s: Controller removed during "
1199 "transfer\n", mmc_hostname(sdhost
->mmc
));
1201 /* make sure all DMA is stopped */
1202 writel(VIA_CRDR_DMACTRL_SFTRST
,
1203 sdhost
->ddma_mmiobase
+ VIA_CRDR_DMACTRL
);
1205 sdhost
->mrq
->cmd
->error
= -ENOMEDIUM
;
1206 if (sdhost
->mrq
->stop
)
1207 sdhost
->mrq
->stop
->error
= -ENOMEDIUM
;
1208 tasklet_schedule(&sdhost
->finish_tasklet
);
1210 spin_unlock_irqrestore(&sdhost
->lock
, flags
);
1212 mmc_remove_host(sdhost
->mmc
);
1214 free_irq(pcidev
->irq
, sdhost
);
1216 del_timer_sync(&sdhost
->timer
);
1218 tasklet_kill(&sdhost
->finish_tasklet
);
1220 /* switch off power */
1221 gatt
= readb(sdhost
->pcictrl_mmiobase
+ VIA_CRDR_PCICLKGATT
);
1222 gatt
&= ~VIA_CRDR_PCICLKGATT_PAD_PWRON
;
1223 writeb(gatt
, sdhost
->pcictrl_mmiobase
+ VIA_CRDR_PCICLKGATT
);
1225 iounmap(sdhost
->mmiobase
);
1226 dev_set_drvdata(&pcidev
->dev
, NULL
);
1227 mmc_free_host(sdhost
->mmc
);
1228 pci_release_regions(pcidev
);
1229 pci_disable_device(pcidev
);
1232 ": VIA SDMMC controller at %s [%04x:%04x] has been removed\n",
1233 pci_name(pcidev
), (int)pcidev
->vendor
, (int)pcidev
->device
);
1238 static void via_init_sdc_pm(struct via_crdr_mmc_host
*host
)
1240 struct sdhcreg
*pm_sdhcreg
;
1241 void __iomem
*addrbase
;
1245 pm_sdhcreg
= &(host
->pm_sdhc_reg
);
1246 addrbase
= host
->sdhc_mmiobase
;
1248 writel(0x0, addrbase
+ VIA_CRDR_SDINTMASK
);
1250 lenreg
= VIA_CRDR_SDBLKLEN_GPIDET
| VIA_CRDR_SDBLKLEN_INTEN
;
1251 writel(lenreg
, addrbase
+ VIA_CRDR_SDBLKLEN
);
1253 status
= readw(addrbase
+ VIA_CRDR_SDSTATUS
);
1254 status
&= VIA_CRDR_SDSTS_W1C_MASK
;
1255 writew(status
, addrbase
+ VIA_CRDR_SDSTATUS
);
1257 status
= readw(addrbase
+ VIA_CRDR_SDSTATUS2
);
1258 status
|= VIA_CRDR_SDSTS_CFE
;
1259 writew(status
, addrbase
+ VIA_CRDR_SDSTATUS2
);
1261 writel(pm_sdhcreg
->sdcontrol_reg
, addrbase
+ VIA_CRDR_SDCTRL
);
1262 writel(pm_sdhcreg
->sdcmdarg_reg
, addrbase
+ VIA_CRDR_SDCARG
);
1263 writel(pm_sdhcreg
->sdintmask_reg
, addrbase
+ VIA_CRDR_SDINTMASK
);
1264 writel(pm_sdhcreg
->sdrsptmo_reg
, addrbase
+ VIA_CRDR_SDRSPTMO
);
1265 writel(pm_sdhcreg
->sdclksel_reg
, addrbase
+ VIA_CRDR_SDCLKSEL
);
1266 writel(pm_sdhcreg
->sdextctrl_reg
, addrbase
+ VIA_CRDR_SDEXTCTRL
);
1268 via_print_pcictrl(host
);
1269 via_print_sdchc(host
);
1272 static int via_sd_suspend(struct pci_dev
*pcidev
, pm_message_t state
)
1274 struct via_crdr_mmc_host
*host
;
1277 host
= pci_get_drvdata(pcidev
);
1279 via_save_pcictrlreg(host
);
1280 via_save_sdcreg(host
);
1282 ret
= mmc_suspend_host(host
->mmc
);
1284 pci_save_state(pcidev
);
1285 pci_enable_wake(pcidev
, pci_choose_state(pcidev
, state
), 0);
1286 pci_disable_device(pcidev
);
1287 pci_set_power_state(pcidev
, pci_choose_state(pcidev
, state
));
1292 static int via_sd_resume(struct pci_dev
*pcidev
)
1294 struct via_crdr_mmc_host
*sdhost
;
1298 sdhost
= pci_get_drvdata(pcidev
);
1300 gatt
= VIA_CRDR_PCICLKGATT_PAD_PWRON
;
1301 if (sdhost
->power
== MMC_VDD_165_195
)
1302 gatt
&= ~VIA_CRDR_PCICLKGATT_3V3
;
1304 gatt
|= VIA_CRDR_PCICLKGATT_3V3
;
1305 writeb(gatt
, sdhost
->pcictrl_mmiobase
+ VIA_CRDR_PCICLKGATT
);
1306 via_pwron_sleep(sdhost
);
1307 gatt
|= VIA_CRDR_PCICLKGATT_SFTRST
;
1308 writeb(gatt
, sdhost
->pcictrl_mmiobase
+ VIA_CRDR_PCICLKGATT
);
1313 pci_set_power_state(pcidev
, PCI_D0
);
1314 pci_restore_state(pcidev
);
1315 ret
= pci_enable_device(pcidev
);
1319 via_restore_pcictrlreg(sdhost
);
1320 via_init_sdc_pm(sdhost
);
1322 ret
= mmc_resume_host(sdhost
->mmc
);
1327 #else /* CONFIG_PM */
1329 #define via_sd_suspend NULL
1330 #define via_sd_resume NULL
1332 #endif /* CONFIG_PM */
1334 static struct pci_driver via_sd_driver
= {
1336 .id_table
= via_ids
,
1337 .probe
= via_sd_probe
,
1338 .remove
= __devexit_p(via_sd_remove
),
1339 .suspend
= via_sd_suspend
,
1340 .resume
= via_sd_resume
,
1343 static int __init
via_sd_drv_init(void)
1345 pr_info(DRV_NAME
": VIA SD/MMC Card Reader driver "
1346 "(C) 2008 VIA Technologies, Inc.\n");
1348 return pci_register_driver(&via_sd_driver
);
1351 static void __exit
via_sd_drv_exit(void)
1353 pci_unregister_driver(&via_sd_driver
);
1356 module_init(via_sd_drv_init
);
1357 module_exit(via_sd_drv_exit
);
1359 MODULE_LICENSE("GPL");
1360 MODULE_AUTHOR("VIA Technologies Inc.");
1361 MODULE_DESCRIPTION("VIA SD/MMC Card Interface driver");