release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/media/dvb/frontends/stv0297.c

   1 /*
   2     Driver for STV0297 demodulator
   3
   4     Copyright (C) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
   5     Copyright (C) 2003-2004 Dennis Noermann <dennis.noermann@noernet.de>
   6
   7     This program is free software; you can redistribute it and/or modify
   8     it under the terms of the GNU General Public License as published by
   9     the Free Software Foundation; either version 2 of the License, or
  10     (at your option) any later version.
  11
  12     This program is distributed in the hope that it will be useful,
  13     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15     GNU General Public License for more details.
  16
  17     You should have received a copy of the GNU General Public License
  18     along with this program; if not, write to the Free Software
  19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20 */
  21
  22 #include <linux/init.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/string.h>
  26 #include <linux/delay.h>
  27 #include <linux/jiffies.h>
  28 #include <linux/slab.h>
  29
  30 #include "dvb_frontend.h"
  31 #include "stv0297.h"
  32
  33 struct stv0297_state {
  34         struct i2c_adapter *i2c;
  35         const struct stv0297_config *config;
  36         struct dvb_frontend frontend;
  37
  38         unsigned long last_ber;
  39         unsigned long base_freq;
  40 };
  41
  42 #define dprintk(x...) printk(x)
  43
  44 #define STV0297_CLOCK_KHZ   28900
  45
  46
  47 static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data)
  48 {
  49         int ret;
  50         u8 buf[] = { reg, data };
  51         struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };
  52
  53         ret = i2c_transfer(state->i2c, &msg, 1);
  54
  55         if (ret != 1)
  56                 dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
  57                         "ret == %i)\n", __func__, reg, data, ret);
  58
  59         return (ret != 1) ? -1 : 0;
  60 }
  61
  62 static int stv0297_readreg(struct stv0297_state *state, u8 reg)
  63 {
  64         int ret;
  65         u8 b0[] = { reg };
  66         u8 b1[] = { 0 };
  67         struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 1},
  68                                  {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
  69                                };
  70
  71         // this device needs a STOP between the register and data
  72         if (state->config->stop_during_read) {
  73                 if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
  74                         dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
  75                         return -1;
  76                 }
  77                 if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
  78                         dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
  79                         return -1;
  80                 }
  81         } else {
  82                 if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
  83                         dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
  84                         return -1;
  85                 }
  86         }
  87
  88         return b1[0];
  89 }
  90
  91 static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data)
  92 {
  93         int val;
  94
  95         val = stv0297_readreg(state, reg);
  96         val &= ~mask;
  97         val |= (data & mask);
  98         stv0297_writereg(state, reg, val);
  99
 100         return 0;
 101 }
 102
 103 static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len)
 104 {
 105         int ret;
 106         struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf =
 107                                   &reg1,.len = 1},
 108         {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len}
 109         };
 110
 111         // this device needs a STOP between the register and data
 112         if (state->config->stop_during_read) {
 113                 if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
 114                         dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
 115                         return -1;
 116                 }
 117                 if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
 118                         dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
 119                         return -1;
 120                 }
 121         } else {
 122                 if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
 123                         dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
 124                         return -1;
 125                 }
 126         }
 127
 128         return 0;
 129 }
 130
 131 static u32 stv0297_get_symbolrate(struct stv0297_state *state)
 132 {
 133         u64 tmp;
 134
 135         tmp = stv0297_readreg(state, 0x55);
 136         tmp |= stv0297_readreg(state, 0x56) << 8;
 137         tmp |= stv0297_readreg(state, 0x57) << 16;
 138         tmp |= stv0297_readreg(state, 0x58) << 24;
 139
 140         tmp *= STV0297_CLOCK_KHZ;
 141         tmp >>= 32;
 142
 143         return (u32) tmp;
 144 }
 145
 146 static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate)
 147 {
 148         long tmp;
 149
 150         tmp = 131072L * srate;  /* 131072 = 2^17  */
 151         tmp = tmp / (STV0297_CLOCK_KHZ / 4);    /* 1/4 = 2^-2 */
 152         tmp = tmp * 8192L;      /* 8192 = 2^13 */
 153
 154         stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF));
 155         stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8));
 156         stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16));
 157         stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24));
 158 }
 159
 160 static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate)
 161 {
 162         long tmp;
 163
 164         tmp = (long) fshift *262144L;   /* 262144 = 2*18 */
 165         tmp /= symrate;
 166         tmp *= 1024;            /* 1024 = 2*10   */
 167
 168         // adjust
 169         if (tmp >= 0) {
 170                 tmp += 500000;
 171         } else {
 172                 tmp -= 500000;
 173         }
 174         tmp /= 1000000;
 175
 176         stv0297_writereg(state, 0x60, tmp & 0xFF);
 177         stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0);
 178 }
 179
 180 static void stv0297_set_carrieroffset(struct stv0297_state *state, long offset)
 181 {
 182         long tmp;
 183
 184         /* symrate is hardcoded to 10000 */
 185         tmp = offset * 26844L;  /* (2**28)/10000 */
 186         if (tmp < 0)
 187                 tmp += 0x10000000;
 188         tmp &= 0x0FFFFFFF;
 189
 190         stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF));
 191         stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8));
 192         stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16));
 193         stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f);
 194 }
 195
 196 /*
 197 static long stv0297_get_carrieroffset(struct stv0297_state *state)
 198 {
 199         s64 tmp;
 200
 201         stv0297_writereg(state, 0x6B, 0x00);
 202
 203         tmp = stv0297_readreg(state, 0x66);
 204         tmp |= (stv0297_readreg(state, 0x67) << 8);
 205         tmp |= (stv0297_readreg(state, 0x68) << 16);
 206         tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24;
 207
 208         tmp *= stv0297_get_symbolrate(state);
 209         tmp >>= 28;
 210
 211         return (s32) tmp;
 212 }
 213 */
 214
 215 static void stv0297_set_initialdemodfreq(struct stv0297_state *state, long freq)
 216 {
 217         s32 tmp;
 218
 219         if (freq > 10000)
 220                 freq -= STV0297_CLOCK_KHZ;
 221
 222         tmp = (STV0297_CLOCK_KHZ * 1000) / (1 << 16);
 223         tmp = (freq * 1000) / tmp;
 224         if (tmp > 0xffff)
 225                 tmp = 0xffff;
 226
 227         stv0297_writereg_mask(state, 0x25, 0x80, 0x80);
 228         stv0297_writereg(state, 0x21, tmp >> 8);
 229         stv0297_writereg(state, 0x20, tmp);
 230 }
 231
 232 static int stv0297_set_qam(struct stv0297_state *state, fe_modulation_t modulation)
 233 {
 234         int val = 0;
 235
 236         switch (modulation) {
 237         case QAM_16:
 238                 val = 0;
 239                 break;
 240
 241         case QAM_32:
 242                 val = 1;
 243                 break;
 244
 245         case QAM_64:
 246                 val = 4;
 247                 break;
 248
 249         case QAM_128:
 250                 val = 2;
 251                 break;
 252
 253         case QAM_256:
 254                 val = 3;
 255                 break;
 256
 257         default:
 258                 return -EINVAL;
 259         }
 260
 261         stv0297_writereg_mask(state, 0x00, 0x70, val << 4);
 262
 263         return 0;
 264 }
 265
 266 static int stv0297_set_inversion(struct stv0297_state *state, fe_spectral_inversion_t inversion)
 267 {
 268         int val = 0;
 269
 270         switch (inversion) {
 271         case INVERSION_OFF:
 272                 val = 0;
 273                 break;
 274
 275         case INVERSION_ON:
 276                 val = 1;
 277                 break;
 278
 279         default:
 280                 return -EINVAL;
 281         }
 282
 283         stv0297_writereg_mask(state, 0x83, 0x08, val << 3);
 284
 285         return 0;
 286 }
 287
 288 static int stv0297_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 289 {
 290         struct stv0297_state *state = fe->demodulator_priv;
 291
 292         if (enable) {
 293                 stv0297_writereg(state, 0x87, 0x78);
 294                 stv0297_writereg(state, 0x86, 0xc8);
 295         }
 296
 297         return 0;
 298 }
 299
 300 static int stv0297_init(struct dvb_frontend *fe)
 301 {
 302         struct stv0297_state *state = fe->demodulator_priv;
 303         int i;
 304
 305         /* load init table */
 306         for (i=0; !(state->config->inittab[i] == 0xff && state->config->inittab[i+1] == 0xff); i+=2)
 307                 stv0297_writereg(state, state->config->inittab[i], state->config->inittab[i+1]);
 308         msleep(200);
 309
 310         state->last_ber = 0;
 311
 312         return 0;
 313 }
 314
 315 static int stv0297_sleep(struct dvb_frontend *fe)
 316 {
 317         struct stv0297_state *state = fe->demodulator_priv;
 318
 319         stv0297_writereg_mask(state, 0x80, 1, 1);
 320
 321         return 0;
 322 }
 323
 324 static int stv0297_read_status(struct dvb_frontend *fe, fe_status_t * status)
 325 {
 326         struct stv0297_state *state = fe->demodulator_priv;
 327
 328         u8 sync = stv0297_readreg(state, 0xDF);
 329
 330         *status = 0;
 331         if (sync & 0x80)
 332                 *status |=
 333                         FE_HAS_SYNC | FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_LOCK;
 334         return 0;
 335 }
 336
 337 static int stv0297_read_ber(struct dvb_frontend *fe, u32 * ber)
 338 {
 339         struct stv0297_state *state = fe->demodulator_priv;
 340         u8 BER[3];
 341
 342         stv0297_readregs(state, 0xA0, BER, 3);
 343         if (!(BER[0] & 0x80)) {
 344                 state->last_ber = BER[2] << 8 | BER[1];
 345                 stv0297_writereg_mask(state, 0xA0, 0x80, 0x80);
 346         }
 347
 348         *ber = state->last_ber;
 349
 350         return 0;
 351 }
 352
 353
 354 static int stv0297_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
 355 {
 356         struct stv0297_state *state = fe->demodulator_priv;
 357         u8 STRENGTH[3];
 358         u16 tmp;
 359
 360         stv0297_readregs(state, 0x41, STRENGTH, 3);
 361         tmp = (STRENGTH[1] & 0x03) << 8 | STRENGTH[0];
 362         if (STRENGTH[2] & 0x20) {
 363                 if (tmp < 0x200)
 364                         tmp = 0;
 365                 else
 366                         tmp = tmp - 0x200;
 367         } else {
 368                 if (tmp > 0x1ff)
 369                         tmp = 0;
 370                 else
 371                         tmp = 0x1ff - tmp;
 372         }
 373         *strength = (tmp << 7) | (tmp >> 2);
 374         return 0;
 375 }
 376
 377 static int stv0297_read_snr(struct dvb_frontend *fe, u16 * snr)
 378 {
 379         struct stv0297_state *state = fe->demodulator_priv;
 380         u8 SNR[2];
 381
 382         stv0297_readregs(state, 0x07, SNR, 2);
 383         *snr = SNR[1] << 8 | SNR[0];
 384
 385         return 0;
 386 }
 387
 388 static int stv0297_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
 389 {
 390         struct stv0297_state *state = fe->demodulator_priv;
 391
 392         stv0297_writereg_mask(state, 0xDF, 0x03, 0x03); /* freeze the counters */
 393
 394         *ucblocks = (stv0297_readreg(state, 0xD5) << 8)
 395                 | stv0297_readreg(state, 0xD4);
 396
 397         stv0297_writereg_mask(state, 0xDF, 0x03, 0x02); /* clear the counters */
 398         stv0297_writereg_mask(state, 0xDF, 0x03, 0x01); /* re-enable the counters */
 399
 400         return 0;
 401 }
 402
 403 static int stv0297_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
 404 {
 405         struct stv0297_state *state = fe->demodulator_priv;
 406         int u_threshold;
 407         int initial_u;
 408         int blind_u;
 409         int delay;
 410         int sweeprate;
 411         int carrieroffset;
 412         unsigned long starttime;
 413         unsigned long timeout;
 414         fe_spectral_inversion_t inversion;
 415
 416         switch (p->u.qam.modulation) {
 417         case QAM_16:
 418         case QAM_32:
 419         case QAM_64:
 420                 delay = 100;
 421                 sweeprate = 1000;
 422                 break;
 423
 424         case QAM_128:
 425         case QAM_256:
 426                 delay = 200;
 427                 sweeprate = 500;
 428                 break;
 429
 430         default:
 431                 return -EINVAL;
 432         }
 433
 434         // determine inversion dependant parameters
 435         inversion = p->inversion;
 436         if (state->config->invert)
 437                 inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
 438         carrieroffset = -330;
 439         switch (inversion) {
 440         case INVERSION_OFF:
 441                 break;
 442
 443         case INVERSION_ON:
 444                 sweeprate = -sweeprate;
 445                 carrieroffset = -carrieroffset;
 446                 break;
 447
 448         default:
 449                 return -EINVAL;
 450         }
 451
 452         stv0297_init(fe);
 453         if (fe->ops.tuner_ops.set_params) {
 454                 fe->ops.tuner_ops.set_params(fe, p);
 455                 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
 456         }
 457
 458         /* clear software interrupts */
 459         stv0297_writereg(state, 0x82, 0x0);
 460
 461         /* set initial demodulation frequency */
 462         stv0297_set_initialdemodfreq(state, 7250);
 463
 464         /* setup AGC */
 465         stv0297_writereg_mask(state, 0x43, 0x10, 0x00);
 466         stv0297_writereg(state, 0x41, 0x00);
 467         stv0297_writereg_mask(state, 0x42, 0x03, 0x01);
 468         stv0297_writereg_mask(state, 0x36, 0x60, 0x00);
 469         stv0297_writereg_mask(state, 0x36, 0x18, 0x00);
 470         stv0297_writereg_mask(state, 0x71, 0x80, 0x80);
 471         stv0297_writereg(state, 0x72, 0x00);
 472         stv0297_writereg(state, 0x73, 0x00);
 473         stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);
 474         stv0297_writereg_mask(state, 0x43, 0x08, 0x00);
 475         stv0297_writereg_mask(state, 0x71, 0x80, 0x00);
 476
 477         /* setup STL */
 478         stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);
 479         stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);
 480         stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);
 481         stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);
 482         stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);
 483
 484         /* disable frequency sweep */
 485         stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
 486
 487         /* reset deinterleaver */
 488         stv0297_writereg_mask(state, 0x81, 0x01, 0x01);
 489         stv0297_writereg_mask(state, 0x81, 0x01, 0x00);
 490
 491         /* ??? */
 492         stv0297_writereg_mask(state, 0x83, 0x20, 0x20);
 493         stv0297_writereg_mask(state, 0x83, 0x20, 0x00);
 494
 495         /* reset equaliser */
 496         u_threshold = stv0297_readreg(state, 0x00) & 0xf;
 497         initial_u = stv0297_readreg(state, 0x01) >> 4;
 498         blind_u = stv0297_readreg(state, 0x01) & 0xf;
 499         stv0297_writereg_mask(state, 0x84, 0x01, 0x01);
 500         stv0297_writereg_mask(state, 0x84, 0x01, 0x00);
 501         stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);
 502         stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);
 503         stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);
 504
 505         /* data comes from internal A/D */
 506         stv0297_writereg_mask(state, 0x87, 0x80, 0x00);
 507
 508         /* clear phase registers */
 509         stv0297_writereg(state, 0x63, 0x00);
 510         stv0297_writereg(state, 0x64, 0x00);
 511         stv0297_writereg(state, 0x65, 0x00);
 512         stv0297_writereg(state, 0x66, 0x00);
 513         stv0297_writereg(state, 0x67, 0x00);
 514         stv0297_writereg(state, 0x68, 0x00);
 515         stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);
 516
 517         /* set parameters */
 518         stv0297_set_qam(state, p->u.qam.modulation);
 519         stv0297_set_symbolrate(state, p->u.qam.symbol_rate / 1000);
 520         stv0297_set_sweeprate(state, sweeprate, p->u.qam.symbol_rate / 1000);
 521         stv0297_set_carrieroffset(state, carrieroffset);
 522         stv0297_set_inversion(state, inversion);
 523
 524         /* kick off lock */
 525         /* Disable corner detection for higher QAMs */
 526         if (p->u.qam.modulation == QAM_128 ||
 527                 p->u.qam.modulation == QAM_256)
 528                 stv0297_writereg_mask(state, 0x88, 0x08, 0x00);
 529         else
 530                 stv0297_writereg_mask(state, 0x88, 0x08, 0x08);
 531
 532         stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);
 533         stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);
 534         stv0297_writereg_mask(state, 0x43, 0x40, 0x40);
 535         stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);
 536         stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);
 537         stv0297_writereg_mask(state, 0x03, 0x03, 0x03);
 538         stv0297_writereg_mask(state, 0x43, 0x10, 0x10);
 539
 540         /* wait for WGAGC lock */
 541         starttime = jiffies;
 542         timeout = jiffies + msecs_to_jiffies(2000);
 543         while (time_before(jiffies, timeout)) {
 544                 msleep(10);
 545                 if (stv0297_readreg(state, 0x43) & 0x08)
 546                         break;
 547         }
 548         if (time_after(jiffies, timeout)) {
 549                 goto timeout;
 550         }
 551         msleep(20);
 552
 553         /* wait for equaliser partial convergence */
 554         timeout = jiffies + msecs_to_jiffies(500);
 555         while (time_before(jiffies, timeout)) {
 556                 msleep(10);
 557
 558                 if (stv0297_readreg(state, 0x82) & 0x04) {
 559                         break;
 560                 }
 561         }
 562         if (time_after(jiffies, timeout)) {
 563                 goto timeout;
 564         }
 565
 566         /* wait for equaliser full convergence */
 567         timeout = jiffies + msecs_to_jiffies(delay);
 568         while (time_before(jiffies, timeout)) {
 569                 msleep(10);
 570
 571                 if (stv0297_readreg(state, 0x82) & 0x08) {
 572                         break;
 573                 }
 574         }
 575         if (time_after(jiffies, timeout)) {
 576                 goto timeout;
 577         }
 578
 579         /* disable sweep */
 580         stv0297_writereg_mask(state, 0x6a, 1, 0);
 581         stv0297_writereg_mask(state, 0x88, 8, 0);
 582
 583         /* wait for main lock */
 584         timeout = jiffies + msecs_to_jiffies(20);
 585         while (time_before(jiffies, timeout)) {
 586                 msleep(10);
 587
 588                 if (stv0297_readreg(state, 0xDF) & 0x80) {
 589                         break;
 590                 }
 591         }
 592         if (time_after(jiffies, timeout)) {
 593                 goto timeout;
 594         }
 595         msleep(100);
 596
 597         /* is it still locked after that delay? */
 598         if (!(stv0297_readreg(state, 0xDF) & 0x80)) {
 599                 goto timeout;
 600         }
 601
 602         /* success!! */
 603         stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);
 604         state->base_freq = p->frequency;
 605         return 0;
 606
 607 timeout:
 608         stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
 609         return 0;
 610 }
 611
 612 static int stv0297_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
 613 {
 614         struct stv0297_state *state = fe->demodulator_priv;
 615         int reg_00, reg_83;
 616
 617         reg_00 = stv0297_readreg(state, 0x00);
 618         reg_83 = stv0297_readreg(state, 0x83);
 619
 620         p->frequency = state->base_freq;
 621         p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF;
 622         if (state->config->invert)
 623                 p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
 624         p->u.qam.symbol_rate = stv0297_get_symbolrate(state) * 1000;
 625         p->u.qam.fec_inner = FEC_NONE;
 626
 627         switch ((reg_00 >> 4) & 0x7) {
 628         case 0:
 629                 p->u.qam.modulation = QAM_16;
 630                 break;
 631         case 1:
 632                 p->u.qam.modulation = QAM_32;
 633                 break;
 634         case 2:
 635                 p->u.qam.modulation = QAM_128;
 636                 break;
 637         case 3:
 638                 p->u.qam.modulation = QAM_256;
 639                 break;
 640         case 4:
 641                 p->u.qam.modulation = QAM_64;
 642                 break;
 643         }
 644
 645         return 0;
 646 }
 647
 648 static void stv0297_release(struct dvb_frontend *fe)
 649 {
 650         struct stv0297_state *state = fe->demodulator_priv;
 651         kfree(state);
 652 }
 653
 654 static struct dvb_frontend_ops stv0297_ops;
 655
 656 struct dvb_frontend *stv0297_attach(const struct stv0297_config *config,
 657                                     struct i2c_adapter *i2c)
 658 {
 659         struct stv0297_state *state = NULL;
 660
 661         /* allocate memory for the internal state */
 662         state = kzalloc(sizeof(struct stv0297_state), GFP_KERNEL);
 663         if (state == NULL)
 664                 goto error;
 665
 666         /* setup the state */
 667         state->config = config;
 668         state->i2c = i2c;
 669         state->last_ber = 0;
 670         state->base_freq = 0;
 671
 672         /* check if the demod is there */
 673         if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20)
 674                 goto error;
 675
 676         /* create dvb_frontend */
 677         memcpy(&state->frontend.ops, &stv0297_ops, sizeof(struct dvb_frontend_ops));
 678         state->frontend.demodulator_priv = state;
 679         return &state->frontend;
 680
 681 error:
 682         kfree(state);
 683         return NULL;
 684 }
 685
 686 static struct dvb_frontend_ops stv0297_ops = {
 687
 688         .info = {
 689                  .name = "ST STV0297 DVB-C",
 690                  .type = FE_QAM,
 691                  .frequency_min = 47000000,
 692                  .frequency_max = 862000000,
 693                  .frequency_stepsize = 62500,
 694                  .symbol_rate_min = 870000,
 695                  .symbol_rate_max = 11700000,
 696                  .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
 697                  FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},
 698
 699         .release = stv0297_release,
 700
 701         .init = stv0297_init,
 702         .sleep = stv0297_sleep,
 703         .i2c_gate_ctrl = stv0297_i2c_gate_ctrl,
 704
 705         .set_frontend = stv0297_set_frontend,
 706         .get_frontend = stv0297_get_frontend,
 707
 708         .read_status = stv0297_read_status,
 709         .read_ber = stv0297_read_ber,
 710         .read_signal_strength = stv0297_read_signal_strength,
 711         .read_snr = stv0297_read_snr,
 712         .read_ucblocks = stv0297_read_ucblocks,
 713 };
 714
 715 MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver");
 716 MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey");
 717 MODULE_LICENSE("GPL");
 718
 719 EXPORT_SYMBOL(stv0297_attach);