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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / media / dvb / dvb-usb / af9005-fe.c
blob7b4d08b0fe0d53f33c3a5239bc0c374e539cdaab
1 /* Frontend part of the Linux driver for the Afatech 9005
2 * USB1.1 DVB-T receiver.
3 *
4 * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
5 *
6 * Thanks to Afatech who kindly provided information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * see Documentation/dvb/README.dvb-usb for more information
23 */
24 #include "af9005.h"
25 #include "af9005-script.h"
26 #include "mt2060.h"
27 #include "qt1010.h"
28 #include <asm/div64.h>
29
30 struct af9005_fe_state {
31 struct dvb_usb_device *d;
32 fe_status_t stat;
33
34 /* retraining parameters */
35 u32 original_fcw;
36 u16 original_rf_top;
37 u16 original_if_top;
38 u16 original_if_min;
39 u16 original_aci0_if_top;
40 u16 original_aci1_if_top;
41 u16 original_aci0_if_min;
42 u8 original_if_unplug_th;
43 u8 original_rf_unplug_th;
44 u8 original_dtop_if_unplug_th;
45 u8 original_dtop_rf_unplug_th;
46
47 /* statistics */
48 u32 pre_vit_error_count;
49 u32 pre_vit_bit_count;
50 u32 ber;
51 u32 post_vit_error_count;
52 u32 post_vit_bit_count;
53 u32 unc;
54 u16 abort_count;
55
56 int opened;
57 int strong;
58 unsigned long next_status_check;
59 struct dvb_frontend frontend;
60 };
61
62 static int af9005_write_word_agc(struct dvb_usb_device *d, u16 reghi,
63 u16 reglo, u8 pos, u8 len, u16 value)
64 {
65 int ret;
66 u8 temp;
67
68 if ((ret = af9005_write_ofdm_register(d, reglo, (u8) (value & 0xff))))
69 return ret;
70 temp = (u8) ((value & 0x0300) >> 8);
71 return af9005_write_register_bits(d, reghi, pos, len,
72 (u8) ((value & 0x300) >> 8));
73 }
74
75 static int af9005_read_word_agc(struct dvb_usb_device *d, u16 reghi,
76 u16 reglo, u8 pos, u8 len, u16 * value)
77 {
78 int ret;
79 u8 temp0, temp1;
80
81 if ((ret = af9005_read_ofdm_register(d, reglo, &temp0)))
82 return ret;
83 if ((ret = af9005_read_ofdm_register(d, reghi, &temp1)))
84 return ret;
85 switch (pos) {
86 case 0:
87 *value = ((u16) (temp1 & 0x03) << 8) + (u16) temp0;
88 break;
89 case 2:
90 *value = ((u16) (temp1 & 0x0C) << 6) + (u16) temp0;
91 break;
92 case 4:
93 *value = ((u16) (temp1 & 0x30) << 4) + (u16) temp0;
94 break;
95 case 6:
96 *value = ((u16) (temp1 & 0xC0) << 2) + (u16) temp0;
97 break;
98 default:
99 err("invalid pos in read word agc");
100 return -EINVAL;
101 }
102 return 0;
103
104 }
105
106 static int af9005_is_fecmon_available(struct dvb_frontend *fe, int *available)
107 {
108 struct af9005_fe_state *state = fe->demodulator_priv;
109 int ret;
110 u8 temp;
111
112 *available = false;
113
114 ret = af9005_read_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
115 fec_vtb_rsd_mon_en_pos,
116 fec_vtb_rsd_mon_en_len, &temp);
117 if (ret)
118 return ret;
119 if (temp & 1) {
120 ret =
121 af9005_read_register_bits(state->d,
122 xd_p_reg_ofsm_read_rbc_en,
123 reg_ofsm_read_rbc_en_pos,
124 reg_ofsm_read_rbc_en_len, &temp);
125 if (ret)
126 return ret;
127 if ((temp & 1) == 0)
128 *available = true;
129
130 }
131 return 0;
132 }
133
134 static int af9005_get_post_vit_err_cw_count(struct dvb_frontend *fe,
135 u32 * post_err_count,
136 u32 * post_cw_count,
137 u16 * abort_count)
138 {
139 struct af9005_fe_state *state = fe->demodulator_priv;
140 int ret;
141 u32 err_count;
142 u32 cw_count;
143 u8 temp, temp0, temp1, temp2;
144 u16 loc_abort_count;
145
146 *post_err_count = 0;
147 *post_cw_count = 0;
148
149 /* check if error bit count is ready */
150 ret =
151 af9005_read_register_bits(state->d, xd_r_fec_rsd_ber_rdy,
152 fec_rsd_ber_rdy_pos, fec_rsd_ber_rdy_len,
153 &temp);
154 if (ret)
155 return ret;
156 if (!temp) {
157 deb_info("rsd counter not ready\n");
158 return 100;
159 }
160 /* get abort count */
161 ret =
162 af9005_read_ofdm_register(state->d,
163 xd_r_fec_rsd_abort_packet_cnt_7_0,
164 &temp0);
165 if (ret)
166 return ret;
167 ret =
168 af9005_read_ofdm_register(state->d,
169 xd_r_fec_rsd_abort_packet_cnt_15_8,
170 &temp1);
171 if (ret)
172 return ret;
173 loc_abort_count = ((u16) temp1 << 8) + temp0;
174
175 /* get error count */
176 ret =
177 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_7_0,
178 &temp0);
179 if (ret)
180 return ret;
181 ret =
182 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_15_8,
183 &temp1);
184 if (ret)
185 return ret;
186 ret =
187 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_23_16,
188 &temp2);
189 if (ret)
190 return ret;
191 err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0;
192 *post_err_count = err_count - (u32) loc_abort_count *8 * 8;
193
194 /* get RSD packet number */
195 ret =
196 af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0,
197 &temp0);
198 if (ret)
199 return ret;
200 ret =
201 af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8,
202 &temp1);
203 if (ret)
204 return ret;
205 cw_count = ((u32) temp1 << 8) + temp0;
206 if (cw_count == 0) {
207 err("wrong RSD packet count");
208 return -EIO;
209 }
210 deb_info("POST abort count %d err count %d rsd packets %d\n",
211 loc_abort_count, err_count, cw_count);
212 *post_cw_count = cw_count - (u32) loc_abort_count;
213 *abort_count = loc_abort_count;
214 return 0;
215
216 }
217
218 static int af9005_get_post_vit_ber(struct dvb_frontend *fe,
219 u32 * post_err_count, u32 * post_cw_count,
220 u16 * abort_count)
221 {
222 u32 loc_cw_count = 0, loc_err_count;
223 u16 loc_abort_count = 0;
224 int ret;
225
226 ret =
227 af9005_get_post_vit_err_cw_count(fe, &loc_err_count, &loc_cw_count,
228 &loc_abort_count);
229 if (ret)
230 return ret;
231 *post_err_count = loc_err_count;
232 *post_cw_count = loc_cw_count * 204 * 8;
233 *abort_count = loc_abort_count;
234
235 return 0;
236 }
237
238 static int af9005_get_pre_vit_err_bit_count(struct dvb_frontend *fe,
239 u32 * pre_err_count,
240 u32 * pre_bit_count)
241 {
242 struct af9005_fe_state *state = fe->demodulator_priv;
243 u8 temp, temp0, temp1, temp2;
244 u32 super_frame_count, x, bits;
245 int ret;
246
247 ret =
248 af9005_read_register_bits(state->d, xd_r_fec_vtb_ber_rdy,
249 fec_vtb_ber_rdy_pos, fec_vtb_ber_rdy_len,
250 &temp);
251 if (ret)
252 return ret;
253 if (!temp) {
254 deb_info("viterbi counter not ready\n");
255 return 101; /* ERR_APO_VTB_COUNTER_NOT_READY; */
256 }
257 ret =
258 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_7_0,
259 &temp0);
260 if (ret)
261 return ret;
262 ret =
263 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_15_8,
264 &temp1);
265 if (ret)
266 return ret;
267 ret =
268 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_23_16,
269 &temp2);
270 if (ret)
271 return ret;
272 *pre_err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0;
273
274 ret =
275 af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0,
276 &temp0);
277 if (ret)
278 return ret;
279 ret =
280 af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8,
281 &temp1);
282 if (ret)
283 return ret;
284 super_frame_count = ((u32) temp1 << 8) + temp0;
285 if (super_frame_count == 0) {
286 deb_info("super frame count 0\n");
287 return 102;
288 }
289
290 /* read fft mode */
291 ret =
292 af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod,
293 reg_tpsd_txmod_pos, reg_tpsd_txmod_len,
294 &temp);
295 if (ret)
296 return ret;
297 if (temp == 0) {
298 /* 2K */
299 x = 1512;
300 } else if (temp == 1) {
301 /* 8k */
302 x = 6048;
303 } else {
304 err("Invalid fft mode");
305 return -EINVAL;
306 }
307
308 /* read constellation mode */
309 ret =
310 af9005_read_register_bits(state->d, xd_g_reg_tpsd_const,
311 reg_tpsd_const_pos, reg_tpsd_const_len,
312 &temp);
313 if (ret)
314 return ret;
315 switch (temp) {
316 case 0: /* QPSK */
317 bits = 2;
318 break;
319 case 1: /* QAM_16 */
320 bits = 4;
321 break;
322 case 2: /* QAM_64 */
323 bits = 6;
324 break;
325 default:
326 err("invalid constellation mode");
327 return -EINVAL;
328 }
329 *pre_bit_count = super_frame_count * 68 * 4 * x * bits;
330 deb_info("PRE err count %d frame count %d bit count %d\n",
331 *pre_err_count, super_frame_count, *pre_bit_count);
332 return 0;
333 }
334
335 static int af9005_reset_pre_viterbi(struct dvb_frontend *fe)
336 {
337 struct af9005_fe_state *state = fe->demodulator_priv;
338 int ret;
339
340 /* set super frame count to 1 */
341 ret =
342 af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0,
343 1 & 0xff);
344 if (ret)
345 return ret;
346 ret = af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8,
347 1 >> 8);
348 if (ret)
349 return ret;
350 /* reset pre viterbi error count */
351 ret =
352 af9005_write_register_bits(state->d, xd_p_fec_vtb_ber_rst,
353 fec_vtb_ber_rst_pos, fec_vtb_ber_rst_len,
354 1);
355
356 return ret;
357 }
358
359 static int af9005_reset_post_viterbi(struct dvb_frontend *fe)
360 {
361 struct af9005_fe_state *state = fe->demodulator_priv;
362 int ret;
363
364 /* set packet unit */
365 ret =
366 af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0,
367 10000 & 0xff);
368 if (ret)
369 return ret;
370 ret =
371 af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8,
372 10000 >> 8);
373 if (ret)
374 return ret;
375 /* reset post viterbi error count */
376 ret =
377 af9005_write_register_bits(state->d, xd_p_fec_rsd_ber_rst,
378 fec_rsd_ber_rst_pos, fec_rsd_ber_rst_len,
379 1);
380
381 return ret;
382 }
383
384 static int af9005_get_statistic(struct dvb_frontend *fe)
385 {
386 struct af9005_fe_state *state = fe->demodulator_priv;
387 int ret, fecavailable;
388 u64 numerator, denominator;
389
390 deb_info("GET STATISTIC\n");
391 ret = af9005_is_fecmon_available(fe, &fecavailable);
392 if (ret)
393 return ret;
394 if (!fecavailable) {
395 deb_info("fecmon not available\n");
396 return 0;
397 }
398
399 ret = af9005_get_pre_vit_err_bit_count(fe, &state->pre_vit_error_count,
400 &state->pre_vit_bit_count);
401 if (ret == 0) {
402 af9005_reset_pre_viterbi(fe);
403 if (state->pre_vit_bit_count > 0) {
404 /* according to v 0.0.4 of the dvb api ber should be a multiple
405 of 10E-9 so we have to multiply the error count by
406 10E9=1000000000 */
407 numerator =
408 (u64) state->pre_vit_error_count * (u64) 1000000000;
409 denominator = (u64) state->pre_vit_bit_count;
410 state->ber = do_div(numerator, denominator);
411 } else {
412 state->ber = 0xffffffff;
413 }
414 }
415
416 ret = af9005_get_post_vit_ber(fe, &state->post_vit_error_count,
417 &state->post_vit_bit_count,
418 &state->abort_count);
419 if (ret == 0) {
420 ret = af9005_reset_post_viterbi(fe);
421 state->unc += state->abort_count;
422 if (ret)
423 return ret;
424 }
425 return 0;
426 }
427
428 static int af9005_fe_refresh_state(struct dvb_frontend *fe)
429 {
430 struct af9005_fe_state *state = fe->demodulator_priv;
431 if (time_after(jiffies, state->next_status_check)) {
432 deb_info("REFRESH STATE\n");
433
434 /* statistics */
435 if (af9005_get_statistic(fe))
436 err("get_statistic_failed");
437 state->next_status_check = jiffies + 250 * HZ / 1000;
438 }
439 return 0;
440 }
441
442 static int af9005_fe_read_status(struct dvb_frontend *fe, fe_status_t * stat)
443 {
444 struct af9005_fe_state *state = fe->demodulator_priv;
445 u8 temp;
446 int ret;
447
448 if (fe->ops.tuner_ops.release == NULL)
449 return -ENODEV;
450
451 *stat = 0;
452 ret = af9005_read_register_bits(state->d, xd_p_agc_lock,
453 agc_lock_pos, agc_lock_len, &temp);
454 if (ret)
455 return ret;
456 if (temp)
457 *stat |= FE_HAS_SIGNAL;
458
459 ret = af9005_read_register_bits(state->d, xd_p_fd_tpsd_lock,
460 fd_tpsd_lock_pos, fd_tpsd_lock_len,
461 &temp);
462 if (ret)
463 return ret;
464 if (temp)
465 *stat |= FE_HAS_CARRIER;
466
467 ret = af9005_read_register_bits(state->d,
468 xd_r_mp2if_sync_byte_locked,
469 mp2if_sync_byte_locked_pos,
470 mp2if_sync_byte_locked_pos, &temp);
471 if (ret)
472 return ret;
473 if (temp)
474 *stat |= FE_HAS_SYNC | FE_HAS_VITERBI | FE_HAS_LOCK;
475 if (state->opened)
476 af9005_led_control(state->d, *stat & FE_HAS_LOCK);
477
478 ret =
479 af9005_read_register_bits(state->d, xd_p_reg_strong_sginal_detected,
480 reg_strong_sginal_detected_pos,
481 reg_strong_sginal_detected_len, &temp);
482 if (ret)
483 return ret;
484 if (temp != state->strong) {
485 deb_info("adjust for strong signal %d\n", temp);
486 state->strong = temp;
487 }
488 return 0;
489 }
490
491 static int af9005_fe_read_ber(struct dvb_frontend *fe, u32 * ber)
492 {
493 struct af9005_fe_state *state = fe->demodulator_priv;
494 if (fe->ops.tuner_ops.release == NULL)
495 return -ENODEV;
496 af9005_fe_refresh_state(fe);
497 *ber = state->ber;
498 return 0;
499 }
500
501 static int af9005_fe_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
502 {
503 struct af9005_fe_state *state = fe->demodulator_priv;
504 if (fe->ops.tuner_ops.release == NULL)
505 return -ENODEV;
506 af9005_fe_refresh_state(fe);
507 *unc = state->unc;
508 return 0;
509 }
510
511 static int af9005_fe_read_signal_strength(struct dvb_frontend *fe,
512 u16 * strength)
513 {
514 struct af9005_fe_state *state = fe->demodulator_priv;
515 int ret;
516 u8 if_gain, rf_gain;
517
518 if (fe->ops.tuner_ops.release == NULL)
519 return -ENODEV;
520 ret =
521 af9005_read_ofdm_register(state->d, xd_r_reg_aagc_rf_gain,
522 &rf_gain);
523 if (ret)
524 return ret;
525 ret =
526 af9005_read_ofdm_register(state->d, xd_r_reg_aagc_if_gain,
527 &if_gain);
528 if (ret)
529 return ret;
530 /* this value has no real meaning, but i don't have the tables that relate
531 the rf and if gain with the dbm, so I just scale the value */
532 *strength = (512 - rf_gain - if_gain) << 7;
533 return 0;
534 }
535
536 static int af9005_fe_read_snr(struct dvb_frontend *fe, u16 * snr)
537 {
538 /* the snr can be derived from the ber and the constellation
539 but I don't think this kind of complex calculations belong
540 in the driver. I may be wrong.... */
541 return -ENOSYS;
542 }
543
544 static int af9005_fe_program_cfoe(struct dvb_usb_device *d, fe_bandwidth_t bw)
545 {
546 u8 temp0, temp1, temp2, temp3, buf[4];
547 int ret;
548 u32 NS_coeff1_2048Nu;
549 u32 NS_coeff1_8191Nu;
550 u32 NS_coeff1_8192Nu;
551 u32 NS_coeff1_8193Nu;
552 u32 NS_coeff2_2k;
553 u32 NS_coeff2_8k;
554
555 switch (bw) {
556 case BANDWIDTH_6_MHZ:
557 NS_coeff1_2048Nu = 0x2ADB6DC;
558 NS_coeff1_8191Nu = 0xAB7313;
559 NS_coeff1_8192Nu = 0xAB6DB7;
560 NS_coeff1_8193Nu = 0xAB685C;
561 NS_coeff2_2k = 0x156DB6E;
562 NS_coeff2_8k = 0x55B6DC;
563 break;
564
565 case BANDWIDTH_7_MHZ:
566 NS_coeff1_2048Nu = 0x3200001;
567 NS_coeff1_8191Nu = 0xC80640;
568 NS_coeff1_8192Nu = 0xC80000;
569 NS_coeff1_8193Nu = 0xC7F9C0;
570 NS_coeff2_2k = 0x1900000;
571 NS_coeff2_8k = 0x640000;
572 break;
573
574 case BANDWIDTH_8_MHZ:
575 NS_coeff1_2048Nu = 0x3924926;
576 NS_coeff1_8191Nu = 0xE4996E;
577 NS_coeff1_8192Nu = 0xE49249;
578 NS_coeff1_8193Nu = 0xE48B25;
579 NS_coeff2_2k = 0x1C92493;
580 NS_coeff2_8k = 0x724925;
581 break;
582 default:
583 err("Invalid bandwith %d.", bw);
584 return -EINVAL;
585 }
586
587 /*
588 * write NS_coeff1_2048Nu
589 */
590
591 temp0 = (u8) (NS_coeff1_2048Nu & 0x000000FF);
592 temp1 = (u8) ((NS_coeff1_2048Nu & 0x0000FF00) >> 8);
593 temp2 = (u8) ((NS_coeff1_2048Nu & 0x00FF0000) >> 16);
594 temp3 = (u8) ((NS_coeff1_2048Nu & 0x03000000) >> 24);
595
596 /* big endian to make 8051 happy */
597 buf[0] = temp3;
598 buf[1] = temp2;
599 buf[2] = temp1;
600 buf[3] = temp0;
601
602 /* cfoe_NS_2k_coeff1_25_24 */
603 ret = af9005_write_ofdm_register(d, 0xAE00, buf[0]);
604 if (ret)
605 return ret;
606
607 /* cfoe_NS_2k_coeff1_23_16 */
608 ret = af9005_write_ofdm_register(d, 0xAE01, buf[1]);
609 if (ret)
610 return ret;
611
612 /* cfoe_NS_2k_coeff1_15_8 */
613 ret = af9005_write_ofdm_register(d, 0xAE02, buf[2]);
614 if (ret)
615 return ret;
616
617 /* cfoe_NS_2k_coeff1_7_0 */
618 ret = af9005_write_ofdm_register(d, 0xAE03, buf[3]);
619 if (ret)
620 return ret;
621
622 /*
623 * write NS_coeff2_2k
624 */
625
626 temp0 = (u8) ((NS_coeff2_2k & 0x0000003F));
627 temp1 = (u8) ((NS_coeff2_2k & 0x00003FC0) >> 6);
628 temp2 = (u8) ((NS_coeff2_2k & 0x003FC000) >> 14);
629 temp3 = (u8) ((NS_coeff2_2k & 0x01C00000) >> 22);
630
631 /* big endian to make 8051 happy */
632 buf[0] = temp3;
633 buf[1] = temp2;
634 buf[2] = temp1;
635 buf[3] = temp0;
636
637 ret = af9005_write_ofdm_register(d, 0xAE04, buf[0]);
638 if (ret)
639 return ret;
640
641 ret = af9005_write_ofdm_register(d, 0xAE05, buf[1]);
642 if (ret)
643 return ret;
644
645 ret = af9005_write_ofdm_register(d, 0xAE06, buf[2]);
646 if (ret)
647 return ret;
648
649 ret = af9005_write_ofdm_register(d, 0xAE07, buf[3]);
650 if (ret)
651 return ret;
652
653 /*
654 * write NS_coeff1_8191Nu
655 */
656
657 temp0 = (u8) ((NS_coeff1_8191Nu & 0x000000FF));
658 temp1 = (u8) ((NS_coeff1_8191Nu & 0x0000FF00) >> 8);
659 temp2 = (u8) ((NS_coeff1_8191Nu & 0x00FFC000) >> 16);
660 temp3 = (u8) ((NS_coeff1_8191Nu & 0x03000000) >> 24);
661
662 /* big endian to make 8051 happy */
663 buf[0] = temp3;
664 buf[1] = temp2;
665 buf[2] = temp1;
666 buf[3] = temp0;
667
668 ret = af9005_write_ofdm_register(d, 0xAE08, buf[0]);
669 if (ret)
670 return ret;
671
672 ret = af9005_write_ofdm_register(d, 0xAE09, buf[1]);
673 if (ret)
674 return ret;
675
676 ret = af9005_write_ofdm_register(d, 0xAE0A, buf[2]);
677 if (ret)
678 return ret;
679
680 ret = af9005_write_ofdm_register(d, 0xAE0B, buf[3]);
681 if (ret)
682 return ret;
683
684 /*
685 * write NS_coeff1_8192Nu
686 */
687
688 temp0 = (u8) (NS_coeff1_8192Nu & 0x000000FF);
689 temp1 = (u8) ((NS_coeff1_8192Nu & 0x0000FF00) >> 8);
690 temp2 = (u8) ((NS_coeff1_8192Nu & 0x00FFC000) >> 16);
691 temp3 = (u8) ((NS_coeff1_8192Nu & 0x03000000) >> 24);
692
693 /* big endian to make 8051 happy */
694 buf[0] = temp3;
695 buf[1] = temp2;
696 buf[2] = temp1;
697 buf[3] = temp0;
698
699 ret = af9005_write_ofdm_register(d, 0xAE0C, buf[0]);
700 if (ret)
701 return ret;
702
703 ret = af9005_write_ofdm_register(d, 0xAE0D, buf[1]);
704 if (ret)
705 return ret;
706
707 ret = af9005_write_ofdm_register(d, 0xAE0E, buf[2]);
708 if (ret)
709 return ret;
710
711 ret = af9005_write_ofdm_register(d, 0xAE0F, buf[3]);
712 if (ret)
713 return ret;
714
715 /*
716 * write NS_coeff1_8193Nu
717 */
718
719 temp0 = (u8) ((NS_coeff1_8193Nu & 0x000000FF));
720 temp1 = (u8) ((NS_coeff1_8193Nu & 0x0000FF00) >> 8);
721 temp2 = (u8) ((NS_coeff1_8193Nu & 0x00FFC000) >> 16);
722 temp3 = (u8) ((NS_coeff1_8193Nu & 0x03000000) >> 24);
723
724 /* big endian to make 8051 happy */
725 buf[0] = temp3;
726 buf[1] = temp2;
727 buf[2] = temp1;
728 buf[3] = temp0;
729
730 ret = af9005_write_ofdm_register(d, 0xAE10, buf[0]);
731 if (ret)
732 return ret;
733
734 ret = af9005_write_ofdm_register(d, 0xAE11, buf[1]);
735 if (ret)
736 return ret;
737
738 ret = af9005_write_ofdm_register(d, 0xAE12, buf[2]);
739 if (ret)
740 return ret;
741
742 ret = af9005_write_ofdm_register(d, 0xAE13, buf[3]);
743 if (ret)
744 return ret;
745
746 /*
747 * write NS_coeff2_8k
748 */
749
750 temp0 = (u8) ((NS_coeff2_8k & 0x0000003F));
751 temp1 = (u8) ((NS_coeff2_8k & 0x00003FC0) >> 6);
752 temp2 = (u8) ((NS_coeff2_8k & 0x003FC000) >> 14);
753 temp3 = (u8) ((NS_coeff2_8k & 0x01C00000) >> 22);
754
755 /* big endian to make 8051 happy */
756 buf[0] = temp3;
757 buf[1] = temp2;
758 buf[2] = temp1;
759 buf[3] = temp0;
760
761 ret = af9005_write_ofdm_register(d, 0xAE14, buf[0]);
762 if (ret)
763 return ret;
764
765 ret = af9005_write_ofdm_register(d, 0xAE15, buf[1]);
766 if (ret)
767 return ret;
768
769 ret = af9005_write_ofdm_register(d, 0xAE16, buf[2]);
770 if (ret)
771 return ret;
772
773 ret = af9005_write_ofdm_register(d, 0xAE17, buf[3]);
774 return ret;
775
776 }
777
778 static int af9005_fe_select_bw(struct dvb_usb_device *d, fe_bandwidth_t bw)
779 {
780 u8 temp;
781 switch (bw) {
782 case BANDWIDTH_6_MHZ:
783 temp = 0;
784 break;
785 case BANDWIDTH_7_MHZ:
786 temp = 1;
787 break;
788 case BANDWIDTH_8_MHZ:
789 temp = 2;
790 break;
791 default:
792 err("Invalid bandwith %d.", bw);
793 return -EINVAL;
794 }
795 return af9005_write_register_bits(d, xd_g_reg_bw, reg_bw_pos,
796 reg_bw_len, temp);
797 }
798
799 static int af9005_fe_power(struct dvb_frontend *fe, int on)
800 {
801 struct af9005_fe_state *state = fe->demodulator_priv;
802 u8 temp = on;
803 int ret;
804 deb_info("power %s tuner\n", on ? "on" : "off");
805 ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
806 return ret;
807 }
808
809 static struct mt2060_config af9005_mt2060_config = {
810 0xC0
811 };
812
813 static struct qt1010_config af9005_qt1010_config = {
814 0xC4
815 };
816
817 static int af9005_fe_init(struct dvb_frontend *fe)
818 {
819 struct af9005_fe_state *state = fe->demodulator_priv;
820 struct dvb_usb_adapter *adap = fe->dvb->priv;
821 int ret, i, scriptlen;
822 u8 temp, temp0 = 0, temp1 = 0, temp2 = 0;
823 u8 buf[2];
824 u16 if1;
825
826 deb_info("in af9005_fe_init\n");
827
828 /* reset */
829 deb_info("reset\n");
830 if ((ret =
831 af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst_en,
832 4, 1, 0x01)))
833 return ret;
834 if ((ret = af9005_write_ofdm_register(state->d, APO_REG_RESET, 0)))
835 return ret;
836 /* clear ofdm reset */
837 deb_info("clear ofdm reset\n");
838 for (i = 0; i < 150; i++) {
839 if ((ret =
840 af9005_read_ofdm_register(state->d,
841 xd_I2C_reg_ofdm_rst, &temp)))
842 return ret;
843 if (temp & (regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos))
844 break;
845 msleep(10);
846 }
847 if (i == 150)
848 return -ETIMEDOUT;
849
850 ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa9);
851 if (ret)
852 return ret;
853 ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x07);
854 if (ret)
855 return ret;
856 temp = 0x01;
857 ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
858 if (ret)
859 return ret;
860 ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x00);
861 if (ret)
862 return ret;
863 ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa1);
864 if (ret)
865 return ret;
866
867 temp = regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos;
868 if ((ret =
869 af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
870 reg_ofdm_rst_pos, reg_ofdm_rst_len, 1)))
871 return ret;
872 ret = af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
873 reg_ofdm_rst_pos, reg_ofdm_rst_len, 0);
874
875 if (ret)
876 return ret;
877 /* don't know what register aefc is, but this is what the windows driver does */
878 ret = af9005_write_ofdm_register(state->d, 0xaefc, 0);
879 if (ret)
880 return ret;
881
882 /* set stand alone chip */
883 deb_info("set stand alone chip\n");
884 if ((ret =
885 af9005_write_register_bits(state->d, xd_p_reg_dca_stand_alone,
886 reg_dca_stand_alone_pos,
887 reg_dca_stand_alone_len, 1)))
888 return ret;
889
890 /* set dca upper & lower chip */
891 deb_info("set dca upper & lower chip\n");
892 if ((ret =
893 af9005_write_register_bits(state->d, xd_p_reg_dca_upper_chip,
894 reg_dca_upper_chip_pos,
895 reg_dca_upper_chip_len, 0)))
896 return ret;
897 if ((ret =
898 af9005_write_register_bits(state->d, xd_p_reg_dca_lower_chip,
899 reg_dca_lower_chip_pos,
900 reg_dca_lower_chip_len, 0)))
901 return ret;
902
903 /* set 2wire master clock to 0x14 (for 60KHz) */
904 deb_info("set 2wire master clock to 0x14 (for 60KHz)\n");
905 if ((ret =
906 af9005_write_ofdm_register(state->d, xd_I2C_i2c_m_period, 0x14)))
907 return ret;
908
909 /* clear dca enable chip */
910 deb_info("clear dca enable chip\n");
911 if ((ret =
912 af9005_write_register_bits(state->d, xd_p_reg_dca_en,
913 reg_dca_en_pos, reg_dca_en_len, 0)))
914 return ret;
915 ret = af9005_write_ofdm_register(state->d, 0xa16c, 1);
916 if (ret)
917 return ret;
918 ret = af9005_write_ofdm_register(state->d, 0xa3c1, 0);
919 if (ret)
920 return ret;
921
922 /* init other parameters: program cfoe and select bandwith */
923 deb_info("program cfoe\n");
924 if ((ret = af9005_fe_program_cfoe(state->d, BANDWIDTH_6_MHZ)))
925 return ret;
926 /* set read-update bit for constellation */
927 deb_info("set read-update bit for constellation\n");
928 if ((ret =
929 af9005_write_register_bits(state->d, xd_p_reg_feq_read_update,
930 reg_feq_read_update_pos,
931 reg_feq_read_update_len, 1)))
932 return ret;
933
934 /* sample code has a set MPEG TS code here
935 but sniffing reveals that it doesn't do it */
936
937 /* set read-update bit to 1 for DCA constellation */
938 deb_info("set read-update bit 1 for DCA constellation\n");
939 if ((ret =
940 af9005_write_register_bits(state->d, xd_p_reg_dca_read_update,
941 reg_dca_read_update_pos,
942 reg_dca_read_update_len, 1)))
943 return ret;
944
945 /* enable fec monitor */
946 deb_info("enable fec monitor\n");
947 if ((ret =
948 af9005_write_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
949 fec_vtb_rsd_mon_en_pos,
950 fec_vtb_rsd_mon_en_len, 1)))
951 return ret;
952
953 ret = af9005_write_ofdm_register(state->d, 0xa601, 0);
954
955 /* set api_retrain_never_freeze */
956 deb_info("set api_retrain_never_freeze\n");
957 if ((ret = af9005_write_ofdm_register(state->d, 0xaefb, 0x01)))
958 return ret;
959
960 /* load init script */
961 deb_info("load init script\n");
962 scriptlen = sizeof(script) / sizeof(RegDesc);
963 for (i = 0; i < scriptlen; i++) {
964 if ((ret =
965 af9005_write_register_bits(state->d, script[i].reg,
966 script[i].pos,
967 script[i].len, script[i].val)))
968 return ret;
969 /* save 3 bytes of original fcw */
970 if (script[i].reg == 0xae18)
971 temp2 = script[i].val;
972 if (script[i].reg == 0xae19)
973 temp1 = script[i].val;
974 if (script[i].reg == 0xae1a)
975 temp0 = script[i].val;
976
977 /* save original unplug threshold */
978 if (script[i].reg == xd_p_reg_unplug_th)
979 state->original_if_unplug_th = script[i].val;
980 if (script[i].reg == xd_p_reg_unplug_rf_gain_th)
981 state->original_rf_unplug_th = script[i].val;
982 if (script[i].reg == xd_p_reg_unplug_dtop_if_gain_th)
983 state->original_dtop_if_unplug_th = script[i].val;
984 if (script[i].reg == xd_p_reg_unplug_dtop_rf_gain_th)
985 state->original_dtop_rf_unplug_th = script[i].val;
986
987 }
988 state->original_fcw =
989 ((u32) temp2 << 16) + ((u32) temp1 << 8) + (u32) temp0;
990
991
992 /* save original TOPs */
993 deb_info("save original TOPs\n");
994
995 /* RF TOP */
996 ret =
997 af9005_read_word_agc(state->d,
998 xd_p_reg_aagc_rf_top_numerator_9_8,
999 xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
1000 &state->original_rf_top);
1001 if (ret)
1002 return ret;
1003
1004 /* IF TOP */
1005 ret =
1006 af9005_read_word_agc(state->d,
1007 xd_p_reg_aagc_if_top_numerator_9_8,
1008 xd_p_reg_aagc_if_top_numerator_7_0, 0, 2,
1009 &state->original_if_top);
1010 if (ret)
1011 return ret;
1012
1013 /* ACI 0 IF TOP */
1014 ret =
1015 af9005_read_word_agc(state->d, 0xA60E, 0xA60A, 4, 2,
1016 &state->original_aci0_if_top);
1017 if (ret)
1018 return ret;
1019
1020 /* ACI 1 IF TOP */
1021 ret =
1022 af9005_read_word_agc(state->d, 0xA60E, 0xA60B, 6, 2,
1023 &state->original_aci1_if_top);
1024 if (ret)
1025 return ret;
1026
1027 /* attach tuner and init */
1028 if (fe->ops.tuner_ops.release == NULL) {
1029 /* read tuner and board id from eeprom */
1030 ret = af9005_read_eeprom(adap->dev, 0xc6, buf, 2);
1031 if (ret) {
1032 err("Impossible to read EEPROM\n");
1033 return ret;
1034 }
1035 deb_info("Tuner id %d, board id %d\n", buf[0], buf[1]);
1036 switch (buf[0]) {
1037 case 2: /* MT2060 */
1038 /* read if1 from eeprom */
1039 ret = af9005_read_eeprom(adap->dev, 0xc8, buf, 2);
1040 if (ret) {
1041 err("Impossible to read EEPROM\n");
1042 return ret;
1043 }
1044 if1 = (u16) (buf[0] << 8) + buf[1];
1045 if (dvb_attach(mt2060_attach, fe, &adap->dev->i2c_adap,
1046 &af9005_mt2060_config, if1) == NULL) {
1047 deb_info("MT2060 attach failed\n");
1048 return -ENODEV;
1049 }
1050 break;
1051 case 3: /* QT1010 */
1052 case 9: /* QT1010B */
1053 if (dvb_attach(qt1010_attach, fe, &adap->dev->i2c_adap,
1054 &af9005_qt1010_config) ==NULL) {
1055 deb_info("QT1010 attach failed\n");
1056 return -ENODEV;
1057 }
1058 break;
1059 default:
1060 err("Unsupported tuner type %d", buf[0]);
1061 return -ENODEV;
1062 }
1063 ret = fe->ops.tuner_ops.init(fe);
1064 if (ret)
1065 return ret;
1066 }
1067
1068 deb_info("profit!\n");
1069 return 0;
1070 }
1071
1072 static int af9005_fe_sleep(struct dvb_frontend *fe)
1073 {
1074 return af9005_fe_power(fe, 0);
1075 }
1076
1077 static int af9005_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
1078 {
1079 struct af9005_fe_state *state = fe->demodulator_priv;
1080
1081 if (acquire) {
1082 state->opened++;
1083 } else {
1084
1085 state->opened--;
1086 if (!state->opened)
1087 af9005_led_control(state->d, 0);
1088 }
1089 return 0;
1090 }
1091
1092 static int af9005_fe_set_frontend(struct dvb_frontend *fe,
1093 struct dvb_frontend_parameters *fep)
1094 {
1095 struct af9005_fe_state *state = fe->demodulator_priv;
1096 int ret;
1097 u8 temp, temp0, temp1, temp2;
1098
1099 deb_info("af9005_fe_set_frontend freq %d bw %d\n", fep->frequency,
1100 fep->u.ofdm.bandwidth);
1101 if (fe->ops.tuner_ops.release == NULL) {
1102 err("Tuner not attached");
1103 return -ENODEV;
1104 }
1105
1106 deb_info("turn off led\n");
1107 /* not in the log */
1108 ret = af9005_led_control(state->d, 0);
1109 if (ret)
1110 return ret;
1111 /* not sure about the bits */
1112 ret = af9005_write_register_bits(state->d, XD_MP2IF_MISC, 2, 1, 0);
1113 if (ret)
1114 return ret;
1115
1116 /* set FCW to default value */
1117 deb_info("set FCW to default value\n");
1118 temp0 = (u8) (state->original_fcw & 0x000000ff);
1119 temp1 = (u8) ((state->original_fcw & 0x0000ff00) >> 8);
1120 temp2 = (u8) ((state->original_fcw & 0x00ff0000) >> 16);
1121 ret = af9005_write_ofdm_register(state->d, 0xae1a, temp0);
1122 if (ret)
1123 return ret;
1124 ret = af9005_write_ofdm_register(state->d, 0xae19, temp1);
1125 if (ret)
1126 return ret;
1127 ret = af9005_write_ofdm_register(state->d, 0xae18, temp2);
1128 if (ret)
1129 return ret;
1130
1131 /* restore original TOPs */
1132 deb_info("restore original TOPs\n");
1133 ret =
1134 af9005_write_word_agc(state->d,
1135 xd_p_reg_aagc_rf_top_numerator_9_8,
1136 xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
1137 state->original_rf_top);
1138 if (ret)
1139 return ret;
1140 ret =
1141 af9005_write_word_agc(state->d,
1142 xd_p_reg_aagc_if_top_numerator_9_8,
1143 xd_p_reg_aagc_if_top_numerator_7_0, 0, 2,
1144 state->original_if_top);
1145 if (ret)
1146 return ret;
1147 ret =
1148 af9005_write_word_agc(state->d, 0xA60E, 0xA60A, 4, 2,
1149 state->original_aci0_if_top);
1150 if (ret)
1151 return ret;
1152 ret =
1153 af9005_write_word_agc(state->d, 0xA60E, 0xA60B, 6, 2,
1154 state->original_aci1_if_top);
1155 if (ret)
1156 return ret;
1157
1158 /* select bandwith */
1159 deb_info("select bandwidth");
1160 ret = af9005_fe_select_bw(state->d, fep->u.ofdm.bandwidth);
1161 if (ret)
1162 return ret;
1163 ret = af9005_fe_program_cfoe(state->d, fep->u.ofdm.bandwidth);
1164 if (ret)
1165 return ret;
1166
1167 /* clear easy mode flag */
1168 deb_info("clear easy mode flag\n");
1169 ret = af9005_write_ofdm_register(state->d, 0xaefd, 0);
1170 if (ret)
1171 return ret;
1172
1173 /* set unplug threshold to original value */
1174 deb_info("set unplug threshold to original value\n");
1175 ret =
1176 af9005_write_ofdm_register(state->d, xd_p_reg_unplug_th,
1177 state->original_if_unplug_th);
1178 if (ret)
1179 return ret;
1180 /* set tuner */
1181 deb_info("set tuner\n");
1182 ret = fe->ops.tuner_ops.set_params(fe, fep);
1183 if (ret)
1184 return ret;
1185
1186 /* trigger ofsm */
1187 deb_info("trigger ofsm\n");
1188 temp = 0;
1189 ret = af9005_write_tuner_registers(state->d, 0xffff, &temp, 1);
1190 if (ret)
1191 return ret;
1192
1193 /* clear retrain and freeze flag */
1194 deb_info("clear retrain and freeze flag\n");
1195 ret =
1196 af9005_write_register_bits(state->d,
1197 xd_p_reg_api_retrain_request,
1198 reg_api_retrain_request_pos, 2, 0);
1199 if (ret)
1200 return ret;
1201
1202 /* reset pre viterbi and post viterbi registers and statistics */
1203 af9005_reset_pre_viterbi(fe);
1204 af9005_reset_post_viterbi(fe);
1205 state->pre_vit_error_count = 0;
1206 state->pre_vit_bit_count = 0;
1207 state->ber = 0;
1208 state->post_vit_error_count = 0;
1209 /* state->unc = 0; commented out since it should be ever increasing */
1210 state->abort_count = 0;
1211
1212 state->next_status_check = jiffies;
1213 state->strong = -1;
1214
1215 return 0;
1216 }
1217
1218 static int af9005_fe_get_frontend(struct dvb_frontend *fe,
1219 struct dvb_frontend_parameters *fep)
1220 {
1221 struct af9005_fe_state *state = fe->demodulator_priv;
1222 int ret;
1223 u8 temp;
1224
1225 /* mode */
1226 ret =
1227 af9005_read_register_bits(state->d, xd_g_reg_tpsd_const,
1228 reg_tpsd_const_pos, reg_tpsd_const_len,
1229 &temp);
1230 if (ret)
1231 return ret;
1232 deb_info("===== fe_get_frontend ==============\n");
1233 deb_info("CONSTELLATION ");
1234 switch (temp) {
1235 case 0:
1236 fep->u.ofdm.constellation = QPSK;
1237 deb_info("QPSK\n");
1238 break;
1239 case 1:
1240 fep->u.ofdm.constellation = QAM_16;
1241 deb_info("QAM_16\n");
1242 break;
1243 case 2:
1244 fep->u.ofdm.constellation = QAM_64;
1245 deb_info("QAM_64\n");
1246 break;
1247 }
1248
1249 /* tps hierarchy and alpha value */
1250 ret =
1251 af9005_read_register_bits(state->d, xd_g_reg_tpsd_hier,
1252 reg_tpsd_hier_pos, reg_tpsd_hier_len,
1253 &temp);
1254 if (ret)
1255 return ret;
1256 deb_info("HIERARCHY ");
1257 switch (temp) {
1258 case 0:
1259 fep->u.ofdm.hierarchy_information = HIERARCHY_NONE;
1260 deb_info("NONE\n");
1261 break;
1262 case 1:
1263 fep->u.ofdm.hierarchy_information = HIERARCHY_1;
1264 deb_info("1\n");
1265 break;
1266 case 2:
1267 fep->u.ofdm.hierarchy_information = HIERARCHY_2;
1268 deb_info("2\n");
1269 break;
1270 case 3:
1271 fep->u.ofdm.hierarchy_information = HIERARCHY_4;
1272 deb_info("4\n");
1273 break;
1274 }
1275
1276 /* high/low priority */
1277 ret =
1278 af9005_read_register_bits(state->d, xd_g_reg_dec_pri,
1279 reg_dec_pri_pos, reg_dec_pri_len, &temp);
1280 if (ret)
1281 return ret;
1282 /* if temp is set = high priority */
1283 deb_info("PRIORITY %s\n", temp ? "high" : "low");
1284
1285 /* high coderate */
1286 ret =
1287 af9005_read_register_bits(state->d, xd_g_reg_tpsd_hpcr,
1288 reg_tpsd_hpcr_pos, reg_tpsd_hpcr_len,
1289 &temp);
1290 if (ret)
1291 return ret;
1292 deb_info("CODERATE HP ");
1293 switch (temp) {
1294 case 0:
1295 fep->u.ofdm.code_rate_HP = FEC_1_2;
1296 deb_info("FEC_1_2\n");
1297 break;
1298 case 1:
1299 fep->u.ofdm.code_rate_HP = FEC_2_3;
1300 deb_info("FEC_2_3\n");
1301 break;
1302 case 2:
1303 fep->u.ofdm.code_rate_HP = FEC_3_4;
1304 deb_info("FEC_3_4\n");
1305 break;
1306 case 3:
1307 fep->u.ofdm.code_rate_HP = FEC_5_6;
1308 deb_info("FEC_5_6\n");
1309 break;
1310 case 4:
1311 fep->u.ofdm.code_rate_HP = FEC_7_8;
1312 deb_info("FEC_7_8\n");
1313 break;
1314 }
1315
1316 /* low coderate */
1317 ret =
1318 af9005_read_register_bits(state->d, xd_g_reg_tpsd_lpcr,
1319 reg_tpsd_lpcr_pos, reg_tpsd_lpcr_len,
1320 &temp);
1321 if (ret)
1322 return ret;
1323 deb_info("CODERATE LP ");
1324 switch (temp) {
1325 case 0:
1326 fep->u.ofdm.code_rate_LP = FEC_1_2;
1327 deb_info("FEC_1_2\n");
1328 break;
1329 case 1:
1330 fep->u.ofdm.code_rate_LP = FEC_2_3;
1331 deb_info("FEC_2_3\n");
1332 break;
1333 case 2:
1334 fep->u.ofdm.code_rate_LP = FEC_3_4;
1335 deb_info("FEC_3_4\n");
1336 break;
1337 case 3:
1338 fep->u.ofdm.code_rate_LP = FEC_5_6;
1339 deb_info("FEC_5_6\n");
1340 break;
1341 case 4:
1342 fep->u.ofdm.code_rate_LP = FEC_7_8;
1343 deb_info("FEC_7_8\n");
1344 break;
1345 }
1346
1347 /* guard interval */
1348 ret =
1349 af9005_read_register_bits(state->d, xd_g_reg_tpsd_gi,
1350 reg_tpsd_gi_pos, reg_tpsd_gi_len, &temp);
1351 if (ret)
1352 return ret;
1353 deb_info("GUARD INTERVAL ");
1354 switch (temp) {
1355 case 0:
1356 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
1357 deb_info("1_32\n");
1358 break;
1359 case 1:
1360 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
1361 deb_info("1_16\n");
1362 break;
1363 case 2:
1364 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
1365 deb_info("1_8\n");
1366 break;
1367 case 3:
1368 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
1369 deb_info("1_4\n");
1370 break;
1371 }
1372
1373 /* fft */
1374 ret =
1375 af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod,
1376 reg_tpsd_txmod_pos, reg_tpsd_txmod_len,
1377 &temp);
1378 if (ret)
1379 return ret;
1380 deb_info("TRANSMISSION MODE ");
1381 switch (temp) {
1382 case 0:
1383 fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
1384 deb_info("2K\n");
1385 break;
1386 case 1:
1387 fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
1388 deb_info("8K\n");
1389 break;
1390 }
1391
1392 /* bandwidth */
1393 ret =
1394 af9005_read_register_bits(state->d, xd_g_reg_bw, reg_bw_pos,
1395 reg_bw_len, &temp);
1396 deb_info("BANDWIDTH ");
1397 switch (temp) {
1398 case 0:
1399 fep->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
1400 deb_info("6\n");
1401 break;
1402 case 1:
1403 fep->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
1404 deb_info("7\n");
1405 break;
1406 case 2:
1407 fep->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
1408 deb_info("8\n");
1409 break;
1410 }
1411 return 0;
1412 }
1413
1414 static void af9005_fe_release(struct dvb_frontend *fe)
1415 {
1416 struct af9005_fe_state *state =
1417 (struct af9005_fe_state *)fe->demodulator_priv;
1418 kfree(state);
1419 }
1420
1421 static struct dvb_frontend_ops af9005_fe_ops;
1422
1423 struct dvb_frontend *af9005_fe_attach(struct dvb_usb_device *d)
1424 {
1425 struct af9005_fe_state *state = NULL;
1426
1427 /* allocate memory for the internal state */
1428 state = kzalloc(sizeof(struct af9005_fe_state), GFP_KERNEL);
1429 if (state == NULL)
1430 goto error;
1431
1432 deb_info("attaching frontend af9005\n");
1433
1434 state->d = d;
1435 state->opened = 0;
1436
1437 memcpy(&state->frontend.ops, &af9005_fe_ops,
1438 sizeof(struct dvb_frontend_ops));
1439 state->frontend.demodulator_priv = state;
1440
1441 return &state->frontend;
1442 error:
1443 return NULL;
1444 }
1445
1446 static struct dvb_frontend_ops af9005_fe_ops = {
1447 .info = {
1448 .name = "AF9005 USB DVB-T",
1449 .type = FE_OFDM,
1450 .frequency_min = 44250000,
1451 .frequency_max = 867250000,
1452 .frequency_stepsize = 250000,
1453 .caps = FE_CAN_INVERSION_AUTO |
1454 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1455 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1456 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
1457 FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
1458 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER |
1459 FE_CAN_HIERARCHY_AUTO,
1460 },
1461
1462 .release = af9005_fe_release,
1463
1464 .init = af9005_fe_init,
1465 .sleep = af9005_fe_sleep,
1466 .ts_bus_ctrl = af9005_ts_bus_ctrl,
1467
1468 .set_frontend = af9005_fe_set_frontend,
1469 .get_frontend = af9005_fe_get_frontend,
1470
1471 .read_status = af9005_fe_read_status,
1472 .read_ber = af9005_fe_read_ber,
1473 .read_signal_strength = af9005_fe_read_signal_strength,
1474 .read_snr = af9005_fe_read_snr,
1475 .read_ucblocks = af9005_fe_read_unc_blocks,
1476 };
Tomato firmware and modifications.