release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/infiniband/hw/qib/qib_common.h

   1 /*
   2  * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
   3  * All rights reserved.
   4  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #ifndef _QIB_COMMON_H
  36 #define _QIB_COMMON_H
  37
  38 /*
  39  * This file contains defines, structures, etc. that are used
  40  * to communicate between kernel and user code.
  41  */
  42
  43 /* This is the IEEE-assigned OUI for QLogic Inc. QLogic_IB */
  44 #define QIB_SRC_OUI_1 0x00
  45 #define QIB_SRC_OUI_2 0x11
  46 #define QIB_SRC_OUI_3 0x75
  47
  48 /* version of protocol header (known to chip also). In the long run,
  49  * we should be able to generate and accept a range of version numbers;
  50  * for now we only accept one, and it's compiled in.
  51  */
  52 #define IPS_PROTO_VERSION 2
  53
  54 /*
  55  * These are compile time constants that you may want to enable or disable
  56  * if you are trying to debug problems with code or performance.
  57  * QIB_VERBOSE_TRACING define as 1 if you want additional tracing in
  58  * fastpath code
  59  * QIB_TRACE_REGWRITES define as 1 if you want register writes to be
  60  * traced in faspath code
  61  * _QIB_TRACING define as 0 if you want to remove all tracing in a
  62  * compilation unit
  63  */
  64
  65 /*
  66  * The value in the BTH QP field that QLogic_IB uses to differentiate
  67  * an qlogic_ib protocol IB packet vs standard IB transport
  68  * This it needs to be even (0x656b78), because the LSB is sometimes
  69  * used for the MSB of context. The change may cause a problem
  70  * interoperating with older software.
  71  */
  72 #define QIB_KD_QP 0x656b78
  73
  74 /*
  75  * These are the status bits readable (in ascii form, 64bit value)
  76  * from the "status" sysfs file.  For binary compatibility, values
  77  * must remain as is; removed states can be reused for different
  78  * purposes.
  79  */
  80 #define QIB_STATUS_INITTED       0x1    /* basic initialization done */
  81 /* Chip has been found and initted */
  82 #define QIB_STATUS_CHIP_PRESENT 0x20
  83 /* IB link is at ACTIVE, usable for data traffic */
  84 #define QIB_STATUS_IB_READY     0x40
  85 /* link is configured, LID, MTU, etc. have been set */
  86 #define QIB_STATUS_IB_CONF      0x80
  87 /* A Fatal hardware error has occurred. */
  88 #define QIB_STATUS_HWERROR     0x200
  89
  90 /*
  91  * The list of usermode accessible registers.  Also see Reg_* later in file.
  92  */
  93 enum qib_ureg {
  94         /* (RO)  DMA RcvHdr to be used next. */
  95         ur_rcvhdrtail = 0,
  96         /* (RW)  RcvHdr entry to be processed next by host. */
  97         ur_rcvhdrhead = 1,
  98         /* (RO)  Index of next Eager index to use. */
  99         ur_rcvegrindextail = 2,
 100         /* (RW)  Eager TID to be processed next */
 101         ur_rcvegrindexhead = 3,
 102         /* For internal use only; max register number. */
 103         _QIB_UregMax
 104 };
 105
 106 /* bit values for spi_runtime_flags */
 107 #define QIB_RUNTIME_PCIE                0x0002
 108 #define QIB_RUNTIME_FORCE_WC_ORDER      0x0004
 109 #define QIB_RUNTIME_RCVHDR_COPY         0x0008
 110 #define QIB_RUNTIME_MASTER              0x0010
 111 #define QIB_RUNTIME_RCHK                0x0020
 112 #define QIB_RUNTIME_NODMA_RTAIL         0x0080
 113 #define QIB_RUNTIME_SPECIAL_TRIGGER     0x0100
 114 #define QIB_RUNTIME_SDMA                0x0200
 115 #define QIB_RUNTIME_FORCE_PIOAVAIL      0x0400
 116 #define QIB_RUNTIME_PIO_REGSWAPPED      0x0800
 117 #define QIB_RUNTIME_CTXT_MSB_IN_QP      0x1000
 118 #define QIB_RUNTIME_CTXT_REDIRECT       0x2000
 119 #define QIB_RUNTIME_HDRSUPP             0x4000
 120
 121 /*
 122  * This structure is returned by qib_userinit() immediately after
 123  * open to get implementation-specific info, and info specific to this
 124  * instance.
 125  *
 126  * This struct must have explict pad fields where type sizes
 127  * may result in different alignments between 32 and 64 bit
 128  * programs, since the 64 bit * bit kernel requires the user code
 129  * to have matching offsets
 130  */
 131 struct qib_base_info {
 132         /* version of hardware, for feature checking. */
 133         __u32 spi_hw_version;
 134         /* version of software, for feature checking. */
 135         __u32 spi_sw_version;
 136         /* QLogic_IB context assigned, goes into sent packets */
 137         __u16 spi_ctxt;
 138         __u16 spi_subctxt;
 139         /*
 140          * IB MTU, packets IB data must be less than this.
 141          * The MTU is in bytes, and will be a multiple of 4 bytes.
 142          */
 143         __u32 spi_mtu;
 144         /*
 145          * Size of a PIO buffer.  Any given packet's total size must be less
 146          * than this (in words).  Included is the starting control word, so
 147          * if 513 is returned, then total pkt size is 512 words or less.
 148          */
 149         __u32 spi_piosize;
 150         /* size of the TID cache in qlogic_ib, in entries */
 151         __u32 spi_tidcnt;
 152         /* size of the TID Eager list in qlogic_ib, in entries */
 153         __u32 spi_tidegrcnt;
 154         /* size of a single receive header queue entry in words. */
 155         __u32 spi_rcvhdrent_size;
 156         /*
 157          * Count of receive header queue entries allocated.
 158          * This may be less than the spu_rcvhdrcnt passed in!.
 159          */
 160         __u32 spi_rcvhdr_cnt;
 161
 162         /* per-chip and other runtime features bitmap (QIB_RUNTIME_*) */
 163         __u32 spi_runtime_flags;
 164
 165         /* address where hardware receive header queue is mapped */
 166         __u64 spi_rcvhdr_base;
 167
 168         /* user program. */
 169
 170         /* base address of eager TID receive buffers used by hardware. */
 171         __u64 spi_rcv_egrbufs;
 172
 173         /* Allocated by initialization code, not by protocol. */
 174
 175         /*
 176          * Size of each TID buffer in host memory, starting at
 177          * spi_rcv_egrbufs.  The buffers are virtually contiguous.
 178          */
 179         __u32 spi_rcv_egrbufsize;
 180         /*
 181          * The special QP (queue pair) value that identifies an qlogic_ib
 182          * protocol packet from standard IB packets.  More, probably much
 183          * more, to be added.
 184          */
 185         __u32 spi_qpair;
 186
 187         /*
 188          * User register base for init code, not to be used directly by
 189          * protocol or applications.  Always points to chip registers,
 190          * for normal or shared context.
 191          */
 192         __u64 spi_uregbase;
 193         /*
 194          * Maximum buffer size in bytes that can be used in a single TID
 195          * entry (assuming the buffer is aligned to this boundary).  This is
 196          * the minimum of what the hardware and software support Guaranteed
 197          * to be a power of 2.
 198          */
 199         __u32 spi_tid_maxsize;
 200         /*
 201          * alignment of each pio send buffer (byte count
 202          * to add to spi_piobufbase to get to second buffer)
 203          */
 204         __u32 spi_pioalign;
 205         /*
 206          * The index of the first pio buffer available to this process;
 207          * needed to do lookup in spi_pioavailaddr; not added to
 208          * spi_piobufbase.
 209          */
 210         __u32 spi_pioindex;
 211          /* number of buffers mapped for this process */
 212         __u32 spi_piocnt;
 213
 214         /*
 215          * Base address of writeonly pio buffers for this process.
 216          * Each buffer has spi_piosize words, and is aligned on spi_pioalign
 217          * boundaries.  spi_piocnt buffers are mapped from this address
 218          */
 219         __u64 spi_piobufbase;
 220
 221         /*
 222          * Base address of readonly memory copy of the pioavail registers.
 223          * There are 2 bits for each buffer.
 224          */
 225         __u64 spi_pioavailaddr;
 226
 227         /*
 228          * Address where driver updates a copy of the interface and driver
 229          * status (QIB_STATUS_*) as a 64 bit value.  It's followed by a
 230          * link status qword (formerly combined with driver status), then a
 231          * string indicating hardware error, if there was one.
 232          */
 233         __u64 spi_status;
 234
 235         /* number of chip ctxts available to user processes */
 236         __u32 spi_nctxts;
 237         __u16 spi_unit; /* unit number of chip we are using */
 238         __u16 spi_port; /* IB port number we are using */
 239         /* num bufs in each contiguous set */
 240         __u32 spi_rcv_egrperchunk;
 241         /* size in bytes of each contiguous set */
 242         __u32 spi_rcv_egrchunksize;
 243         /* total size of mmap to cover full rcvegrbuffers */
 244         __u32 spi_rcv_egrbuftotlen;
 245         __u32 spi_rhf_offset; /* dword offset in hdrqent for rcvhdr flags */
 246         /* address of readonly memory copy of the rcvhdrq tail register. */
 247         __u64 spi_rcvhdr_tailaddr;
 248
 249         /*
 250          * shared memory pages for subctxts if ctxt is shared; these cover
 251          * all the processes in the group sharing a single context.
 252          * all have enough space for the num_subcontexts value on this job.
 253          */
 254         __u64 spi_subctxt_uregbase;
 255         __u64 spi_subctxt_rcvegrbuf;
 256         __u64 spi_subctxt_rcvhdr_base;
 257
 258         /* shared memory page for send buffer disarm status */
 259         __u64 spi_sendbuf_status;
 260 } __attribute__ ((aligned(8)));
 261
 262 /*
 263  * This version number is given to the driver by the user code during
 264  * initialization in the spu_userversion field of qib_user_info, so
 265  * the driver can check for compatibility with user code.
 266  *
 267  * The major version changes when data structures
 268  * change in an incompatible way.  The driver must be the same or higher
 269  * for initialization to succeed.  In some cases, a higher version
 270  * driver will not interoperate with older software, and initialization
 271  * will return an error.
 272  */
 273 #define QIB_USER_SWMAJOR 1
 274
 275 /*
 276  * Minor version differences are always compatible
 277  * a within a major version, however if user software is larger
 278  * than driver software, some new features and/or structure fields
 279  * may not be implemented; the user code must deal with this if it
 280  * cares, or it must abort after initialization reports the difference.
 281  */
 282 #define QIB_USER_SWMINOR 11
 283
 284 #define QIB_USER_SWVERSION ((QIB_USER_SWMAJOR << 16) | QIB_USER_SWMINOR)
 285
 286 #ifndef QIB_KERN_TYPE
 287 #define QIB_KERN_TYPE 0
 288 #define QIB_IDSTR "QLogic kernel.org driver"
 289 #endif
 290
 291 /*
 292  * Similarly, this is the kernel version going back to the user.  It's
 293  * slightly different, in that we want to tell if the driver was built as
 294  * part of a QLogic release, or from the driver from openfabrics.org,
 295  * kernel.org, or a standard distribution, for support reasons.
 296  * The high bit is 0 for non-QLogic and 1 for QLogic-built/supplied.
 297  *
 298  * It's returned by the driver to the user code during initialization in the
 299  * spi_sw_version field of qib_base_info, so the user code can in turn
 300  * check for compatibility with the kernel.
 301 */
 302 #define QIB_KERN_SWVERSION ((QIB_KERN_TYPE << 31) | QIB_USER_SWVERSION)
 303
 304 /*
 305  * If the unit is specified via open, HCA choice is fixed.  If port is
 306  * specified, it's also fixed.  Otherwise we try to spread contexts
 307  * across ports and HCAs, using different algorithims.  WITHIN is
 308  * the old default, prior to this mechanism.
 309  */
 310 #define QIB_PORT_ALG_ACROSS 0 /* round robin contexts across HCAs, then
 311                                * ports; this is the default */
 312 #define QIB_PORT_ALG_WITHIN 1 /* use all contexts on an HCA (round robin
 313                                * active ports within), then next HCA */
 314 #define QIB_PORT_ALG_COUNT 2 /* number of algorithm choices */
 315
 316 /*
 317  * This structure is passed to qib_userinit() to tell the driver where
 318  * user code buffers are, sizes, etc.   The offsets and sizes of the
 319  * fields must remain unchanged, for binary compatibility.  It can
 320  * be extended, if userversion is changed so user code can tell, if needed
 321  */
 322 struct qib_user_info {
 323         /*
 324          * version of user software, to detect compatibility issues.
 325          * Should be set to QIB_USER_SWVERSION.
 326          */
 327         __u32 spu_userversion;
 328
 329         __u32 _spu_unused2;
 330
 331         /* size of struct base_info to write to */
 332         __u32 spu_base_info_size;
 333
 334         __u32 spu_port_alg; /* which QIB_PORT_ALG_*; unused user minor < 11 */
 335
 336         /*
 337          * If two or more processes wish to share a context, each process
 338          * must set the spu_subctxt_cnt and spu_subctxt_id to the same
 339          * values.  The only restriction on the spu_subctxt_id is that
 340          * it be unique for a given node.
 341          */
 342         __u16 spu_subctxt_cnt;
 343         __u16 spu_subctxt_id;
 344
 345         __u32 spu_port; /* IB port requested by user if > 0 */
 346
 347         /*
 348          * address of struct base_info to write to
 349          */
 350         __u64 spu_base_info;
 351
 352 } __attribute__ ((aligned(8)));
 353
 354 /* User commands. */
 355
 356 /* 16 available, was: old set up userspace (for old user code) */
 357 #define QIB_CMD_CTXT_INFO       17      /* find out what resources we got */
 358 #define QIB_CMD_RECV_CTRL       18      /* control receipt of packets */
 359 #define QIB_CMD_TID_UPDATE      19      /* update expected TID entries */
 360 #define QIB_CMD_TID_FREE        20      /* free expected TID entries */
 361 #define QIB_CMD_SET_PART_KEY    21      /* add partition key */
 362 /* 22 available, was: return info on slave processes (for old user code) */
 363 #define QIB_CMD_ASSIGN_CTXT     23      /* allocate HCA and ctxt */
 364 #define QIB_CMD_USER_INIT       24      /* set up userspace */
 365 #define QIB_CMD_UNUSED_1        25
 366 #define QIB_CMD_UNUSED_2        26
 367 #define QIB_CMD_PIOAVAILUPD     27      /* force an update of PIOAvail reg */
 368 #define QIB_CMD_POLL_TYPE       28      /* set the kind of polling we want */
 369 #define QIB_CMD_ARMLAUNCH_CTRL  29      /* armlaunch detection control */
 370 /* 30 is unused */
 371 #define QIB_CMD_SDMA_INFLIGHT   31      /* sdma inflight counter request */
 372 #define QIB_CMD_SDMA_COMPLETE   32      /* sdma completion counter request */
 373 /* 33 available, was a testing feature  */
 374 #define QIB_CMD_DISARM_BUFS     34      /* disarm send buffers w/ errors */
 375 #define QIB_CMD_ACK_EVENT       35      /* ack & clear bits */
 376 #define QIB_CMD_CPUS_LIST       36      /* list of cpus allocated, for pinned
 377                                          * processes: qib_cpus_list */
 378
 379 /*
 380  * QIB_CMD_ACK_EVENT obsoletes QIB_CMD_DISARM_BUFS, but we keep it for
 381  * compatibility with libraries from previous release.   The ACK_EVENT
 382  * will take appropriate driver action (if any, just DISARM for now),
 383  * then clear the bits passed in as part of the mask.  These bits are
 384  * in the first 64bit word at spi_sendbuf_status, and are passed to
 385  * the driver in the event_mask union as well.
 386  */
 387 #define _QIB_EVENT_DISARM_BUFS_BIT      0
 388 #define _QIB_EVENT_LINKDOWN_BIT         1
 389 #define _QIB_EVENT_LID_CHANGE_BIT       2
 390 #define _QIB_EVENT_LMC_CHANGE_BIT       3
 391 #define _QIB_EVENT_SL2VL_CHANGE_BIT     4
 392 #define _QIB_MAX_EVENT_BIT _QIB_EVENT_SL2VL_CHANGE_BIT
 393
 394 #define QIB_EVENT_DISARM_BUFS_BIT       (1UL << _QIB_EVENT_DISARM_BUFS_BIT)
 395 #define QIB_EVENT_LINKDOWN_BIT          (1UL << _QIB_EVENT_LINKDOWN_BIT)
 396 #define QIB_EVENT_LID_CHANGE_BIT        (1UL << _QIB_EVENT_LID_CHANGE_BIT)
 397 #define QIB_EVENT_LMC_CHANGE_BIT        (1UL << _QIB_EVENT_LMC_CHANGE_BIT)
 398 #define QIB_EVENT_SL2VL_CHANGE_BIT      (1UL << _QIB_EVENT_SL2VL_CHANGE_BIT)
 399
 400
 401 /*
 402  * Poll types
 403  */
 404 #define QIB_POLL_TYPE_ANYRCV     0x0
 405 #define QIB_POLL_TYPE_URGENT     0x1
 406
 407 struct qib_ctxt_info {
 408         __u16 num_active;       /* number of active units */
 409         __u16 unit;             /* unit (chip) assigned to caller */
 410         __u16 port;             /* IB port assigned to caller (1-based) */
 411         __u16 ctxt;             /* ctxt on unit assigned to caller */
 412         __u16 subctxt;          /* subctxt on unit assigned to caller */
 413         __u16 num_ctxts;        /* number of ctxts available on unit */
 414         __u16 num_subctxts;     /* number of subctxts opened on ctxt */
 415         __u16 rec_cpu;          /* cpu # for affinity (ffff if none) */
 416 };
 417
 418 struct qib_tid_info {
 419         __u32 tidcnt;
 420         /* make structure same size in 32 and 64 bit */
 421         __u32 tid__unused;
 422         /* virtual address of first page in transfer */
 423         __u64 tidvaddr;
 424         /* pointer (same size 32/64 bit) to __u16 tid array */
 425         __u64 tidlist;
 426
 427         /*
 428          * pointer (same size 32/64 bit) to bitmap of TIDs used
 429          * for this call; checked for being large enough at open
 430          */
 431         __u64 tidmap;
 432 };
 433
 434 struct qib_cmd {
 435         __u32 type;                     /* command type */
 436         union {
 437                 struct qib_tid_info tid_info;
 438                 struct qib_user_info user_info;
 439
 440                 /*
 441                  * address in userspace where we should put the sdma
 442                  * inflight counter
 443                  */
 444                 __u64 sdma_inflight;
 445                 /*
 446                  * address in userspace where we should put the sdma
 447                  * completion counter
 448                  */
 449                 __u64 sdma_complete;
 450                 /* address in userspace of struct qib_ctxt_info to
 451                    write result to */
 452                 __u64 ctxt_info;
 453                 /* enable/disable receipt of packets */
 454                 __u32 recv_ctrl;
 455                 /* enable/disable armlaunch errors (non-zero to enable) */
 456                 __u32 armlaunch_ctrl;
 457                 /* partition key to set */
 458                 __u16 part_key;
 459                 /* user address of __u32 bitmask of active slaves */
 460                 __u64 slave_mask_addr;
 461                 /* type of polling we want */
 462                 __u16 poll_type;
 463                 /* back pressure enable bit for one particular context */
 464                 __u8 ctxt_bp;
 465                 /* qib_user_event_ack(), IPATH_EVENT_* bits */
 466                 __u64 event_mask;
 467         } cmd;
 468 };
 469
 470 struct qib_iovec {
 471         /* Pointer to data, but same size 32 and 64 bit */
 472         __u64 iov_base;
 473
 474         /*
 475          * Length of data; don't need 64 bits, but want
 476          * qib_sendpkt to remain same size as before 32 bit changes, so...
 477          */
 478         __u64 iov_len;
 479 };
 480
 481 /*
 482  * Describes a single packet for send.  Each packet can have one or more
 483  * buffers, but the total length (exclusive of IB headers) must be less
 484  * than the MTU, and if using the PIO method, entire packet length,
 485  * including IB headers, must be less than the qib_piosize value (words).
 486  * Use of this necessitates including sys/uio.h
 487  */
 488 struct __qib_sendpkt {
 489         __u32 sps_flags;        /* flags for packet (TBD) */
 490         __u32 sps_cnt;          /* number of entries to use in sps_iov */
 491         /* array of iov's describing packet. TEMPORARY */
 492         struct qib_iovec sps_iov[4];
 493 };
 494
 495 /*
 496  * Diagnostics can send a packet by "writing" the following
 497  * structs to the diag data special file.
 498  * This allows a custom
 499  * pbc (+ static rate) qword, so that special modes and deliberate
 500  * changes to CRCs can be used. The elements were also re-ordered
 501  * for better alignment and to avoid padding issues.
 502  */
 503 #define _DIAG_XPKT_VERS 3
 504 struct qib_diag_xpkt {
 505         __u16 version;
 506         __u16 unit;
 507         __u16 port;
 508         __u16 len;
 509         __u64 data;
 510         __u64 pbc_wd;
 511 };
 512
 513 /*
 514  * Data layout in I2C flash (for GUID, etc.)
 515  * All fields are little-endian binary unless otherwise stated
 516  */
 517 #define QIB_FLASH_VERSION 2
 518 struct qib_flash {
 519         /* flash layout version (QIB_FLASH_VERSION) */
 520         __u8 if_fversion;
 521         /* checksum protecting if_length bytes */
 522         __u8 if_csum;
 523         /*
 524          * valid length (in use, protected by if_csum), including
 525          * if_fversion and if_csum themselves)
 526          */
 527         __u8 if_length;
 528         /* the GUID, in network order */
 529         __u8 if_guid[8];
 530         /* number of GUIDs to use, starting from if_guid */
 531         __u8 if_numguid;
 532         /* the (last 10 characters of) board serial number, in ASCII */
 533         char if_serial[12];
 534         /* board mfg date (YYYYMMDD ASCII) */
 535         char if_mfgdate[8];
 536         /* last board rework/test date (YYYYMMDD ASCII) */
 537         char if_testdate[8];
 538         /* logging of error counts, TBD */
 539         __u8 if_errcntp[4];
 540         /* powered on hours, updated at driver unload */
 541         __u8 if_powerhour[2];
 542         /* ASCII free-form comment field */
 543         char if_comment[32];
 544         /* Backwards compatible prefix for longer QLogic Serial Numbers */
 545         char if_sprefix[4];
 546         /* 82 bytes used, min flash size is 128 bytes */
 547         __u8 if_future[46];
 548 };
 549
 550 /*
 551  * These are the counters implemented in the chip, and are listed in order.
 552  * The InterCaps naming is taken straight from the chip spec.
 553  */
 554 struct qlogic_ib_counters {
 555         __u64 LBIntCnt;
 556         __u64 LBFlowStallCnt;
 557         __u64 TxSDmaDescCnt;    /* was Reserved1 */
 558         __u64 TxUnsupVLErrCnt;
 559         __u64 TxDataPktCnt;
 560         __u64 TxFlowPktCnt;
 561         __u64 TxDwordCnt;
 562         __u64 TxLenErrCnt;
 563         __u64 TxMaxMinLenErrCnt;
 564         __u64 TxUnderrunCnt;
 565         __u64 TxFlowStallCnt;
 566         __u64 TxDroppedPktCnt;
 567         __u64 RxDroppedPktCnt;
 568         __u64 RxDataPktCnt;
 569         __u64 RxFlowPktCnt;
 570         __u64 RxDwordCnt;
 571         __u64 RxLenErrCnt;
 572         __u64 RxMaxMinLenErrCnt;
 573         __u64 RxICRCErrCnt;
 574         __u64 RxVCRCErrCnt;
 575         __u64 RxFlowCtrlErrCnt;
 576         __u64 RxBadFormatCnt;
 577         __u64 RxLinkProblemCnt;
 578         __u64 RxEBPCnt;
 579         __u64 RxLPCRCErrCnt;
 580         __u64 RxBufOvflCnt;
 581         __u64 RxTIDFullErrCnt;
 582         __u64 RxTIDValidErrCnt;
 583         __u64 RxPKeyMismatchCnt;
 584         __u64 RxP0HdrEgrOvflCnt;
 585         __u64 RxP1HdrEgrOvflCnt;
 586         __u64 RxP2HdrEgrOvflCnt;
 587         __u64 RxP3HdrEgrOvflCnt;
 588         __u64 RxP4HdrEgrOvflCnt;
 589         __u64 RxP5HdrEgrOvflCnt;
 590         __u64 RxP6HdrEgrOvflCnt;
 591         __u64 RxP7HdrEgrOvflCnt;
 592         __u64 RxP8HdrEgrOvflCnt;
 593         __u64 RxP9HdrEgrOvflCnt;
 594         __u64 RxP10HdrEgrOvflCnt;
 595         __u64 RxP11HdrEgrOvflCnt;
 596         __u64 RxP12HdrEgrOvflCnt;
 597         __u64 RxP13HdrEgrOvflCnt;
 598         __u64 RxP14HdrEgrOvflCnt;
 599         __u64 RxP15HdrEgrOvflCnt;
 600         __u64 RxP16HdrEgrOvflCnt;
 601         __u64 IBStatusChangeCnt;
 602         __u64 IBLinkErrRecoveryCnt;
 603         __u64 IBLinkDownedCnt;
 604         __u64 IBSymbolErrCnt;
 605         __u64 RxVL15DroppedPktCnt;
 606         __u64 RxOtherLocalPhyErrCnt;
 607         __u64 PcieRetryBufDiagQwordCnt;
 608         __u64 ExcessBufferOvflCnt;
 609         __u64 LocalLinkIntegrityErrCnt;
 610         __u64 RxVlErrCnt;
 611         __u64 RxDlidFltrCnt;
 612 };
 613
 614 /*
 615  * The next set of defines are for packet headers, and chip register
 616  * and memory bits that are visible to and/or used by user-mode software.
 617  */
 618
 619 /* RcvHdrFlags bits */
 620 #define QLOGIC_IB_RHF_LENGTH_MASK 0x7FF
 621 #define QLOGIC_IB_RHF_LENGTH_SHIFT 0
 622 #define QLOGIC_IB_RHF_RCVTYPE_MASK 0x7
 623 #define QLOGIC_IB_RHF_RCVTYPE_SHIFT 11
 624 #define QLOGIC_IB_RHF_EGRINDEX_MASK 0xFFF
 625 #define QLOGIC_IB_RHF_EGRINDEX_SHIFT 16
 626 #define QLOGIC_IB_RHF_SEQ_MASK 0xF
 627 #define QLOGIC_IB_RHF_SEQ_SHIFT 0
 628 #define QLOGIC_IB_RHF_HDRQ_OFFSET_MASK 0x7FF
 629 #define QLOGIC_IB_RHF_HDRQ_OFFSET_SHIFT 4
 630 #define QLOGIC_IB_RHF_H_ICRCERR   0x80000000
 631 #define QLOGIC_IB_RHF_H_VCRCERR   0x40000000
 632 #define QLOGIC_IB_RHF_H_PARITYERR 0x20000000
 633 #define QLOGIC_IB_RHF_H_LENERR    0x10000000
 634 #define QLOGIC_IB_RHF_H_MTUERR    0x08000000
 635 #define QLOGIC_IB_RHF_H_IHDRERR   0x04000000
 636 #define QLOGIC_IB_RHF_H_TIDERR    0x02000000
 637 #define QLOGIC_IB_RHF_H_MKERR     0x01000000
 638 #define QLOGIC_IB_RHF_H_IBERR     0x00800000
 639 #define QLOGIC_IB_RHF_H_ERR_MASK  0xFF800000
 640 #define QLOGIC_IB_RHF_L_USE_EGR   0x80000000
 641 #define QLOGIC_IB_RHF_L_SWA       0x00008000
 642 #define QLOGIC_IB_RHF_L_SWB       0x00004000
 643
 644 /* qlogic_ib header fields */
 645 #define QLOGIC_IB_I_VERS_MASK 0xF
 646 #define QLOGIC_IB_I_VERS_SHIFT 28
 647 #define QLOGIC_IB_I_CTXT_MASK 0xF
 648 #define QLOGIC_IB_I_CTXT_SHIFT 24
 649 #define QLOGIC_IB_I_TID_MASK 0x7FF
 650 #define QLOGIC_IB_I_TID_SHIFT 13
 651 #define QLOGIC_IB_I_OFFSET_MASK 0x1FFF
 652 #define QLOGIC_IB_I_OFFSET_SHIFT 0
 653
 654 /* K_PktFlags bits */
 655 #define QLOGIC_IB_KPF_INTR 0x1
 656 #define QLOGIC_IB_KPF_SUBCTXT_MASK 0x3
 657 #define QLOGIC_IB_KPF_SUBCTXT_SHIFT 1
 658
 659 #define QLOGIC_IB_MAX_SUBCTXT   4
 660
 661 /* SendPIO per-buffer control */
 662 #define QLOGIC_IB_SP_TEST    0x40
 663 #define QLOGIC_IB_SP_TESTEBP 0x20
 664 #define QLOGIC_IB_SP_TRIGGER_SHIFT  15
 665
 666 /* SendPIOAvail bits */
 667 #define QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT 1
 668 #define QLOGIC_IB_SENDPIOAVAIL_CHECK_SHIFT 0
 669
 670 /* qlogic_ib header format */
 671 struct qib_header {
 672         /*
 673          * Version - 4 bits, Context - 4 bits, TID - 10 bits and Offset -
 674          * 14 bits before ECO change ~28 Dec 03.  After that, Vers 4,
 675          * Context 4, TID 11, offset 13.
 676          */
 677         __le32 ver_ctxt_tid_offset;
 678         __le16 chksum;
 679         __le16 pkt_flags;
 680 };
 681
 682 /*
 683  * qlogic_ib user message header format.
 684  * This structure contains the first 4 fields common to all protocols
 685  * that employ qlogic_ib.
 686  */
 687 struct qib_message_header {
 688         __be16 lrh[4];
 689         __be32 bth[3];
 690         /* fields below this point are in host byte order */
 691         struct qib_header iph;
 692         __u8 sub_opcode;
 693 };
 694
 695 /* IB - LRH header consts */
 696 #define QIB_LRH_GRH 0x0003      /* 1. word of IB LRH - next header: GRH */
 697 #define QIB_LRH_BTH 0x0002      /* 1. word of IB LRH - next header: BTH */
 698
 699 /* misc. */
 700 #define SIZE_OF_CRC 1
 701
 702 #define QIB_DEFAULT_P_KEY 0xFFFF
 703 #define QIB_PERMISSIVE_LID 0xFFFF
 704 #define QIB_AETH_CREDIT_SHIFT 24
 705 #define QIB_AETH_CREDIT_MASK 0x1F
 706 #define QIB_AETH_CREDIT_INVAL 0x1F
 707 #define QIB_PSN_MASK 0xFFFFFF
 708 #define QIB_MSN_MASK 0xFFFFFF
 709 #define QIB_QPN_MASK 0xFFFFFF
 710 #define QIB_MULTICAST_LID_BASE 0xC000
 711 #define QIB_EAGER_TID_ID QLOGIC_IB_I_TID_MASK
 712 #define QIB_MULTICAST_QPN 0xFFFFFF
 713
 714 /* Receive Header Queue: receive type (from qlogic_ib) */
 715 #define RCVHQ_RCV_TYPE_EXPECTED  0
 716 #define RCVHQ_RCV_TYPE_EAGER     1
 717 #define RCVHQ_RCV_TYPE_NON_KD    2
 718 #define RCVHQ_RCV_TYPE_ERROR     3
 719
 720 #define QIB_HEADER_QUEUE_WORDS 9
 721
 722 /* functions for extracting fields from rcvhdrq entries for the driver.
 723  */
 724 static inline __u32 qib_hdrget_err_flags(const __le32 *rbuf)
 725 {
 726         return __le32_to_cpu(rbuf[1]) & QLOGIC_IB_RHF_H_ERR_MASK;
 727 }
 728
 729 static inline __u32 qib_hdrget_rcv_type(const __le32 *rbuf)
 730 {
 731         return (__le32_to_cpu(rbuf[0]) >> QLOGIC_IB_RHF_RCVTYPE_SHIFT) &
 732                 QLOGIC_IB_RHF_RCVTYPE_MASK;
 733 }
 734
 735 static inline __u32 qib_hdrget_length_in_bytes(const __le32 *rbuf)
 736 {
 737         return ((__le32_to_cpu(rbuf[0]) >> QLOGIC_IB_RHF_LENGTH_SHIFT) &
 738                 QLOGIC_IB_RHF_LENGTH_MASK) << 2;
 739 }
 740
 741 static inline __u32 qib_hdrget_index(const __le32 *rbuf)
 742 {
 743         return (__le32_to_cpu(rbuf[0]) >> QLOGIC_IB_RHF_EGRINDEX_SHIFT) &
 744                 QLOGIC_IB_RHF_EGRINDEX_MASK;
 745 }
 746
 747 static inline __u32 qib_hdrget_seq(const __le32 *rbuf)
 748 {
 749         return (__le32_to_cpu(rbuf[1]) >> QLOGIC_IB_RHF_SEQ_SHIFT) &
 750                 QLOGIC_IB_RHF_SEQ_MASK;
 751 }
 752
 753 static inline __u32 qib_hdrget_offset(const __le32 *rbuf)
 754 {
 755         return (__le32_to_cpu(rbuf[1]) >> QLOGIC_IB_RHF_HDRQ_OFFSET_SHIFT) &
 756                 QLOGIC_IB_RHF_HDRQ_OFFSET_MASK;
 757 }
 758
 759 static inline __u32 qib_hdrget_use_egr_buf(const __le32 *rbuf)
 760 {
 761         return __le32_to_cpu(rbuf[0]) & QLOGIC_IB_RHF_L_USE_EGR;
 762 }
 763
 764 static inline __u32 qib_hdrget_qib_ver(__le32 hdrword)
 765 {
 766         return (__le32_to_cpu(hdrword) >> QLOGIC_IB_I_VERS_SHIFT) &
 767                 QLOGIC_IB_I_VERS_MASK;
 768 }
 769
 770 #endif                          /* _QIB_COMMON_H */