release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/i2c/busses/i2c-ibm_iic.c

   1 /*
   2  * drivers/i2c/busses/i2c-ibm_iic.c
   3  *
   4  * Support for the IIC peripheral on IBM PPC 4xx
   5  *
   6  * Copyright (c) 2003, 2004 Zultys Technologies.
   7  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
   8  *
   9  * Copyright (c) 2008 PIKA Technologies
  10  * Sean MacLennan <smaclennan@pikatech.com>
  11  *
  12  * Based on original work by
  13  *      Ian DaSilva  <idasilva@mvista.com>
  14  *      Armin Kuster <akuster@mvista.com>
  15  *      Matt Porter  <mporter@mvista.com>
  16  *
  17  *      Copyright 2000-2003 MontaVista Software Inc.
  18  *
  19  * Original driver version was highly leveraged from i2c-elektor.c
  20  *
  21  *      Copyright 1995-97 Simon G. Vogl
  22  *                1998-99 Hans Berglund
  23  *
  24  *      With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi>
  25  *      and even Frodo Looijaard <frodol@dds.nl>
  26  *
  27  * This program is free software; you can redistribute  it and/or modify it
  28  * under  the terms of  the GNU General  Public License as published by the
  29  * Free Software Foundation;  either version 2 of the  License, or (at your
  30  * option) any later version.
  31  *
  32  */
  33
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/ioport.h>
  37 #include <linux/delay.h>
  38 #include <linux/slab.h>
  39 #include <linux/init.h>
  40 #include <linux/interrupt.h>
  41 #include <asm/irq.h>
  42 #include <linux/io.h>
  43 #include <linux/i2c.h>
  44 #include <linux/i2c-id.h>
  45 #include <linux/of_platform.h>
  46 #include <linux/of_i2c.h>
  47
  48 #include "i2c-ibm_iic.h"
  49
  50 #define DRIVER_VERSION "2.2"
  51
  52 MODULE_DESCRIPTION("IBM IIC driver v" DRIVER_VERSION);
  53 MODULE_LICENSE("GPL");
  54
  55 static int iic_force_poll;
  56 module_param(iic_force_poll, bool, 0);
  57 MODULE_PARM_DESC(iic_force_poll, "Force polling mode");
  58
  59 static int iic_force_fast;
  60 module_param(iic_force_fast, bool, 0);
  61 MODULE_PARM_DESC(iic_force_fast, "Force fast mode (400 kHz)");
  62
  63 #define DBG_LEVEL 0
  64
  65 #ifdef DBG
  66 #undef DBG
  67 #endif
  68
  69 #ifdef DBG2
  70 #undef DBG2
  71 #endif
  72
  73 #if DBG_LEVEL > 0
  74 #  define DBG(f,x...)   printk(KERN_DEBUG "ibm-iic" f, ##x)
  75 #else
  76 #  define DBG(f,x...)   ((void)0)
  77 #endif
  78 #if DBG_LEVEL > 1
  79 #  define DBG2(f,x...)  DBG(f, ##x)
  80 #else
  81 #  define DBG2(f,x...)  ((void)0)
  82 #endif
  83 #if DBG_LEVEL > 2
  84 static void dump_iic_regs(const char* header, struct ibm_iic_private* dev)
  85 {
  86         volatile struct iic_regs __iomem *iic = dev->vaddr;
  87         printk(KERN_DEBUG "ibm-iic%d: %s\n", dev->idx, header);
  88         printk(KERN_DEBUG
  89                "  cntl     = 0x%02x, mdcntl = 0x%02x\n"
  90                "  sts      = 0x%02x, extsts = 0x%02x\n"
  91                "  clkdiv   = 0x%02x, xfrcnt = 0x%02x\n"
  92                "  xtcntlss = 0x%02x, directcntl = 0x%02x\n",
  93                 in_8(&iic->cntl), in_8(&iic->mdcntl), in_8(&iic->sts),
  94                 in_8(&iic->extsts), in_8(&iic->clkdiv), in_8(&iic->xfrcnt),
  95                 in_8(&iic->xtcntlss), in_8(&iic->directcntl));
  96 }
  97 #  define DUMP_REGS(h,dev)      dump_iic_regs((h),(dev))
  98 #else
  99 #  define DUMP_REGS(h,dev)      ((void)0)
 100 #endif
 101
 102 /* Bus timings (in ns) for bit-banging */
 103 static struct i2c_timings {
 104         unsigned int hd_sta;
 105         unsigned int su_sto;
 106         unsigned int low;
 107         unsigned int high;
 108         unsigned int buf;
 109 } timings [] = {
 110 /* Standard mode (100 KHz) */
 111 {
 112         .hd_sta = 4000,
 113         .su_sto = 4000,
 114         .low    = 4700,
 115         .high   = 4000,
 116         .buf    = 4700,
 117 },
 118 /* Fast mode (400 KHz) */
 119 {
 120         .hd_sta = 600,
 121         .su_sto = 600,
 122         .low    = 1300,
 123         .high   = 600,
 124         .buf    = 1300,
 125 }};
 126
 127 /* Enable/disable interrupt generation */
 128 static inline void iic_interrupt_mode(struct ibm_iic_private* dev, int enable)
 129 {
 130         out_8(&dev->vaddr->intmsk, enable ? INTRMSK_EIMTC : 0);
 131 }
 132
 133 /*
 134  * Initialize IIC interface.
 135  */
 136 static void iic_dev_init(struct ibm_iic_private* dev)
 137 {
 138         volatile struct iic_regs __iomem *iic = dev->vaddr;
 139
 140         DBG("%d: init\n", dev->idx);
 141
 142         /* Clear master address */
 143         out_8(&iic->lmadr, 0);
 144         out_8(&iic->hmadr, 0);
 145
 146         /* Clear slave address */
 147         out_8(&iic->lsadr, 0);
 148         out_8(&iic->hsadr, 0);
 149
 150         /* Clear status & extended status */
 151         out_8(&iic->sts, STS_SCMP | STS_IRQA);
 152         out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD | EXTSTS_LA
 153                             | EXTSTS_ICT | EXTSTS_XFRA);
 154
 155         /* Set clock divider */
 156         out_8(&iic->clkdiv, dev->clckdiv);
 157
 158         /* Clear transfer count */
 159         out_8(&iic->xfrcnt, 0);
 160
 161         /* Clear extended control and status */
 162         out_8(&iic->xtcntlss, XTCNTLSS_SRC | XTCNTLSS_SRS | XTCNTLSS_SWC
 163                             | XTCNTLSS_SWS);
 164
 165         /* Clear control register */
 166         out_8(&iic->cntl, 0);
 167
 168         /* Enable interrupts if possible */
 169         iic_interrupt_mode(dev, dev->irq >= 0);
 170
 171         /* Set mode control */
 172         out_8(&iic->mdcntl, MDCNTL_FMDB | MDCNTL_EINT | MDCNTL_EUBS
 173                             | (dev->fast_mode ? MDCNTL_FSM : 0));
 174
 175         DUMP_REGS("iic_init", dev);
 176 }
 177
 178 /*
 179  * Reset IIC interface
 180  */
 181 static void iic_dev_reset(struct ibm_iic_private* dev)
 182 {
 183         volatile struct iic_regs __iomem *iic = dev->vaddr;
 184         int i;
 185         u8 dc;
 186
 187         DBG("%d: soft reset\n", dev->idx);
 188         DUMP_REGS("reset", dev);
 189
 190         /* Place chip in the reset state */
 191         out_8(&iic->xtcntlss, XTCNTLSS_SRST);
 192
 193         /* Check if bus is free */
 194         dc = in_8(&iic->directcntl);
 195         if (!DIRCTNL_FREE(dc)){
 196                 DBG("%d: trying to regain bus control\n", dev->idx);
 197
 198                 /* Try to set bus free state */
 199                 out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
 200
 201                 /* Wait until we regain bus control */
 202                 for (i = 0; i < 100; ++i){
 203                         dc = in_8(&iic->directcntl);
 204                         if (DIRCTNL_FREE(dc))
 205                                 break;
 206
 207                         /* Toggle SCL line */
 208                         dc ^= DIRCNTL_SCC;
 209                         out_8(&iic->directcntl, dc);
 210                         udelay(10);
 211                         dc ^= DIRCNTL_SCC;
 212                         out_8(&iic->directcntl, dc);
 213
 214                         /* be nice */
 215                         cond_resched();
 216                 }
 217         }
 218
 219         /* Remove reset */
 220         out_8(&iic->xtcntlss, 0);
 221
 222         /* Reinitialize interface */
 223         iic_dev_init(dev);
 224 }
 225
 226 /*
 227  * Do 0-length transaction using bit-banging through IIC_DIRECTCNTL register.
 228  */
 229
 230 /* Wait for SCL and/or SDA to be high */
 231 static int iic_dc_wait(volatile struct iic_regs __iomem *iic, u8 mask)
 232 {
 233         unsigned long x = jiffies + HZ / 28 + 2;
 234         while ((in_8(&iic->directcntl) & mask) != mask){
 235                 if (unlikely(time_after(jiffies, x)))
 236                         return -1;
 237                 cond_resched();
 238         }
 239         return 0;
 240 }
 241
 242 static int iic_smbus_quick(struct ibm_iic_private* dev, const struct i2c_msg* p)
 243 {
 244         volatile struct iic_regs __iomem *iic = dev->vaddr;
 245         const struct i2c_timings* t = &timings[dev->fast_mode ? 1 : 0];
 246         u8 mask, v, sda;
 247         int i, res;
 248
 249         /* Only 7-bit addresses are supported */
 250         if (unlikely(p->flags & I2C_M_TEN)){
 251                 DBG("%d: smbus_quick - 10 bit addresses are not supported\n",
 252                         dev->idx);
 253                 return -EINVAL;
 254         }
 255
 256         DBG("%d: smbus_quick(0x%02x)\n", dev->idx, p->addr);
 257
 258         /* Reset IIC interface */
 259         out_8(&iic->xtcntlss, XTCNTLSS_SRST);
 260
 261         /* Wait for bus to become free */
 262         out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
 263         if (unlikely(iic_dc_wait(iic, DIRCNTL_MSDA | DIRCNTL_MSC)))
 264                 goto err;
 265         ndelay(t->buf);
 266
 267         /* START */
 268         out_8(&iic->directcntl, DIRCNTL_SCC);
 269         sda = 0;
 270         ndelay(t->hd_sta);
 271
 272         /* Send address */
 273         v = (u8)((p->addr << 1) | ((p->flags & I2C_M_RD) ? 1 : 0));
 274         for (i = 0, mask = 0x80; i < 8; ++i, mask >>= 1){
 275                 out_8(&iic->directcntl, sda);
 276                 ndelay(t->low / 2);
 277                 sda = (v & mask) ? DIRCNTL_SDAC : 0;
 278                 out_8(&iic->directcntl, sda);
 279                 ndelay(t->low / 2);
 280
 281                 out_8(&iic->directcntl, DIRCNTL_SCC | sda);
 282                 if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
 283                         goto err;
 284                 ndelay(t->high);
 285         }
 286
 287         /* ACK */
 288         out_8(&iic->directcntl, sda);
 289         ndelay(t->low / 2);
 290         out_8(&iic->directcntl, DIRCNTL_SDAC);
 291         ndelay(t->low / 2);
 292         out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
 293         if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
 294                 goto err;
 295         res = (in_8(&iic->directcntl) & DIRCNTL_MSDA) ? -EREMOTEIO : 1;
 296         ndelay(t->high);
 297
 298         /* STOP */
 299         out_8(&iic->directcntl, 0);
 300         ndelay(t->low);
 301         out_8(&iic->directcntl, DIRCNTL_SCC);
 302         if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
 303                 goto err;
 304         ndelay(t->su_sto);
 305         out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
 306
 307         ndelay(t->buf);
 308
 309         DBG("%d: smbus_quick -> %s\n", dev->idx, res ? "NACK" : "ACK");
 310 out:
 311         /* Remove reset */
 312         out_8(&iic->xtcntlss, 0);
 313
 314         /* Reinitialize interface */
 315         iic_dev_init(dev);
 316
 317         return res;
 318 err:
 319         DBG("%d: smbus_quick - bus is stuck\n", dev->idx);
 320         res = -EREMOTEIO;
 321         goto out;
 322 }
 323
 324 /*
 325  * IIC interrupt handler
 326  */
 327 static irqreturn_t iic_handler(int irq, void *dev_id)
 328 {
 329         struct ibm_iic_private* dev = (struct ibm_iic_private*)dev_id;
 330         volatile struct iic_regs __iomem *iic = dev->vaddr;
 331
 332         DBG2("%d: irq handler, STS = 0x%02x, EXTSTS = 0x%02x\n",
 333              dev->idx, in_8(&iic->sts), in_8(&iic->extsts));
 334
 335         /* Acknowledge IRQ and wakeup iic_wait_for_tc */
 336         out_8(&iic->sts, STS_IRQA | STS_SCMP);
 337         wake_up_interruptible(&dev->wq);
 338
 339         return IRQ_HANDLED;
 340 }
 341
 342 /*
 343  * Get master transfer result and clear errors if any.
 344  * Returns the number of actually transferred bytes or error (<0)
 345  */
 346 static int iic_xfer_result(struct ibm_iic_private* dev)
 347 {
 348         volatile struct iic_regs __iomem *iic = dev->vaddr;
 349
 350         if (unlikely(in_8(&iic->sts) & STS_ERR)){
 351                 DBG("%d: xfer error, EXTSTS = 0x%02x\n", dev->idx,
 352                         in_8(&iic->extsts));
 353
 354                 /* Clear errors and possible pending IRQs */
 355                 out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD |
 356                         EXTSTS_LA | EXTSTS_ICT | EXTSTS_XFRA);
 357
 358                 /* Flush master data buffer */
 359                 out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
 360
 361                 /* Is bus free?
 362                  * If error happened during combined xfer
 363                  * IIC interface is usually stuck in some strange
 364                  * state, the only way out - soft reset.
 365                  */
 366                 if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
 367                         DBG("%d: bus is stuck, resetting\n", dev->idx);
 368                         iic_dev_reset(dev);
 369                 }
 370                 return -EREMOTEIO;
 371         }
 372         else
 373                 return in_8(&iic->xfrcnt) & XFRCNT_MTC_MASK;
 374 }
 375
 376 /*
 377  * Try to abort active transfer.
 378  */
 379 static void iic_abort_xfer(struct ibm_iic_private* dev)
 380 {
 381         volatile struct iic_regs __iomem *iic = dev->vaddr;
 382         unsigned long x;
 383
 384         DBG("%d: iic_abort_xfer\n", dev->idx);
 385
 386         out_8(&iic->cntl, CNTL_HMT);
 387
 388         /*
 389          * Wait for the abort command to complete.
 390          * It's not worth to be optimized, just poll (timeout >= 1 tick)
 391          */
 392         x = jiffies + 2;
 393         while ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
 394                 if (time_after(jiffies, x)){
 395                         DBG("%d: abort timeout, resetting...\n", dev->idx);
 396                         iic_dev_reset(dev);
 397                         return;
 398                 }
 399                 schedule();
 400         }
 401
 402         /* Just to clear errors */
 403         iic_xfer_result(dev);
 404 }
 405
 406 /*
 407  * Wait for master transfer to complete.
 408  * It puts current process to sleep until we get interrupt or timeout expires.
 409  * Returns the number of transferred bytes or error (<0)
 410  */
 411 static int iic_wait_for_tc(struct ibm_iic_private* dev){
 412
 413         volatile struct iic_regs __iomem *iic = dev->vaddr;
 414         int ret = 0;
 415
 416         if (dev->irq >= 0){
 417                 /* Interrupt mode */
 418                 ret = wait_event_interruptible_timeout(dev->wq,
 419                         !(in_8(&iic->sts) & STS_PT), dev->adap.timeout);
 420
 421                 if (unlikely(ret < 0))
 422                         DBG("%d: wait interrupted\n", dev->idx);
 423                 else if (unlikely(in_8(&iic->sts) & STS_PT)){
 424                         DBG("%d: wait timeout\n", dev->idx);
 425                         ret = -ETIMEDOUT;
 426                 }
 427         }
 428         else {
 429                 /* Polling mode */
 430                 unsigned long x = jiffies + dev->adap.timeout;
 431
 432                 while (in_8(&iic->sts) & STS_PT){
 433                         if (unlikely(time_after(jiffies, x))){
 434                                 DBG("%d: poll timeout\n", dev->idx);
 435                                 ret = -ETIMEDOUT;
 436                                 break;
 437                         }
 438
 439                         if (unlikely(signal_pending(current))){
 440                                 DBG("%d: poll interrupted\n", dev->idx);
 441                                 ret = -ERESTARTSYS;
 442                                 break;
 443                         }
 444                         schedule();
 445                 }
 446         }
 447
 448         if (unlikely(ret < 0))
 449                 iic_abort_xfer(dev);
 450         else
 451                 ret = iic_xfer_result(dev);
 452
 453         DBG2("%d: iic_wait_for_tc -> %d\n", dev->idx, ret);
 454
 455         return ret;
 456 }
 457
 458 /*
 459  * Low level master transfer routine
 460  */
 461 static int iic_xfer_bytes(struct ibm_iic_private* dev, struct i2c_msg* pm,
 462                           int combined_xfer)
 463 {
 464         volatile struct iic_regs __iomem *iic = dev->vaddr;
 465         char* buf = pm->buf;
 466         int i, j, loops, ret = 0;
 467         int len = pm->len;
 468
 469         u8 cntl = (in_8(&iic->cntl) & CNTL_AMD) | CNTL_PT;
 470         if (pm->flags & I2C_M_RD)
 471                 cntl |= CNTL_RW;
 472
 473         loops = (len + 3) / 4;
 474         for (i = 0; i < loops; ++i, len -= 4){
 475                 int count = len > 4 ? 4 : len;
 476                 u8 cmd = cntl | ((count - 1) << CNTL_TCT_SHIFT);
 477
 478                 if (!(cntl & CNTL_RW))
 479                         for (j = 0; j < count; ++j)
 480                                 out_8((void __iomem *)&iic->mdbuf, *buf++);
 481
 482                 if (i < loops - 1)
 483                         cmd |= CNTL_CHT;
 484                 else if (combined_xfer)
 485                         cmd |= CNTL_RPST;
 486
 487                 DBG2("%d: xfer_bytes, %d, CNTL = 0x%02x\n", dev->idx, count, cmd);
 488
 489                 /* Start transfer */
 490                 out_8(&iic->cntl, cmd);
 491
 492                 /* Wait for completion */
 493                 ret = iic_wait_for_tc(dev);
 494
 495                 if (unlikely(ret < 0))
 496                         break;
 497                 else if (unlikely(ret != count)){
 498                         DBG("%d: xfer_bytes, requested %d, transfered %d\n",
 499                                 dev->idx, count, ret);
 500
 501                         /* If it's not a last part of xfer, abort it */
 502                         if (combined_xfer || (i < loops - 1))
 503                                 iic_abort_xfer(dev);
 504
 505                         ret = -EREMOTEIO;
 506                         break;
 507                 }
 508
 509                 if (cntl & CNTL_RW)
 510                         for (j = 0; j < count; ++j)
 511                                 *buf++ = in_8((void __iomem *)&iic->mdbuf);
 512         }
 513
 514         return ret > 0 ? 0 : ret;
 515 }
 516
 517 /*
 518  * Set target slave address for master transfer
 519  */
 520 static inline void iic_address(struct ibm_iic_private* dev, struct i2c_msg* msg)
 521 {
 522         volatile struct iic_regs __iomem *iic = dev->vaddr;
 523         u16 addr = msg->addr;
 524
 525         DBG2("%d: iic_address, 0x%03x (%d-bit)\n", dev->idx,
 526                 addr, msg->flags & I2C_M_TEN ? 10 : 7);
 527
 528         if (msg->flags & I2C_M_TEN){
 529             out_8(&iic->cntl, CNTL_AMD);
 530             out_8(&iic->lmadr, addr);
 531             out_8(&iic->hmadr, 0xf0 | ((addr >> 7) & 0x06));
 532         }
 533         else {
 534             out_8(&iic->cntl, 0);
 535             out_8(&iic->lmadr, addr << 1);
 536         }
 537 }
 538
 539 static inline int iic_invalid_address(const struct i2c_msg* p)
 540 {
 541         return (p->addr > 0x3ff) || (!(p->flags & I2C_M_TEN) && (p->addr > 0x7f));
 542 }
 543
 544 static inline int iic_address_neq(const struct i2c_msg* p1,
 545                                   const struct i2c_msg* p2)
 546 {
 547         return (p1->addr != p2->addr)
 548                 || ((p1->flags & I2C_M_TEN) != (p2->flags & I2C_M_TEN));
 549 }
 550
 551 /*
 552  * Generic master transfer entrypoint.
 553  * Returns the number of processed messages or error (<0)
 554  */
 555 static int iic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 556 {
 557         struct ibm_iic_private* dev = (struct ibm_iic_private*)(i2c_get_adapdata(adap));
 558         volatile struct iic_regs __iomem *iic = dev->vaddr;
 559         int i, ret = 0;
 560
 561         DBG2("%d: iic_xfer, %d msg(s)\n", dev->idx, num);
 562
 563         if (!num)
 564                 return 0;
 565
 566         /* Check the sanity of the passed messages.
 567          * Uhh, generic i2c layer is more suitable place for such code...
 568          */
 569         if (unlikely(iic_invalid_address(&msgs[0]))){
 570                 DBG("%d: invalid address 0x%03x (%d-bit)\n", dev->idx,
 571                         msgs[0].addr, msgs[0].flags & I2C_M_TEN ? 10 : 7);
 572                 return -EINVAL;
 573         }
 574         for (i = 0; i < num; ++i){
 575                 if (unlikely(msgs[i].len <= 0)){
 576                         if (num == 1 && !msgs[0].len){
 577                                 /* Special case for I2C_SMBUS_QUICK emulation.
 578                                  * IBM IIC doesn't support 0-length transactions
 579                                  * so we have to emulate them using bit-banging.
 580                                  */
 581                                 return iic_smbus_quick(dev, &msgs[0]);
 582                         }
 583                         DBG("%d: invalid len %d in msg[%d]\n", dev->idx,
 584                                 msgs[i].len, i);
 585                         return -EINVAL;
 586                 }
 587                 if (unlikely(iic_address_neq(&msgs[0], &msgs[i]))){
 588                         DBG("%d: invalid addr in msg[%d]\n", dev->idx, i);
 589                         return -EINVAL;
 590                 }
 591         }
 592
 593         /* Check bus state */
 594         if (unlikely((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE)){
 595                 DBG("%d: iic_xfer, bus is not free\n", dev->idx);
 596
 597                 /* Usually it means something serious has happend.
 598                  * We *cannot* have unfinished previous transfer
 599                  * so it doesn't make any sense to try to stop it.
 600                  * Probably we were not able to recover from the
 601                  * previous error.
 602                  * The only *reasonable* thing I can think of here
 603                  * is soft reset.  --ebs
 604                  */
 605                 iic_dev_reset(dev);
 606
 607                 if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
 608                         DBG("%d: iic_xfer, bus is still not free\n", dev->idx);
 609                         return -EREMOTEIO;
 610                 }
 611         }
 612         else {
 613                 /* Flush master data buffer (just in case) */
 614                 out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
 615         }
 616
 617         /* Load slave address */
 618         iic_address(dev, &msgs[0]);
 619
 620         /* Do real transfer */
 621         for (i = 0; i < num && !ret; ++i)
 622                 ret = iic_xfer_bytes(dev, &msgs[i], i < num - 1);
 623
 624         return ret < 0 ? ret : num;
 625 }
 626
 627 static u32 iic_func(struct i2c_adapter *adap)
 628 {
 629         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
 630 }
 631
 632 static const struct i2c_algorithm iic_algo = {
 633         .master_xfer    = iic_xfer,
 634         .functionality  = iic_func
 635 };
 636
 637 /*
 638  * Calculates IICx_CLCKDIV value for a specific OPB clock frequency
 639  */
 640 static inline u8 iic_clckdiv(unsigned int opb)
 641 {
 642         /* Compatibility kludge, should go away after all cards
 643          * are fixed to fill correct value for opbfreq.
 644          * Previous driver version used hardcoded divider value 4,
 645          * it corresponds to OPB frequency from the range (40, 50] MHz
 646          */
 647         if (!opb){
 648                 printk(KERN_WARNING "ibm-iic: using compatibility value for OPB freq,"
 649                         " fix your board specific setup\n");
 650                 opb = 50000000;
 651         }
 652
 653         /* Convert to MHz */
 654         opb /= 1000000;
 655
 656         if (opb < 20 || opb > 150){
 657                 printk(KERN_WARNING "ibm-iic: invalid OPB clock frequency %u MHz\n",
 658                         opb);
 659                 opb = opb < 20 ? 20 : 150;
 660         }
 661         return (u8)((opb + 9) / 10 - 1);
 662 }
 663
 664 static int __devinit iic_request_irq(struct platform_device *ofdev,
 665                                      struct ibm_iic_private *dev)
 666 {
 667         struct device_node *np = ofdev->dev.of_node;
 668         int irq;
 669
 670         if (iic_force_poll)
 671                 return 0;
 672
 673         irq = irq_of_parse_and_map(np, 0);
 674         if (!irq) {
 675                 dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n");
 676                 return 0;
 677         }
 678
 679         /* Disable interrupts until we finish initialization, assumes
 680          *  level-sensitive IRQ setup...
 681          */
 682         iic_interrupt_mode(dev, 0);
 683         if (request_irq(irq, iic_handler, 0, "IBM IIC", dev)) {
 684                 dev_err(&ofdev->dev, "request_irq %d failed\n", irq);
 685                 /* Fallback to the polling mode */
 686                 return 0;
 687         }
 688
 689         return irq;
 690 }
 691
 692 /*
 693  * Register single IIC interface
 694  */
 695 static int __devinit iic_probe(struct platform_device *ofdev,
 696                                const struct of_device_id *match)
 697 {
 698         struct device_node *np = ofdev->dev.of_node;
 699         struct ibm_iic_private *dev;
 700         struct i2c_adapter *adap;
 701         const u32 *freq;
 702         int ret;
 703
 704         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
 705         if (!dev) {
 706                 dev_err(&ofdev->dev, "failed to allocate device data\n");
 707                 return -ENOMEM;
 708         }
 709
 710         dev_set_drvdata(&ofdev->dev, dev);
 711
 712         dev->vaddr = of_iomap(np, 0);
 713         if (dev->vaddr == NULL) {
 714                 dev_err(&ofdev->dev, "failed to iomap device\n");
 715                 ret = -ENXIO;
 716                 goto error_cleanup;
 717         }
 718
 719         init_waitqueue_head(&dev->wq);
 720
 721         dev->irq = iic_request_irq(ofdev, dev);
 722         if (!dev->irq)
 723                 dev_warn(&ofdev->dev, "using polling mode\n");
 724
 725         /* Board specific settings */
 726         if (iic_force_fast || of_get_property(np, "fast-mode", NULL))
 727                 dev->fast_mode = 1;
 728
 729         freq = of_get_property(np, "clock-frequency", NULL);
 730         if (freq == NULL) {
 731                 freq = of_get_property(np->parent, "clock-frequency", NULL);
 732                 if (freq == NULL) {
 733                         dev_err(&ofdev->dev, "Unable to get bus frequency\n");
 734                         ret = -EINVAL;
 735                         goto error_cleanup;
 736                 }
 737         }
 738
 739         dev->clckdiv = iic_clckdiv(*freq);
 740         dev_dbg(&ofdev->dev, "clckdiv = %d\n", dev->clckdiv);
 741
 742         /* Initialize IIC interface */
 743         iic_dev_init(dev);
 744
 745         /* Register it with i2c layer */
 746         adap = &dev->adap;
 747         adap->dev.parent = &ofdev->dev;
 748         adap->dev.of_node = of_node_get(np);
 749         strlcpy(adap->name, "IBM IIC", sizeof(adap->name));
 750         i2c_set_adapdata(adap, dev);
 751         adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 752         adap->algo = &iic_algo;
 753         adap->timeout = HZ;
 754
 755         ret = i2c_add_adapter(adap);
 756         if (ret  < 0) {
 757                 dev_err(&ofdev->dev, "failed to register i2c adapter\n");
 758                 goto error_cleanup;
 759         }
 760
 761         dev_info(&ofdev->dev, "using %s mode\n",
 762                  dev->fast_mode ? "fast (400 kHz)" : "standard (100 kHz)");
 763
 764         /* Now register all the child nodes */
 765         of_i2c_register_devices(adap);
 766
 767         return 0;
 768
 769 error_cleanup:
 770         if (dev->irq) {
 771                 iic_interrupt_mode(dev, 0);
 772                 free_irq(dev->irq, dev);
 773         }
 774
 775         if (dev->vaddr)
 776                 iounmap(dev->vaddr);
 777
 778         dev_set_drvdata(&ofdev->dev, NULL);
 779         kfree(dev);
 780         return ret;
 781 }
 782
 783 /*
 784  * Cleanup initialized IIC interface
 785  */
 786 static int __devexit iic_remove(struct platform_device *ofdev)
 787 {
 788         struct ibm_iic_private *dev = dev_get_drvdata(&ofdev->dev);
 789
 790         dev_set_drvdata(&ofdev->dev, NULL);
 791
 792         i2c_del_adapter(&dev->adap);
 793
 794         if (dev->irq) {
 795                 iic_interrupt_mode(dev, 0);
 796                 free_irq(dev->irq, dev);
 797         }
 798
 799         iounmap(dev->vaddr);
 800         kfree(dev);
 801
 802         return 0;
 803 }
 804
 805 static const struct of_device_id ibm_iic_match[] = {
 806         { .compatible = "ibm,iic", },
 807         {}
 808 };
 809
 810 static struct of_platform_driver ibm_iic_driver = {
 811         .driver = {
 812                 .name = "ibm-iic",
 813                 .owner = THIS_MODULE,
 814                 .of_match_table = ibm_iic_match,
 815         },
 816         .probe  = iic_probe,
 817         .remove = __devexit_p(iic_remove),
 818 };
 819
 820 static int __init iic_init(void)
 821 {
 822         return of_register_platform_driver(&ibm_iic_driver);
 823 }
 824
 825 static void __exit iic_exit(void)
 826 {
 827         of_unregister_platform_driver(&ibm_iic_driver);
 828 }
 829
 830 module_init(iic_init);
 831 module_exit(iic_exit);