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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / gpu / drm / radeon / rs600.c
blob9e5606b9b6eb25cda4e076aa2406a3135f09550f
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 /* RS600 / Radeon X1250/X1270 integrated GPU
29 *
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
37 */
38 #include "drmP.h"
39 #include "radeon.h"
40 #include "radeon_asic.h"
41 #include "atom.h"
42 #include "rs600d.h"
43
44 #include "rs600_reg_safe.h"
45
46 void rs600_gpu_init(struct radeon_device *rdev);
47 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
48
49 void rs600_pm_misc(struct radeon_device *rdev)
50 {
51 int requested_index = rdev->pm.requested_power_state_index;
52 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
53 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
54 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
55 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
56
57 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
58 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
59 tmp = RREG32(voltage->gpio.reg);
60 if (voltage->active_high)
61 tmp |= voltage->gpio.mask;
62 else
63 tmp &= ~(voltage->gpio.mask);
64 WREG32(voltage->gpio.reg, tmp);
65 if (voltage->delay)
66 udelay(voltage->delay);
67 } else {
68 tmp = RREG32(voltage->gpio.reg);
69 if (voltage->active_high)
70 tmp &= ~voltage->gpio.mask;
71 else
72 tmp |= voltage->gpio.mask;
73 WREG32(voltage->gpio.reg, tmp);
74 if (voltage->delay)
75 udelay(voltage->delay);
76 }
77 } else if (voltage->type == VOLTAGE_VDDC)
78 radeon_atom_set_voltage(rdev, voltage->vddc_id);
79
80 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
81 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
82 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
83 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
84 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
85 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
86 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
87 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
88 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
89 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
90 }
91 } else {
92 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
93 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
94 }
95 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
96
97 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
98 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
99 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
100 if (voltage->delay) {
101 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
102 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
103 } else
104 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
105 } else
106 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
107 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
108
109 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
110 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
111 hdp_dyn_cntl &= ~HDP_FORCEON;
112 else
113 hdp_dyn_cntl |= HDP_FORCEON;
114 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
115 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
116 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
117 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
118 else
119 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
120 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
121
122 /* set pcie lanes */
123 if ((rdev->flags & RADEON_IS_PCIE) &&
124 !(rdev->flags & RADEON_IS_IGP) &&
125 rdev->asic->set_pcie_lanes &&
126 (ps->pcie_lanes !=
127 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
128 radeon_set_pcie_lanes(rdev,
129 ps->pcie_lanes);
130 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
131 }
132 }
133
134 void rs600_pm_prepare(struct radeon_device *rdev)
135 {
136 struct drm_device *ddev = rdev->ddev;
137 struct drm_crtc *crtc;
138 struct radeon_crtc *radeon_crtc;
139 u32 tmp;
140
141 /* disable any active CRTCs */
142 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
143 radeon_crtc = to_radeon_crtc(crtc);
144 if (radeon_crtc->enabled) {
145 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
146 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
147 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
148 }
149 }
150 }
151
152 void rs600_pm_finish(struct radeon_device *rdev)
153 {
154 struct drm_device *ddev = rdev->ddev;
155 struct drm_crtc *crtc;
156 struct radeon_crtc *radeon_crtc;
157 u32 tmp;
158
159 /* enable any active CRTCs */
160 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
161 radeon_crtc = to_radeon_crtc(crtc);
162 if (radeon_crtc->enabled) {
163 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
164 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
165 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
166 }
167 }
168 }
169
170 /* hpd for digital panel detect/disconnect */
171 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
172 {
173 u32 tmp;
174 bool connected = false;
175
176 switch (hpd) {
177 case RADEON_HPD_1:
178 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
179 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
180 connected = true;
181 break;
182 case RADEON_HPD_2:
183 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
184 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
185 connected = true;
186 break;
187 default:
188 break;
189 }
190 return connected;
191 }
192
193 void rs600_hpd_set_polarity(struct radeon_device *rdev,
194 enum radeon_hpd_id hpd)
195 {
196 u32 tmp;
197 bool connected = rs600_hpd_sense(rdev, hpd);
198
199 switch (hpd) {
200 case RADEON_HPD_1:
201 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
202 if (connected)
203 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
204 else
205 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
206 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
207 break;
208 case RADEON_HPD_2:
209 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
210 if (connected)
211 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
212 else
213 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
214 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
215 break;
216 default:
217 break;
218 }
219 }
220
221 void rs600_hpd_init(struct radeon_device *rdev)
222 {
223 struct drm_device *dev = rdev->ddev;
224 struct drm_connector *connector;
225
226 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
227 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
228 switch (radeon_connector->hpd.hpd) {
229 case RADEON_HPD_1:
230 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
231 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
232 rdev->irq.hpd[0] = true;
233 break;
234 case RADEON_HPD_2:
235 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
236 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
237 rdev->irq.hpd[1] = true;
238 break;
239 default:
240 break;
241 }
242 }
243 if (rdev->irq.installed)
244 rs600_irq_set(rdev);
245 }
246
247 void rs600_hpd_fini(struct radeon_device *rdev)
248 {
249 struct drm_device *dev = rdev->ddev;
250 struct drm_connector *connector;
251
252 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
253 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
254 switch (radeon_connector->hpd.hpd) {
255 case RADEON_HPD_1:
256 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
257 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
258 rdev->irq.hpd[0] = false;
259 break;
260 case RADEON_HPD_2:
261 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
262 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
263 rdev->irq.hpd[1] = false;
264 break;
265 default:
266 break;
267 }
268 }
269 }
270
271 void rs600_bm_disable(struct radeon_device *rdev)
272 {
273 u32 tmp;
274
275 /* disable bus mastering */
276 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
277 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
278 mdelay(1);
279 }
280
281 int rs600_asic_reset(struct radeon_device *rdev)
282 {
283 u32 status, tmp;
284
285 struct rv515_mc_save save;
286
287 /* Stops all mc clients */
288 rv515_mc_stop(rdev, &save);
289 status = RREG32(R_000E40_RBBM_STATUS);
290 if (!G_000E40_GUI_ACTIVE(status)) {
291 return 0;
292 }
293 status = RREG32(R_000E40_RBBM_STATUS);
294 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
295 /* stop CP */
296 WREG32(RADEON_CP_CSQ_CNTL, 0);
297 tmp = RREG32(RADEON_CP_RB_CNTL);
298 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
299 WREG32(RADEON_CP_RB_RPTR_WR, 0);
300 WREG32(RADEON_CP_RB_WPTR, 0);
301 WREG32(RADEON_CP_RB_CNTL, tmp);
302 pci_save_state(rdev->pdev);
303 /* disable bus mastering */
304 rs600_bm_disable(rdev);
305 /* reset GA+VAP */
306 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
307 S_0000F0_SOFT_RESET_GA(1));
308 RREG32(R_0000F0_RBBM_SOFT_RESET);
309 mdelay(500);
310 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
311 mdelay(1);
312 status = RREG32(R_000E40_RBBM_STATUS);
313 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
314 /* reset CP */
315 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
316 RREG32(R_0000F0_RBBM_SOFT_RESET);
317 mdelay(500);
318 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
319 mdelay(1);
320 status = RREG32(R_000E40_RBBM_STATUS);
321 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
322 /* reset MC */
323 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
324 RREG32(R_0000F0_RBBM_SOFT_RESET);
325 mdelay(500);
326 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
327 mdelay(1);
328 status = RREG32(R_000E40_RBBM_STATUS);
329 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
330 /* restore PCI & busmastering */
331 pci_restore_state(rdev->pdev);
332 /* Check if GPU is idle */
333 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
334 dev_err(rdev->dev, "failed to reset GPU\n");
335 rdev->gpu_lockup = true;
336 return -1;
337 }
338 rv515_mc_resume(rdev, &save);
339 dev_info(rdev->dev, "GPU reset succeed\n");
340 return 0;
341 }
342
343 /*
344 * GART.
345 */
346 void rs600_gart_tlb_flush(struct radeon_device *rdev)
347 {
348 uint32_t tmp;
349
350 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
351 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
352 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
353
354 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
355 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
356 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
357
358 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
359 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
360 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
361 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
362 }
363
364 int rs600_gart_init(struct radeon_device *rdev)
365 {
366 int r;
367
368 if (rdev->gart.table.vram.robj) {
369 WARN(1, "RS600 GART already initialized.\n");
370 return 0;
371 }
372 /* Initialize common gart structure */
373 r = radeon_gart_init(rdev);
374 if (r) {
375 return r;
376 }
377 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
378 return radeon_gart_table_vram_alloc(rdev);
379 }
380
381 int rs600_gart_enable(struct radeon_device *rdev)
382 {
383 u32 tmp;
384 int r, i;
385
386 if (rdev->gart.table.vram.robj == NULL) {
387 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
388 return -EINVAL;
389 }
390 r = radeon_gart_table_vram_pin(rdev);
391 if (r)
392 return r;
393 radeon_gart_restore(rdev);
394 /* Enable bus master */
395 tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
396 WREG32(R_00004C_BUS_CNTL, tmp);
397 WREG32_MC(R_000100_MC_PT0_CNTL,
398 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
399 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
400
401 for (i = 0; i < 19; i++) {
402 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
403 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
404 S_00016C_SYSTEM_ACCESS_MODE_MASK(
405 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
406 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
407 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
408 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
409 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
410 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
411 }
412 /* enable first context */
413 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
414 S_000102_ENABLE_PAGE_TABLE(1) |
415 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
416
417 /* disable all other contexts */
418 for (i = 1; i < 8; i++)
419 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
420
421 /* setup the page table */
422 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
423 rdev->gart.table_addr);
424 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
425 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
426 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
427
428 /* System context maps to VRAM space */
429 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
430 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
431
432 /* enable page tables */
433 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
434 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
435 tmp = RREG32_MC(R_000009_MC_CNTL1);
436 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
437 rs600_gart_tlb_flush(rdev);
438 rdev->gart.ready = true;
439 return 0;
440 }
441
442 void rs600_gart_disable(struct radeon_device *rdev)
443 {
444 u32 tmp;
445 int r;
446
447 WREG32_MC(R_000100_MC_PT0_CNTL, 0);
448 tmp = RREG32_MC(R_000009_MC_CNTL1);
449 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
450 if (rdev->gart.table.vram.robj) {
451 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
452 if (r == 0) {
453 radeon_bo_kunmap(rdev->gart.table.vram.robj);
454 radeon_bo_unpin(rdev->gart.table.vram.robj);
455 radeon_bo_unreserve(rdev->gart.table.vram.robj);
456 }
457 }
458 }
459
460 void rs600_gart_fini(struct radeon_device *rdev)
461 {
462 radeon_gart_fini(rdev);
463 rs600_gart_disable(rdev);
464 radeon_gart_table_vram_free(rdev);
465 }
466
467 #define R600_PTE_VALID (1 << 0)
468 #define R600_PTE_SYSTEM (1 << 1)
469 #define R600_PTE_SNOOPED (1 << 2)
470 #define R600_PTE_READABLE (1 << 5)
471 #define R600_PTE_WRITEABLE (1 << 6)
472
473 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
474 {
475 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
476
477 if (i < 0 || i > rdev->gart.num_gpu_pages) {
478 return -EINVAL;
479 }
480 addr = addr & 0xFFFFFFFFFFFFF000ULL;
481 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
482 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
483 writeq(addr, ((void __iomem *)ptr) + (i * 8));
484 return 0;
485 }
486
487 int rs600_irq_set(struct radeon_device *rdev)
488 {
489 uint32_t tmp = 0;
490 uint32_t mode_int = 0;
491 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
492 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
493 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
494 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
495
496 if (!rdev->irq.installed) {
497 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
498 WREG32(R_000040_GEN_INT_CNTL, 0);
499 return -EINVAL;
500 }
501 if (rdev->irq.sw_int) {
502 tmp |= S_000040_SW_INT_EN(1);
503 }
504 if (rdev->irq.gui_idle) {
505 tmp |= S_000040_GUI_IDLE(1);
506 }
507 if (rdev->irq.crtc_vblank_int[0]) {
508 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
509 }
510 if (rdev->irq.crtc_vblank_int[1]) {
511 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
512 }
513 if (rdev->irq.hpd[0]) {
514 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
515 }
516 if (rdev->irq.hpd[1]) {
517 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
518 }
519 WREG32(R_000040_GEN_INT_CNTL, tmp);
520 WREG32(R_006540_DxMODE_INT_MASK, mode_int);
521 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
522 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
523 return 0;
524 }
525
526 static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
527 {
528 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
529 uint32_t irq_mask = S_000044_SW_INT(1);
530 u32 tmp;
531
532 /* the interrupt works, but the status bit is permanently asserted */
533 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
534 if (!rdev->irq.gui_idle_acked)
535 irq_mask |= S_000044_GUI_IDLE_STAT(1);
536 }
537
538 if (G_000044_DISPLAY_INT_STAT(irqs)) {
539 *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
540 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
541 WREG32(R_006534_D1MODE_VBLANK_STATUS,
542 S_006534_D1MODE_VBLANK_ACK(1));
543 }
544 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
545 WREG32(R_006D34_D2MODE_VBLANK_STATUS,
546 S_006D34_D2MODE_VBLANK_ACK(1));
547 }
548 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) {
549 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
550 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
551 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
552 }
553 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) {
554 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
555 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
556 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
557 }
558 } else {
559 *r500_disp_int = 0;
560 }
561
562 if (irqs) {
563 WREG32(R_000044_GEN_INT_STATUS, irqs);
564 }
565 return irqs & irq_mask;
566 }
567
568 void rs600_irq_disable(struct radeon_device *rdev)
569 {
570 u32 tmp;
571
572 WREG32(R_000040_GEN_INT_CNTL, 0);
573 WREG32(R_006540_DxMODE_INT_MASK, 0);
574 /* Wait and acknowledge irq */
575 mdelay(1);
576 rs600_irq_ack(rdev, &tmp);
577 }
578
579 int rs600_irq_process(struct radeon_device *rdev)
580 {
581 uint32_t status, msi_rearm;
582 uint32_t r500_disp_int;
583 bool queue_hotplug = false;
584
585 /* reset gui idle ack. the status bit is broken */
586 rdev->irq.gui_idle_acked = false;
587
588 status = rs600_irq_ack(rdev, &r500_disp_int);
589 if (!status && !r500_disp_int) {
590 return IRQ_NONE;
591 }
592 while (status || r500_disp_int) {
593 /* SW interrupt */
594 if (G_000044_SW_INT(status))
595 radeon_fence_process(rdev);
596 /* GUI idle */
597 if (G_000040_GUI_IDLE(status)) {
598 rdev->irq.gui_idle_acked = true;
599 rdev->pm.gui_idle = true;
600 wake_up(&rdev->irq.idle_queue);
601 }
602 /* Vertical blank interrupts */
603 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) {
604 drm_handle_vblank(rdev->ddev, 0);
605 rdev->pm.vblank_sync = true;
606 wake_up(&rdev->irq.vblank_queue);
607 }
608 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) {
609 drm_handle_vblank(rdev->ddev, 1);
610 rdev->pm.vblank_sync = true;
611 wake_up(&rdev->irq.vblank_queue);
612 }
613 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) {
614 queue_hotplug = true;
615 DRM_DEBUG("HPD1\n");
616 }
617 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int)) {
618 queue_hotplug = true;
619 DRM_DEBUG("HPD2\n");
620 }
621 status = rs600_irq_ack(rdev, &r500_disp_int);
622 }
623 /* reset gui idle ack. the status bit is broken */
624 rdev->irq.gui_idle_acked = false;
625 if (queue_hotplug)
626 queue_work(rdev->wq, &rdev->hotplug_work);
627 if (rdev->msi_enabled) {
628 switch (rdev->family) {
629 case CHIP_RS600:
630 case CHIP_RS690:
631 case CHIP_RS740:
632 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
633 WREG32(RADEON_BUS_CNTL, msi_rearm);
634 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
635 break;
636 default:
637 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
638 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
639 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
640 break;
641 }
642 }
643 return IRQ_HANDLED;
644 }
645
646 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
647 {
648 if (crtc == 0)
649 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
650 else
651 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
652 }
653
654 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
655 {
656 unsigned i;
657
658 for (i = 0; i < rdev->usec_timeout; i++) {
659 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
660 return 0;
661 udelay(1);
662 }
663 return -1;
664 }
665
666 void rs600_gpu_init(struct radeon_device *rdev)
667 {
668 r420_pipes_init(rdev);
669 /* Wait for mc idle */
670 if (rs600_mc_wait_for_idle(rdev))
671 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
672 }
673
674 void rs600_mc_init(struct radeon_device *rdev)
675 {
676 u64 base;
677
678 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
679 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
680 rdev->mc.vram_is_ddr = true;
681 rdev->mc.vram_width = 128;
682 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
683 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
684 rdev->mc.visible_vram_size = rdev->mc.aper_size;
685 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
686 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
687 base = RREG32_MC(R_000004_MC_FB_LOCATION);
688 base = G_000004_MC_FB_START(base) << 16;
689 radeon_vram_location(rdev, &rdev->mc, base);
690 rdev->mc.gtt_base_align = 0;
691 radeon_gtt_location(rdev, &rdev->mc);
692 radeon_update_bandwidth_info(rdev);
693 }
694
695 void rs600_bandwidth_update(struct radeon_device *rdev)
696 {
697 struct drm_display_mode *mode0 = NULL;
698 struct drm_display_mode *mode1 = NULL;
699 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
700
701 radeon_update_display_priority(rdev);
702
703 if (rdev->mode_info.crtcs[0]->base.enabled)
704 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
705 if (rdev->mode_info.crtcs[1]->base.enabled)
706 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
707
708 rs690_line_buffer_adjust(rdev, mode0, mode1);
709
710 if (rdev->disp_priority == 2) {
711 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
712 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
713 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
714 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
715 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
716 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
717 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
718 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
719 }
720 }
721
722 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
723 {
724 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
725 S_000070_MC_IND_CITF_ARB0(1));
726 return RREG32(R_000074_MC_IND_DATA);
727 }
728
729 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
730 {
731 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
732 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
733 WREG32(R_000074_MC_IND_DATA, v);
734 }
735
736 void rs600_debugfs(struct radeon_device *rdev)
737 {
738 if (r100_debugfs_rbbm_init(rdev))
739 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
740 }
741
742 void rs600_set_safe_registers(struct radeon_device *rdev)
743 {
744 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
745 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
746 }
747
748 static void rs600_mc_program(struct radeon_device *rdev)
749 {
750 struct rv515_mc_save save;
751
752 /* Stops all mc clients */
753 rv515_mc_stop(rdev, &save);
754
755 /* Wait for mc idle */
756 if (rs600_mc_wait_for_idle(rdev))
757 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
758
759 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
760 WREG32_MC(R_000006_AGP_BASE, 0);
761 WREG32_MC(R_000007_AGP_BASE_2, 0);
762 /* Program MC */
763 WREG32_MC(R_000004_MC_FB_LOCATION,
764 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
765 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
766 WREG32(R_000134_HDP_FB_LOCATION,
767 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
768
769 rv515_mc_resume(rdev, &save);
770 }
771
772 static int rs600_startup(struct radeon_device *rdev)
773 {
774 int r;
775
776 rs600_mc_program(rdev);
777 /* Resume clock */
778 rv515_clock_startup(rdev);
779 /* Initialize GPU configuration (# pipes, ...) */
780 rs600_gpu_init(rdev);
781 /* Initialize GART (initialize after TTM so we can allocate
782 * memory through TTM but finalize after TTM) */
783 r = rs600_gart_enable(rdev);
784 if (r)
785 return r;
786 /* Enable IRQ */
787 rs600_irq_set(rdev);
788 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
789 /* 1M ring buffer */
790 r = r100_cp_init(rdev, 1024 * 1024);
791 if (r) {
792 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
793 return r;
794 }
795 r = r100_wb_init(rdev);
796 if (r)
797 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
798 r = r100_ib_init(rdev);
799 if (r) {
800 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
801 return r;
802 }
803
804 r = r600_audio_init(rdev);
805 if (r) {
806 dev_err(rdev->dev, "failed initializing audio\n");
807 return r;
808 }
809
810 return 0;
811 }
812
813 int rs600_resume(struct radeon_device *rdev)
814 {
815 /* Make sur GART are not working */
816 rs600_gart_disable(rdev);
817 /* Resume clock before doing reset */
818 rv515_clock_startup(rdev);
819 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
820 if (radeon_asic_reset(rdev)) {
821 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
822 RREG32(R_000E40_RBBM_STATUS),
823 RREG32(R_0007C0_CP_STAT));
824 }
825 /* post */
826 atom_asic_init(rdev->mode_info.atom_context);
827 /* Resume clock after posting */
828 rv515_clock_startup(rdev);
829 /* Initialize surface registers */
830 radeon_surface_init(rdev);
831 return rs600_startup(rdev);
832 }
833
834 int rs600_suspend(struct radeon_device *rdev)
835 {
836 r600_audio_fini(rdev);
837 r100_cp_disable(rdev);
838 r100_wb_disable(rdev);
839 rs600_irq_disable(rdev);
840 rs600_gart_disable(rdev);
841 return 0;
842 }
843
844 void rs600_fini(struct radeon_device *rdev)
845 {
846 r600_audio_fini(rdev);
847 r100_cp_fini(rdev);
848 r100_wb_fini(rdev);
849 r100_ib_fini(rdev);
850 radeon_gem_fini(rdev);
851 rs600_gart_fini(rdev);
852 radeon_irq_kms_fini(rdev);
853 radeon_fence_driver_fini(rdev);
854 radeon_bo_fini(rdev);
855 radeon_atombios_fini(rdev);
856 kfree(rdev->bios);
857 rdev->bios = NULL;
858 }
859
860 int rs600_init(struct radeon_device *rdev)
861 {
862 int r;
863
864 /* Disable VGA */
865 rv515_vga_render_disable(rdev);
866 /* Initialize scratch registers */
867 radeon_scratch_init(rdev);
868 /* Initialize surface registers */
869 radeon_surface_init(rdev);
870 /* restore some register to sane defaults */
871 r100_restore_sanity(rdev);
872 /* BIOS */
873 if (!radeon_get_bios(rdev)) {
874 if (ASIC_IS_AVIVO(rdev))
875 return -EINVAL;
876 }
877 if (rdev->is_atom_bios) {
878 r = radeon_atombios_init(rdev);
879 if (r)
880 return r;
881 } else {
882 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
883 return -EINVAL;
884 }
885 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
886 if (radeon_asic_reset(rdev)) {
887 dev_warn(rdev->dev,
888 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
889 RREG32(R_000E40_RBBM_STATUS),
890 RREG32(R_0007C0_CP_STAT));
891 }
892 /* check if cards are posted or not */
893 if (radeon_boot_test_post_card(rdev) == false)
894 return -EINVAL;
895
896 /* Initialize clocks */
897 radeon_get_clock_info(rdev->ddev);
898 /* initialize memory controller */
899 rs600_mc_init(rdev);
900 rs600_debugfs(rdev);
901 /* Fence driver */
902 r = radeon_fence_driver_init(rdev);
903 if (r)
904 return r;
905 r = radeon_irq_kms_init(rdev);
906 if (r)
907 return r;
908 /* Memory manager */
909 r = radeon_bo_init(rdev);
910 if (r)
911 return r;
912 r = rs600_gart_init(rdev);
913 if (r)
914 return r;
915 rs600_set_safe_registers(rdev);
916 rdev->accel_working = true;
917 r = rs600_startup(rdev);
918 if (r) {
919 /* Somethings want wront with the accel init stop accel */
920 dev_err(rdev->dev, "Disabling GPU acceleration\n");
921 r100_cp_fini(rdev);
922 r100_wb_fini(rdev);
923 r100_ib_fini(rdev);
924 rs600_gart_fini(rdev);
925 radeon_irq_kms_fini(rdev);
926 rdev->accel_working = false;
927 }
928 return 0;
929 }
Tomato firmware and modifications.