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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / gpu / drm / radeon / radeon_legacy_tv.c
blob21f7b6d2e4e4a307303537ab7b0ec69e9de518c2
1 #include "drmP.h"
2 #include "drm_crtc_helper.h"
3 #include "radeon.h"
4
5 /*
6 * Integrated TV out support based on the GATOS code by
7 * Federico Ulivi <fulivi@lycos.com>
8 */
9
10
11 /*
12 * Limits of h/v positions (hPos & vPos)
13 */
14 #define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */
15 #define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */
16
17 /*
18 * Unit for hPos (in TV clock periods)
19 */
20 #define H_POS_UNIT 10
21
22 /*
23 * Indexes in h. code timing table for horizontal line position adjustment
24 */
25 #define H_TABLE_POS1 6
26 #define H_TABLE_POS2 8
27
28 /*
29 * Limits of hor. size (hSize)
30 */
31 #define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */
32
33 /* tv standard constants */
34 #define NTSC_TV_CLOCK_T 233
35 #define NTSC_TV_VFTOTAL 1
36 #define NTSC_TV_LINES_PER_FRAME 525
37 #define NTSC_TV_ZERO_H_SIZE 479166
38 #define NTSC_TV_H_SIZE_UNIT 9478
39
40 #define PAL_TV_CLOCK_T 188
41 #define PAL_TV_VFTOTAL 3
42 #define PAL_TV_LINES_PER_FRAME 625
43 #define PAL_TV_ZERO_H_SIZE 473200
44 #define PAL_TV_H_SIZE_UNIT 9360
45
46 /* tv pll setting for 27 mhz ref clk */
47 #define NTSC_TV_PLL_M_27 22
48 #define NTSC_TV_PLL_N_27 175
49 #define NTSC_TV_PLL_P_27 5
50
51 #define PAL_TV_PLL_M_27 113
52 #define PAL_TV_PLL_N_27 668
53 #define PAL_TV_PLL_P_27 3
54
55 /* tv pll setting for 14 mhz ref clk */
56 #define NTSC_TV_PLL_M_14 33
57 #define NTSC_TV_PLL_N_14 693
58 #define NTSC_TV_PLL_P_14 7
59
60 #define PAL_TV_PLL_M_14 19
61 #define PAL_TV_PLL_N_14 353
62 #define PAL_TV_PLL_P_14 5
63
64 #define VERT_LEAD_IN_LINES 2
65 #define FRAC_BITS 0xe
66 #define FRAC_MASK 0x3fff
67
68 struct radeon_tv_mode_constants {
69 uint16_t hor_resolution;
70 uint16_t ver_resolution;
71 enum radeon_tv_std standard;
72 uint16_t hor_total;
73 uint16_t ver_total;
74 uint16_t hor_start;
75 uint16_t hor_syncstart;
76 uint16_t ver_syncstart;
77 unsigned def_restart;
78 uint16_t crtcPLL_N;
79 uint8_t crtcPLL_M;
80 uint8_t crtcPLL_post_div;
81 unsigned pix_to_tv;
82 };
83
84 static const uint16_t hor_timing_NTSC[MAX_H_CODE_TIMING_LEN] = {
85 0x0007,
86 0x003f,
87 0x0263,
88 0x0a24,
89 0x2a6b,
90 0x0a36,
91 0x126d, /* H_TABLE_POS1 */
92 0x1bfe,
93 0x1a8f, /* H_TABLE_POS2 */
94 0x1ec7,
95 0x3863,
96 0x1bfe,
97 0x1bfe,
98 0x1a2a,
99 0x1e95,
100 0x0e31,
101 0x201b,
102 0
103 };
104
105 static const uint16_t vert_timing_NTSC[MAX_V_CODE_TIMING_LEN] = {
106 0x2001,
107 0x200d,
108 0x1006,
109 0x0c06,
110 0x1006,
111 0x1818,
112 0x21e3,
113 0x1006,
114 0x0c06,
115 0x1006,
116 0x1817,
117 0x21d4,
118 0x0002,
119 0
120 };
121
122 static const uint16_t hor_timing_PAL[MAX_H_CODE_TIMING_LEN] = {
123 0x0007,
124 0x0058,
125 0x027c,
126 0x0a31,
127 0x2a77,
128 0x0a95,
129 0x124f, /* H_TABLE_POS1 */
130 0x1bfe,
131 0x1b22, /* H_TABLE_POS2 */
132 0x1ef9,
133 0x387c,
134 0x1bfe,
135 0x1bfe,
136 0x1b31,
137 0x1eb5,
138 0x0e43,
139 0x201b,
140 0
141 };
142
143 static const uint16_t vert_timing_PAL[MAX_V_CODE_TIMING_LEN] = {
144 0x2001,
145 0x200c,
146 0x1005,
147 0x0c05,
148 0x1005,
149 0x1401,
150 0x1821,
151 0x2240,
152 0x1005,
153 0x0c05,
154 0x1005,
155 0x1401,
156 0x1822,
157 0x2230,
158 0x0002,
159 0
160 };
161
162 /**********************************************************************
163 *
164 * availableModes
165 *
166 * Table of all allowed modes for tv output
167 *
168 **********************************************************************/
169 static const struct radeon_tv_mode_constants available_tv_modes[] = {
170 { /* NTSC timing for 27 Mhz ref clk */
171 800, /* horResolution */
172 600, /* verResolution */
173 TV_STD_NTSC, /* standard */
174 990, /* horTotal */
175 740, /* verTotal */
176 813, /* horStart */
177 824, /* horSyncStart */
178 632, /* verSyncStart */
179 625592, /* defRestart */
180 592, /* crtcPLL_N */
181 91, /* crtcPLL_M */
182 4, /* crtcPLL_postDiv */
183 1022, /* pixToTV */
184 },
185 { /* PAL timing for 27 Mhz ref clk */
186 800, /* horResolution */
187 600, /* verResolution */
188 TV_STD_PAL, /* standard */
189 1144, /* horTotal */
190 706, /* verTotal */
191 812, /* horStart */
192 824, /* horSyncStart */
193 669, /* verSyncStart */
194 696700, /* defRestart */
195 1382, /* crtcPLL_N */
196 231, /* crtcPLL_M */
197 4, /* crtcPLL_postDiv */
198 759, /* pixToTV */
199 },
200 { /* NTSC timing for 14 Mhz ref clk */
201 800, /* horResolution */
202 600, /* verResolution */
203 TV_STD_NTSC, /* standard */
204 1018, /* horTotal */
205 727, /* verTotal */
206 813, /* horStart */
207 840, /* horSyncStart */
208 633, /* verSyncStart */
209 630627, /* defRestart */
210 347, /* crtcPLL_N */
211 14, /* crtcPLL_M */
212 8, /* crtcPLL_postDiv */
213 1022, /* pixToTV */
214 },
215 { /* PAL timing for 14 Mhz ref clk */
216 800, /* horResolution */
217 600, /* verResolution */
218 TV_STD_PAL, /* standard */
219 1131, /* horTotal */
220 742, /* verTotal */
221 813, /* horStart */
222 840, /* horSyncStart */
223 633, /* verSyncStart */
224 708369, /* defRestart */
225 211, /* crtcPLL_N */
226 9, /* crtcPLL_M */
227 8, /* crtcPLL_postDiv */
228 759, /* pixToTV */
229 },
230 };
231
232 #define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes)
233
234 static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(struct radeon_encoder *radeon_encoder,
235 uint16_t *pll_ref_freq)
236 {
237 struct drm_device *dev = radeon_encoder->base.dev;
238 struct radeon_device *rdev = dev->dev_private;
239 struct radeon_crtc *radeon_crtc;
240 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
241 const struct radeon_tv_mode_constants *const_ptr;
242 struct radeon_pll *pll;
243
244 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc);
245 if (radeon_crtc->crtc_id == 1)
246 pll = &rdev->clock.p2pll;
247 else
248 pll = &rdev->clock.p1pll;
249
250 if (pll_ref_freq)
251 *pll_ref_freq = pll->reference_freq;
252
253 if (tv_dac->tv_std == TV_STD_NTSC ||
254 tv_dac->tv_std == TV_STD_NTSC_J ||
255 tv_dac->tv_std == TV_STD_PAL_M) {
256 if (pll->reference_freq == 2700)
257 const_ptr = &available_tv_modes[0];
258 else
259 const_ptr = &available_tv_modes[2];
260 } else {
261 if (pll->reference_freq == 2700)
262 const_ptr = &available_tv_modes[1];
263 else
264 const_ptr = &available_tv_modes[3];
265 }
266 return const_ptr;
267 }
268
269 static long YCOEF_value[5] = { 2, 2, 0, 4, 0 };
270 static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 };
271 static long SLOPE_value[5] = { 1, 2, 2, 4, 8 };
272 static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 };
273
274 static void radeon_wait_pll_lock(struct drm_encoder *encoder, unsigned n_tests,
275 unsigned n_wait_loops, unsigned cnt_threshold)
276 {
277 struct drm_device *dev = encoder->dev;
278 struct radeon_device *rdev = dev->dev_private;
279 uint32_t save_pll_test;
280 unsigned int i, j;
281
282 WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100);
283 save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL);
284 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B);
285
286 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL);
287 for (i = 0; i < n_tests; i++) {
288 WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0);
289 for (j = 0; j < n_wait_loops; j++)
290 if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold)
291 break;
292 }
293 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test);
294 WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff);
295 }
296
297
298 static void radeon_legacy_tv_write_fifo(struct radeon_encoder *radeon_encoder,
299 uint16_t addr, uint32_t value)
300 {
301 struct drm_device *dev = radeon_encoder->base.dev;
302 struct radeon_device *rdev = dev->dev_private;
303 uint32_t tmp;
304 int i = 0;
305
306 WREG32(RADEON_TV_HOST_WRITE_DATA, value);
307
308 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);
309 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT);
310
311 do {
312 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
313 if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0)
314 break;
315 i++;
316 } while (i < 10000);
317 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);
318 }
319
320
321 static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr)
322 {
323 uint16_t h_table;
324
325 switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) {
326 case 0:
327 h_table = RADEON_TV_MAX_FIFO_ADDR_INTERNAL;
328 break;
329 case 1:
330 h_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2;
331 break;
332 case 2:
333 h_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2;
334 break;
335 default:
336 h_table = 0;
337 break;
338 }
339 return h_table;
340 }
341
342 static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr)
343 {
344 uint16_t v_table;
345
346 switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) {
347 case 0:
348 v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1;
349 break;
350 case 1:
351 v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1;
352 break;
353 case 2:
354 v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1;
355 break;
356 default:
357 v_table = 0;
358 break;
359 }
360 return v_table;
361 }
362
363 static void radeon_restore_tv_timing_tables(struct radeon_encoder *radeon_encoder)
364 {
365 struct drm_device *dev = radeon_encoder->base.dev;
366 struct radeon_device *rdev = dev->dev_private;
367 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
368 uint16_t h_table, v_table;
369 uint32_t tmp;
370 int i;
371
372 WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr);
373 h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr);
374 v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr);
375
376 for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, h_table--) {
377 tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]);
378 radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp);
379 if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0)
380 break;
381 }
382 for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, v_table++) {
383 tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]);
384 radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp);
385 if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0)
386 break;
387 }
388 }
389
390 static void radeon_legacy_write_tv_restarts(struct radeon_encoder *radeon_encoder)
391 {
392 struct drm_device *dev = radeon_encoder->base.dev;
393 struct radeon_device *rdev = dev->dev_private;
394 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
395 WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart);
396 WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart);
397 WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart);
398 }
399
400 static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder)
401 {
402 struct drm_device *dev = encoder->dev;
403 struct radeon_device *rdev = dev->dev_private;
404 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
405 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
406 struct radeon_crtc *radeon_crtc;
407 int restart;
408 unsigned int h_total, v_total, f_total;
409 int v_offset, h_offset;
410 u16 p1, p2, h_inc;
411 bool h_changed;
412 const struct radeon_tv_mode_constants *const_ptr;
413 struct radeon_pll *pll;
414
415 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc);
416 if (radeon_crtc->crtc_id == 1)
417 pll = &rdev->clock.p2pll;
418 else
419 pll = &rdev->clock.p1pll;
420
421 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
422 if (!const_ptr)
423 return false;
424
425 h_total = const_ptr->hor_total;
426 v_total = const_ptr->ver_total;
427
428 if (tv_dac->tv_std == TV_STD_NTSC ||
429 tv_dac->tv_std == TV_STD_NTSC_J ||
430 tv_dac->tv_std == TV_STD_PAL_M ||
431 tv_dac->tv_std == TV_STD_PAL_60)
432 f_total = NTSC_TV_VFTOTAL + 1;
433 else
434 f_total = PAL_TV_VFTOTAL + 1;
435
436 /* adjust positions 1&2 in hor. cod timing table */
437 h_offset = tv_dac->h_pos * H_POS_UNIT;
438
439 if (tv_dac->tv_std == TV_STD_NTSC ||
440 tv_dac->tv_std == TV_STD_NTSC_J ||
441 tv_dac->tv_std == TV_STD_PAL_M) {
442 h_offset -= 50;
443 p1 = hor_timing_NTSC[H_TABLE_POS1];
444 p2 = hor_timing_NTSC[H_TABLE_POS2];
445 } else {
446 p1 = hor_timing_PAL[H_TABLE_POS1];
447 p2 = hor_timing_PAL[H_TABLE_POS2];
448 }
449
450 p1 = (u16)((int)p1 + h_offset);
451 p2 = (u16)((int)p2 - h_offset);
452
453 h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] ||
454 p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]);
455
456 tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1;
457 tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2;
458
459 /* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */
460 h_offset = (h_offset * (int)(const_ptr->pix_to_tv)) / 1000;
461
462 /* adjust restart */
463 restart = const_ptr->def_restart;
464
465 /*
466 * convert v_pos TV lines to n. of CRTC pixels
467 */
468 if (tv_dac->tv_std == TV_STD_NTSC ||
469 tv_dac->tv_std == TV_STD_NTSC_J ||
470 tv_dac->tv_std == TV_STD_PAL_M ||
471 tv_dac->tv_std == TV_STD_PAL_60)
472 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME);
473 else
474 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME);
475
476 restart -= v_offset + h_offset;
477
478 DRM_DEBUG_KMS("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n",
479 const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart);
480
481 tv_dac->tv.hrestart = restart % h_total;
482 restart /= h_total;
483 tv_dac->tv.vrestart = restart % v_total;
484 restart /= v_total;
485 tv_dac->tv.frestart = restart % f_total;
486
487 DRM_DEBUG_KMS("compute_restart: F/H/V=%u,%u,%u\n",
488 (unsigned)tv_dac->tv.frestart,
489 (unsigned)tv_dac->tv.vrestart,
490 (unsigned)tv_dac->tv.hrestart);
491
492 /* compute h_inc from hsize */
493 if (tv_dac->tv_std == TV_STD_NTSC ||
494 tv_dac->tv_std == TV_STD_NTSC_J ||
495 tv_dac->tv_std == TV_STD_PAL_M)
496 h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * NTSC_TV_CLOCK_T) /
497 (tv_dac->h_size * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE)));
498 else
499 h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * PAL_TV_CLOCK_T) /
500 (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE)));
501
502 tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) |
503 ((u32)h_inc << RADEON_H_INC_SHIFT);
504
505 DRM_DEBUG_KMS("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc);
506
507 return h_changed;
508 }
509
510 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
511 struct drm_display_mode *mode,
512 struct drm_display_mode *adjusted_mode)
513 {
514 struct drm_device *dev = encoder->dev;
515 struct radeon_device *rdev = dev->dev_private;
516 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
517 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
518 const struct radeon_tv_mode_constants *const_ptr;
519 struct radeon_crtc *radeon_crtc;
520 int i;
521 uint16_t pll_ref_freq;
522 uint32_t vert_space, flicker_removal, tmp;
523 uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl;
524 uint32_t tv_modulator_cntl1, tv_modulator_cntl2;
525 uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2;
526 uint32_t tv_pll_cntl, tv_pll_cntl1, tv_ftotal;
527 uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl;
528 uint32_t m, n, p;
529 const uint16_t *hor_timing;
530 const uint16_t *vert_timing;
531
532 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, &pll_ref_freq);
533 if (!const_ptr)
534 return;
535
536 radeon_crtc = to_radeon_crtc(encoder->crtc);
537
538 tv_master_cntl = (RADEON_VIN_ASYNC_RST |
539 RADEON_CRT_FIFO_CE_EN |
540 RADEON_TV_FIFO_CE_EN |
541 RADEON_TV_ON);
542
543 if (!ASIC_IS_R300(rdev))
544 tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb;
545
546 if (tv_dac->tv_std == TV_STD_NTSC ||
547 tv_dac->tv_std == TV_STD_NTSC_J)
548 tv_master_cntl |= RADEON_RESTART_PHASE_FIX;
549
550 tv_modulator_cntl1 = (RADEON_SLEW_RATE_LIMIT |
551 RADEON_SYNC_TIP_LEVEL |
552 RADEON_YFLT_EN |
553 RADEON_UVFLT_EN |
554 (6 << RADEON_CY_FILT_BLEND_SHIFT));
555
556 if (tv_dac->tv_std == TV_STD_NTSC ||
557 tv_dac->tv_std == TV_STD_NTSC_J) {
558 tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT) |
559 (0x3b << RADEON_BLANK_LEVEL_SHIFT);
560 tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) |
561 ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
562 } else if (tv_dac->tv_std == TV_STD_SCART_PAL) {
563 tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN;
564 tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) |
565 ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
566 } else {
567 tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN |
568 (0x3b << RADEON_SET_UP_LEVEL_SHIFT) |
569 (0x3b << RADEON_BLANK_LEVEL_SHIFT);
570 tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) |
571 ((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
572 }
573
574
575 tv_rgb_cntl = (RADEON_RGB_DITHER_EN
576 | RADEON_TVOUT_SCALE_EN
577 | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT)
578 | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT)
579 | RADEON_RGB_ATTEN_SEL(0x3)
580 | RADEON_RGB_ATTEN_VAL(0xc));
581
582 if (radeon_crtc->crtc_id == 1)
583 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC2;
584 else {
585 if (radeon_crtc->rmx_type != RMX_OFF)
586 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_RMX;
587 else
588 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC1;
589 }
590
591 if (tv_dac->tv_std == TV_STD_NTSC ||
592 tv_dac->tv_std == TV_STD_NTSC_J ||
593 tv_dac->tv_std == TV_STD_PAL_M ||
594 tv_dac->tv_std == TV_STD_PAL_60)
595 vert_space = const_ptr->ver_total * 2 * 10000 / NTSC_TV_LINES_PER_FRAME;
596 else
597 vert_space = const_ptr->ver_total * 2 * 10000 / PAL_TV_LINES_PER_FRAME;
598
599 tmp = RREG32(RADEON_TV_VSCALER_CNTL1);
600 tmp &= 0xe3ff0000;
601 tmp |= (vert_space * (1 << FRAC_BITS) / 10000);
602 tv_vscaler_cntl1 = tmp;
603
604 if (pll_ref_freq == 2700)
605 tv_vscaler_cntl1 |= RADEON_RESTART_FIELD;
606
607 if (const_ptr->hor_resolution == 1024)
608 tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT);
609 else
610 tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT);
611
612 /* scale up for int divide */
613 tmp = const_ptr->ver_total * 2 * 1000;
614 if (tv_dac->tv_std == TV_STD_NTSC ||
615 tv_dac->tv_std == TV_STD_NTSC_J ||
616 tv_dac->tv_std == TV_STD_PAL_M ||
617 tv_dac->tv_std == TV_STD_PAL_60) {
618 tmp /= NTSC_TV_LINES_PER_FRAME;
619 } else {
620 tmp /= PAL_TV_LINES_PER_FRAME;
621 }
622 flicker_removal = (tmp + 500) / 1000;
623
624 if (flicker_removal < 3)
625 flicker_removal = 3;
626 for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) {
627 if (flicker_removal == SLOPE_limit[i])
628 break;
629 }
630
631 tv_y_saw_tooth_cntl = (vert_space * SLOPE_value[i] * (1 << (FRAC_BITS - 1)) +
632 5001) / 10000 / 8 | ((SLOPE_value[i] *
633 (1 << (FRAC_BITS - 1)) / 8) << 16);
634 tv_y_fall_cntl =
635 (YCOEF_EN_value[i] << 17) | ((YCOEF_value[i] * (1 << 8) / 8) << 24) |
636 RADEON_Y_FALL_PING_PONG | (272 * SLOPE_value[i] / 8) * (1 << (FRAC_BITS - 1)) /
637 1024;
638 tv_y_rise_cntl = RADEON_Y_RISE_PING_PONG|
639 (flicker_removal * 1024 - 272) * SLOPE_value[i] / 8 * (1 << (FRAC_BITS - 1)) / 1024;
640
641 tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0;
642 tv_vscaler_cntl2 |= (0x10 << 24) |
643 RADEON_DITHER_MODE |
644 RADEON_Y_OUTPUT_DITHER_EN |
645 RADEON_UV_OUTPUT_DITHER_EN |
646 RADEON_UV_TO_BUF_DITHER_EN;
647
648 tmp = (tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK;
649 tmp = ((16384 * 256 * 10) / tmp + 5) / 10;
650 tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000;
651 tv_dac->tv.timing_cntl = tmp;
652
653 if (tv_dac->tv_std == TV_STD_NTSC ||
654 tv_dac->tv_std == TV_STD_NTSC_J ||
655 tv_dac->tv_std == TV_STD_PAL_M ||
656 tv_dac->tv_std == TV_STD_PAL_60)
657 tv_dac_cntl = tv_dac->ntsc_tvdac_adj;
658 else
659 tv_dac_cntl = tv_dac->pal_tvdac_adj;
660
661 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
662
663 if (tv_dac->tv_std == TV_STD_NTSC ||
664 tv_dac->tv_std == TV_STD_NTSC_J)
665 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
666 else
667 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
668
669 if (tv_dac->tv_std == TV_STD_NTSC ||
670 tv_dac->tv_std == TV_STD_NTSC_J) {
671 if (pll_ref_freq == 2700) {
672 m = NTSC_TV_PLL_M_27;
673 n = NTSC_TV_PLL_N_27;
674 p = NTSC_TV_PLL_P_27;
675 } else {
676 m = NTSC_TV_PLL_M_14;
677 n = NTSC_TV_PLL_N_14;
678 p = NTSC_TV_PLL_P_14;
679 }
680 } else {
681 if (pll_ref_freq == 2700) {
682 m = PAL_TV_PLL_M_27;
683 n = PAL_TV_PLL_N_27;
684 p = PAL_TV_PLL_P_27;
685 } else {
686 m = PAL_TV_PLL_M_14;
687 n = PAL_TV_PLL_N_14;
688 p = PAL_TV_PLL_P_14;
689 }
690 }
691
692 tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) |
693 (((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) |
694 ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) |
695 (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) |
696 ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT);
697
698 tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK) << RADEON_TVPCP_SHIFT) |
699 ((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) |
700 ((1 & RADEON_TVPDC_MASK) << RADEON_TVPDC_SHIFT) |
701 RADEON_TVCLK_SRC_SEL_TVPLL |
702 RADEON_TVPLL_TEST_DIS);
703
704 tv_dac->tv.tv_uv_adr = 0xc8;
705
706 if (tv_dac->tv_std == TV_STD_NTSC ||
707 tv_dac->tv_std == TV_STD_NTSC_J ||
708 tv_dac->tv_std == TV_STD_PAL_M ||
709 tv_dac->tv_std == TV_STD_PAL_60) {
710 tv_ftotal = NTSC_TV_VFTOTAL;
711 hor_timing = hor_timing_NTSC;
712 vert_timing = vert_timing_NTSC;
713 } else {
714 hor_timing = hor_timing_PAL;
715 vert_timing = vert_timing_PAL;
716 tv_ftotal = PAL_TV_VFTOTAL;
717 }
718
719 for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) {
720 if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0)
721 break;
722 }
723
724 for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) {
725 if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0)
726 break;
727 }
728
729 radeon_legacy_tv_init_restarts(encoder);
730
731 /* play with DAC_CNTL */
732 /* play with GPIOPAD_A */
733 /* DISP_OUTPUT_CNTL */
734 /* use reference freq */
735
736 /* program the TV registers */
737 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST |
738 RADEON_CRT_ASYNC_RST | RADEON_TV_FIFO_ASYNC_RST));
739
740 tmp = RREG32(RADEON_TV_DAC_CNTL);
741 tmp &= ~RADEON_TV_DAC_NBLANK;
742 tmp |= RADEON_TV_DAC_BGSLEEP |
743 RADEON_TV_DAC_RDACPD |
744 RADEON_TV_DAC_GDACPD |
745 RADEON_TV_DAC_BDACPD;
746 WREG32(RADEON_TV_DAC_CNTL, tmp);
747
748 /* TV PLL */
749 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL);
750 WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl);
751 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET);
752
753 radeon_wait_pll_lock(encoder, 200, 800, 135);
754
755 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET);
756
757 radeon_wait_pll_lock(encoder, 300, 160, 27);
758 radeon_wait_pll_lock(encoder, 200, 800, 135);
759
760 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf);
761 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL);
762
763 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK);
764 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP);
765
766 /* TV HV */
767 WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl);
768 WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1);
769 WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1);
770 WREG32(RADEON_TV_HSTART, const_ptr->hor_start);
771
772 WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1);
773 WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1);
774 WREG32(RADEON_TV_FTOTAL, tv_ftotal);
775 WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1);
776 WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2);
777
778 WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl);
779 WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl);
780 WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl);
781
782 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST |
783 RADEON_CRT_ASYNC_RST));
784
785 /* TV restarts */
786 radeon_legacy_write_tv_restarts(radeon_encoder);
787
788 /* tv timings */
789 radeon_restore_tv_timing_tables(radeon_encoder);
790
791 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST));
792
793 /* tv std */
794 WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE));
795 WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl);
796 WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1);
797 WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2);
798 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN |
799 RADEON_C_GRN_EN |
800 RADEON_CMP_BLU_EN |
801 RADEON_DAC_DITHER_EN));
802
803 WREG32(RADEON_TV_CRC_CNTL, 0);
804
805 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
806
807 WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) |
808 (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT)));
809 WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) |
810 (0x100 << RADEON_Y_GAIN_SHIFT)));
811
812 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
813
814 }
815
816 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
817 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
818 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid)
819 {
820 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
821 const struct radeon_tv_mode_constants *const_ptr;
822 uint32_t tmp;
823
824 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
825 if (!const_ptr)
826 return;
827
828 *h_total_disp = (((const_ptr->hor_resolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
829 (((const_ptr->hor_total / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT);
830
831 tmp = *h_sync_strt_wid;
832 tmp &= ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR);
833 tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) |
834 (const_ptr->hor_syncstart & 7);
835 *h_sync_strt_wid = tmp;
836
837 *v_total_disp = ((const_ptr->ver_resolution - 1) << RADEON_CRTC_V_DISP_SHIFT) |
838 ((const_ptr->ver_total - 1) << RADEON_CRTC_V_TOTAL_SHIFT);
839
840 tmp = *v_sync_strt_wid;
841 tmp &= ~RADEON_CRTC_V_SYNC_STRT;
842 tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT);
843 *v_sync_strt_wid = tmp;
844 }
845
846 static inline int get_post_div(int value)
847 {
848 int post_div;
849 switch (value) {
850 case 1: post_div = 0; break;
851 case 2: post_div = 1; break;
852 case 3: post_div = 4; break;
853 case 4: post_div = 2; break;
854 case 6: post_div = 6; break;
855 case 8: post_div = 3; break;
856 case 12: post_div = 7; break;
857 case 16:
858 default: post_div = 5; break;
859 }
860 return post_div;
861 }
862
863 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
864 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
865 uint32_t *ppll_div_3, uint32_t *pixclks_cntl)
866 {
867 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
868 const struct radeon_tv_mode_constants *const_ptr;
869
870 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
871 if (!const_ptr)
872 return;
873
874 *htotal_cntl = (const_ptr->hor_total & 0x7) | RADEON_HTOT_CNTL_VGA_EN;
875
876 *ppll_ref_div = const_ptr->crtcPLL_M;
877
878 *ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16);
879 *pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL);
880 *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK;
881 }
882
883 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
884 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
885 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl)
886 {
887 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
888 const struct radeon_tv_mode_constants *const_ptr;
889
890 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
891 if (!const_ptr)
892 return;
893
894 *htotal2_cntl = (const_ptr->hor_total & 0x7);
895
896 *p2pll_ref_div = const_ptr->crtcPLL_M;
897
898 *p2pll_div_0 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16);
899 *pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK;
900 *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK | RADEON_PIXCLK_TV_SRC_SEL;
901 }
Tomato firmware and modifications.