release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/gpu/drm/radeon/radeon_legacy_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
  33 {
  34         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  35         struct drm_encoder_helper_funcs *encoder_funcs;
  36
  37         encoder_funcs = encoder->helper_private;
  38         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  39         radeon_encoder->active_device = 0;
  40 }
  41
  42 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
  43 {
  44         struct drm_device *dev = encoder->dev;
  45         struct radeon_device *rdev = dev->dev_private;
  46         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  47         uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
  48         int panel_pwr_delay = 2000;
  49         bool is_mac = false;
  50         DRM_DEBUG_KMS("\n");
  51
  52         if (radeon_encoder->enc_priv) {
  53                 if (rdev->is_atom_bios) {
  54                         struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  55                         panel_pwr_delay = lvds->panel_pwr_delay;
  56                 } else {
  57                         struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  58                         panel_pwr_delay = lvds->panel_pwr_delay;
  59                 }
  60         }
  61
  62         /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
  63          * Taken from radeonfb.
  64          */
  65         if ((rdev->mode_info.connector_table == CT_IBOOK) ||
  66             (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
  67             (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
  68             (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
  69                 is_mac = true;
  70
  71         switch (mode) {
  72         case DRM_MODE_DPMS_ON:
  73                 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
  74                 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
  75                 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
  76                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  77                 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
  78                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  79                 udelay(1000);
  80
  81                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  82                 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
  83                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  84
  85                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  86                 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
  87                 if (is_mac)
  88                         lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
  89                 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
  90                 udelay(panel_pwr_delay * 1000);
  91                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  92                 break;
  93         case DRM_MODE_DPMS_STANDBY:
  94         case DRM_MODE_DPMS_SUSPEND:
  95         case DRM_MODE_DPMS_OFF:
  96                 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
  97                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
  98                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  99                 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 100                 if (is_mac) {
 101                         lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
 102                         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 103                         lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
 104                 } else {
 105                         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 106                         lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
 107                 }
 108                 udelay(panel_pwr_delay * 1000);
 109                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 110                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 111                 udelay(panel_pwr_delay * 1000);
 112                 break;
 113         }
 114
 115         if (rdev->is_atom_bios)
 116                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 117         else
 118                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 119
 120 }
 121
 122 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
 123 {
 124         struct radeon_device *rdev = encoder->dev->dev_private;
 125
 126         if (rdev->is_atom_bios)
 127                 radeon_atom_output_lock(encoder, true);
 128         else
 129                 radeon_combios_output_lock(encoder, true);
 130         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
 131 }
 132
 133 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
 134 {
 135         struct radeon_device *rdev = encoder->dev->dev_private;
 136
 137         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
 138         if (rdev->is_atom_bios)
 139                 radeon_atom_output_lock(encoder, false);
 140         else
 141                 radeon_combios_output_lock(encoder, false);
 142 }
 143
 144 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
 145                                         struct drm_display_mode *mode,
 146                                         struct drm_display_mode *adjusted_mode)
 147 {
 148         struct drm_device *dev = encoder->dev;
 149         struct radeon_device *rdev = dev->dev_private;
 150         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 151         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 152         uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
 153
 154         DRM_DEBUG_KMS("\n");
 155
 156         lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
 157         lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
 158
 159         lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
 160         if (rdev->is_atom_bios) {
 161                 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
 162                  * need to call that on resume to set up the reg properly.
 163                  */
 164                 radeon_encoder->pixel_clock = adjusted_mode->clock;
 165                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
 166                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 167         } else {
 168                 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 169                 if (lvds) {
 170                         DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
 171                         lvds_gen_cntl = lvds->lvds_gen_cntl;
 172                         lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 173                                               (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 174                         lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 175                                              (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 176                 } else
 177                         lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 178         }
 179         lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 180         lvds_gen_cntl &= ~(RADEON_LVDS_ON |
 181                            RADEON_LVDS_BLON |
 182                            RADEON_LVDS_EN |
 183                            RADEON_LVDS_RST_FM);
 184
 185         if (ASIC_IS_R300(rdev))
 186                 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
 187
 188         if (radeon_crtc->crtc_id == 0) {
 189                 if (ASIC_IS_R300(rdev)) {
 190                         if (radeon_encoder->rmx_type != RMX_OFF)
 191                                 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
 192                 } else
 193                         lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
 194         } else {
 195                 if (ASIC_IS_R300(rdev))
 196                         lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
 197                 else
 198                         lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
 199         }
 200
 201         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 202         WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 203         WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
 204
 205         if (rdev->family == CHIP_RV410)
 206                 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
 207
 208         if (rdev->is_atom_bios)
 209                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 210         else
 211                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 212 }
 213
 214 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
 215                                      struct drm_display_mode *mode,
 216                                      struct drm_display_mode *adjusted_mode)
 217 {
 218         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 219
 220         /* set the active encoder to connector routing */
 221         radeon_encoder_set_active_device(encoder);
 222         drm_mode_set_crtcinfo(adjusted_mode, 0);
 223
 224         /* get the native mode for LVDS */
 225         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
 226                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 227
 228         return true;
 229 }
 230
 231 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
 232         .dpms = radeon_legacy_lvds_dpms,
 233         .mode_fixup = radeon_legacy_mode_fixup,
 234         .prepare = radeon_legacy_lvds_prepare,
 235         .mode_set = radeon_legacy_lvds_mode_set,
 236         .commit = radeon_legacy_lvds_commit,
 237         .disable = radeon_legacy_encoder_disable,
 238 };
 239
 240
 241 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
 242         .destroy = radeon_enc_destroy,
 243 };
 244
 245 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
 246 {
 247         struct drm_device *dev = encoder->dev;
 248         struct radeon_device *rdev = dev->dev_private;
 249         uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 250         uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
 251         uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 252
 253         DRM_DEBUG_KMS("\n");
 254
 255         switch (mode) {
 256         case DRM_MODE_DPMS_ON:
 257                 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
 258                 dac_cntl &= ~RADEON_DAC_PDWN;
 259                 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
 260                                     RADEON_DAC_PDWN_G |
 261                                     RADEON_DAC_PDWN_B);
 262                 break;
 263         case DRM_MODE_DPMS_STANDBY:
 264         case DRM_MODE_DPMS_SUSPEND:
 265         case DRM_MODE_DPMS_OFF:
 266                 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
 267                 dac_cntl |= RADEON_DAC_PDWN;
 268                 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
 269                                    RADEON_DAC_PDWN_G |
 270                                    RADEON_DAC_PDWN_B);
 271                 break;
 272         }
 273
 274         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 275         WREG32(RADEON_DAC_CNTL, dac_cntl);
 276         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 277
 278         if (rdev->is_atom_bios)
 279                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 280         else
 281                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 282
 283 }
 284
 285 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
 286 {
 287         struct radeon_device *rdev = encoder->dev->dev_private;
 288
 289         if (rdev->is_atom_bios)
 290                 radeon_atom_output_lock(encoder, true);
 291         else
 292                 radeon_combios_output_lock(encoder, true);
 293         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 294 }
 295
 296 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
 297 {
 298         struct radeon_device *rdev = encoder->dev->dev_private;
 299
 300         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 301
 302         if (rdev->is_atom_bios)
 303                 radeon_atom_output_lock(encoder, false);
 304         else
 305                 radeon_combios_output_lock(encoder, false);
 306 }
 307
 308 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
 309                                                struct drm_display_mode *mode,
 310                                                struct drm_display_mode *adjusted_mode)
 311 {
 312         struct drm_device *dev = encoder->dev;
 313         struct radeon_device *rdev = dev->dev_private;
 314         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 315         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 316         uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
 317
 318         DRM_DEBUG_KMS("\n");
 319
 320         if (radeon_crtc->crtc_id == 0) {
 321                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
 322                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
 323                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 324                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 325                 } else {
 326                         dac2_cntl = RREG32(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
 327                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 328                 }
 329         } else {
 330                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
 331                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
 332                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 333                         disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
 334                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 335                 } else {
 336                         dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
 337                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 338                 }
 339         }
 340
 341         dac_cntl = (RADEON_DAC_MASK_ALL |
 342                     RADEON_DAC_VGA_ADR_EN |
 343                     /* TODO 6-bits */
 344                     RADEON_DAC_8BIT_EN);
 345
 346         WREG32_P(RADEON_DAC_CNTL,
 347                        dac_cntl,
 348                        RADEON_DAC_RANGE_CNTL |
 349                        RADEON_DAC_BLANKING);
 350
 351         if (radeon_encoder->enc_priv) {
 352                 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
 353                 dac_macro_cntl = p_dac->ps2_pdac_adj;
 354         } else
 355                 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 356         dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
 357         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 358
 359         if (rdev->is_atom_bios)
 360                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 361         else
 362                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 363 }
 364
 365 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
 366                                                                   struct drm_connector *connector)
 367 {
 368         struct drm_device *dev = encoder->dev;
 369         struct radeon_device *rdev = dev->dev_private;
 370         uint32_t vclk_ecp_cntl, crtc_ext_cntl;
 371         uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
 372         enum drm_connector_status found = connector_status_disconnected;
 373         bool color = true;
 374
 375         /* save the regs we need */
 376         vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
 377         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 378         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
 379         dac_cntl = RREG32(RADEON_DAC_CNTL);
 380         dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 381
 382         tmp = vclk_ecp_cntl &
 383                 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
 384         WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
 385
 386         tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
 387         WREG32(RADEON_CRTC_EXT_CNTL, tmp);
 388
 389         tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
 390                 RADEON_DAC_FORCE_DATA_EN;
 391
 392         if (color)
 393                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
 394         else
 395                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
 396
 397         if (ASIC_IS_R300(rdev))
 398                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
 399         else
 400                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
 401
 402         WREG32(RADEON_DAC_EXT_CNTL, tmp);
 403
 404         tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
 405         tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
 406         WREG32(RADEON_DAC_CNTL, tmp);
 407
 408         tmp &= ~(RADEON_DAC_PDWN_R |
 409                  RADEON_DAC_PDWN_G |
 410                  RADEON_DAC_PDWN_B);
 411
 412         WREG32(RADEON_DAC_MACRO_CNTL, tmp);
 413
 414         udelay(2000);
 415
 416         if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
 417                 found = connector_status_connected;
 418
 419         /* restore the regs we used */
 420         WREG32(RADEON_DAC_CNTL, dac_cntl);
 421         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 422         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
 423         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 424         WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
 425
 426         return found;
 427 }
 428
 429 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
 430         .dpms = radeon_legacy_primary_dac_dpms,
 431         .mode_fixup = radeon_legacy_mode_fixup,
 432         .prepare = radeon_legacy_primary_dac_prepare,
 433         .mode_set = radeon_legacy_primary_dac_mode_set,
 434         .commit = radeon_legacy_primary_dac_commit,
 435         .detect = radeon_legacy_primary_dac_detect,
 436         .disable = radeon_legacy_encoder_disable,
 437 };
 438
 439
 440 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
 441         .destroy = radeon_enc_destroy,
 442 };
 443
 444 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
 445 {
 446         struct drm_device *dev = encoder->dev;
 447         struct radeon_device *rdev = dev->dev_private;
 448         uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
 449         DRM_DEBUG_KMS("\n");
 450
 451         switch (mode) {
 452         case DRM_MODE_DPMS_ON:
 453                 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 454                 break;
 455         case DRM_MODE_DPMS_STANDBY:
 456         case DRM_MODE_DPMS_SUSPEND:
 457         case DRM_MODE_DPMS_OFF:
 458                 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 459                 break;
 460         }
 461
 462         WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 463
 464         if (rdev->is_atom_bios)
 465                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 466         else
 467                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 468
 469 }
 470
 471 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
 472 {
 473         struct radeon_device *rdev = encoder->dev->dev_private;
 474
 475         if (rdev->is_atom_bios)
 476                 radeon_atom_output_lock(encoder, true);
 477         else
 478                 radeon_combios_output_lock(encoder, true);
 479         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
 480 }
 481
 482 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
 483 {
 484         struct radeon_device *rdev = encoder->dev->dev_private;
 485
 486         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
 487
 488         if (rdev->is_atom_bios)
 489                 radeon_atom_output_lock(encoder, true);
 490         else
 491                 radeon_combios_output_lock(encoder, true);
 492 }
 493
 494 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
 495                                             struct drm_display_mode *mode,
 496                                             struct drm_display_mode *adjusted_mode)
 497 {
 498         struct drm_device *dev = encoder->dev;
 499         struct radeon_device *rdev = dev->dev_private;
 500         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 501         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 502         uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
 503         int i;
 504
 505         DRM_DEBUG_KMS("\n");
 506
 507         tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
 508         tmp &= 0xfffff;
 509         if (rdev->family == CHIP_RV280) {
 510                 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
 511                 tmp ^= (1 << 22);
 512                 tmds_pll_cntl ^= (1 << 22);
 513         }
 514
 515         if (radeon_encoder->enc_priv) {
 516                 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
 517
 518                 for (i = 0; i < 4; i++) {
 519                         if (tmds->tmds_pll[i].freq == 0)
 520                                 break;
 521                         if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
 522                                 tmp = tmds->tmds_pll[i].value ;
 523                                 break;
 524                         }
 525                 }
 526         }
 527
 528         if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
 529                 if (tmp & 0xfff00000)
 530                         tmds_pll_cntl = tmp;
 531                 else {
 532                         tmds_pll_cntl &= 0xfff00000;
 533                         tmds_pll_cntl |= tmp;
 534                 }
 535         } else
 536                 tmds_pll_cntl = tmp;
 537
 538         tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
 539                 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
 540
 541     if (rdev->family == CHIP_R200 ||
 542         rdev->family == CHIP_R100 ||
 543         ASIC_IS_R300(rdev))
 544             tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
 545     else /* RV chips got this bit reversed */
 546             tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
 547
 548     fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
 549                    (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
 550                     RADEON_FP_CRTC_DONT_SHADOW_HEND));
 551
 552     fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 553
 554     fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
 555                      RADEON_FP_DFP_SYNC_SEL |
 556                      RADEON_FP_CRT_SYNC_SEL |
 557                      RADEON_FP_CRTC_LOCK_8DOT |
 558                      RADEON_FP_USE_SHADOW_EN |
 559                      RADEON_FP_CRTC_USE_SHADOW_VEND |
 560                      RADEON_FP_CRT_SYNC_ALT);
 561
 562     if (1)
 563             fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
 564     else
 565             fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
 566
 567     if (radeon_crtc->crtc_id == 0) {
 568             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
 569                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 570                     if (radeon_encoder->rmx_type != RMX_OFF)
 571                             fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
 572                     else
 573                             fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
 574             } else
 575                     fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
 576     } else {
 577             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
 578                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 579                     fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
 580             } else
 581                     fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
 582     }
 583
 584     WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
 585     WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
 586     WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 587
 588         if (rdev->is_atom_bios)
 589                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 590         else
 591                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 592 }
 593
 594 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
 595         .dpms = radeon_legacy_tmds_int_dpms,
 596         .mode_fixup = radeon_legacy_mode_fixup,
 597         .prepare = radeon_legacy_tmds_int_prepare,
 598         .mode_set = radeon_legacy_tmds_int_mode_set,
 599         .commit = radeon_legacy_tmds_int_commit,
 600         .disable = radeon_legacy_encoder_disable,
 601 };
 602
 603
 604 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
 605         .destroy = radeon_enc_destroy,
 606 };
 607
 608 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
 609 {
 610         struct drm_device *dev = encoder->dev;
 611         struct radeon_device *rdev = dev->dev_private;
 612         uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 613         DRM_DEBUG_KMS("\n");
 614
 615         switch (mode) {
 616         case DRM_MODE_DPMS_ON:
 617                 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
 618                 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 619                 break;
 620         case DRM_MODE_DPMS_STANDBY:
 621         case DRM_MODE_DPMS_SUSPEND:
 622         case DRM_MODE_DPMS_OFF:
 623                 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
 624                 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 625                 break;
 626         }
 627
 628         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 629
 630         if (rdev->is_atom_bios)
 631                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 632         else
 633                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 634
 635 }
 636
 637 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
 638 {
 639         struct radeon_device *rdev = encoder->dev->dev_private;
 640
 641         if (rdev->is_atom_bios)
 642                 radeon_atom_output_lock(encoder, true);
 643         else
 644                 radeon_combios_output_lock(encoder, true);
 645         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
 646 }
 647
 648 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
 649 {
 650         struct radeon_device *rdev = encoder->dev->dev_private;
 651         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
 652
 653         if (rdev->is_atom_bios)
 654                 radeon_atom_output_lock(encoder, false);
 655         else
 656                 radeon_combios_output_lock(encoder, false);
 657 }
 658
 659 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
 660                                             struct drm_display_mode *mode,
 661                                             struct drm_display_mode *adjusted_mode)
 662 {
 663         struct drm_device *dev = encoder->dev;
 664         struct radeon_device *rdev = dev->dev_private;
 665         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 666         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 667         uint32_t fp2_gen_cntl;
 668
 669         DRM_DEBUG_KMS("\n");
 670
 671         if (rdev->is_atom_bios) {
 672                 radeon_encoder->pixel_clock = adjusted_mode->clock;
 673                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
 674                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 675         } else {
 676                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 677
 678                 if (1)
 679                         fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
 680                 else
 681                         fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
 682
 683                 fp2_gen_cntl &= ~(RADEON_FP2_ON |
 684                                   RADEON_FP2_DVO_EN |
 685                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 686
 687                 if (ASIC_IS_R300(rdev)) {
 688                         if ((dev->pdev->device == 0x4850) &&
 689                             (dev->pdev->subsystem_vendor == 0x1028) &&
 690                             (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
 691                                 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
 692                         else
 693                                 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
 694
 695                         /*if (mode->clock > 165000)
 696                           fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
 697                 }
 698                 if (!radeon_combios_external_tmds_setup(encoder))
 699                         radeon_external_tmds_setup(encoder);
 700         }
 701
 702         if (radeon_crtc->crtc_id == 0) {
 703                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
 704                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 705                         if (radeon_encoder->rmx_type != RMX_OFF)
 706                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
 707                         else
 708                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
 709                 } else
 710                         fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
 711         } else {
 712                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
 713                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 714                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 715                 } else
 716                         fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
 717         }
 718
 719         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 720
 721         if (rdev->is_atom_bios)
 722                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 723         else
 724                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 725 }
 726
 727 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
 728 {
 729         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 730         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
 731         if (tmds) {
 732                 if (tmds->i2c_bus)
 733                         radeon_i2c_destroy(tmds->i2c_bus);
 734         }
 735         kfree(radeon_encoder->enc_priv);
 736         drm_encoder_cleanup(encoder);
 737         kfree(radeon_encoder);
 738 }
 739
 740 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
 741         .dpms = radeon_legacy_tmds_ext_dpms,
 742         .mode_fixup = radeon_legacy_mode_fixup,
 743         .prepare = radeon_legacy_tmds_ext_prepare,
 744         .mode_set = radeon_legacy_tmds_ext_mode_set,
 745         .commit = radeon_legacy_tmds_ext_commit,
 746         .disable = radeon_legacy_encoder_disable,
 747 };
 748
 749
 750 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
 751         .destroy = radeon_ext_tmds_enc_destroy,
 752 };
 753
 754 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
 755 {
 756         struct drm_device *dev = encoder->dev;
 757         struct radeon_device *rdev = dev->dev_private;
 758         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 759         uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
 760         uint32_t tv_master_cntl = 0;
 761         bool is_tv;
 762         DRM_DEBUG_KMS("\n");
 763
 764         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
 765
 766         if (rdev->family == CHIP_R200)
 767                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 768         else {
 769                 if (is_tv)
 770                         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
 771                 else
 772                         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 773                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 774         }
 775
 776         switch (mode) {
 777         case DRM_MODE_DPMS_ON:
 778                 if (rdev->family == CHIP_R200) {
 779                         fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 780                 } else {
 781                         if (is_tv)
 782                                 tv_master_cntl |= RADEON_TV_ON;
 783                         else
 784                                 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
 785
 786                         if (rdev->family == CHIP_R420 ||
 787                             rdev->family == CHIP_R423 ||
 788                             rdev->family == CHIP_RV410)
 789                                 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
 790                                                  R420_TV_DAC_GDACPD |
 791                                                  R420_TV_DAC_BDACPD |
 792                                                  RADEON_TV_DAC_BGSLEEP);
 793                         else
 794                                 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
 795                                                  RADEON_TV_DAC_GDACPD |
 796                                                  RADEON_TV_DAC_BDACPD |
 797                                                  RADEON_TV_DAC_BGSLEEP);
 798                 }
 799                 break;
 800         case DRM_MODE_DPMS_STANDBY:
 801         case DRM_MODE_DPMS_SUSPEND:
 802         case DRM_MODE_DPMS_OFF:
 803                 if (rdev->family == CHIP_R200)
 804                         fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 805                 else {
 806                         if (is_tv)
 807                                 tv_master_cntl &= ~RADEON_TV_ON;
 808                         else
 809                                 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
 810
 811                         if (rdev->family == CHIP_R420 ||
 812                             rdev->family == CHIP_R423 ||
 813                             rdev->family == CHIP_RV410)
 814                                 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
 815                                                 R420_TV_DAC_GDACPD |
 816                                                 R420_TV_DAC_BDACPD |
 817                                                 RADEON_TV_DAC_BGSLEEP);
 818                         else
 819                                 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
 820                                                 RADEON_TV_DAC_GDACPD |
 821                                                 RADEON_TV_DAC_BDACPD |
 822                                                 RADEON_TV_DAC_BGSLEEP);
 823                 }
 824                 break;
 825         }
 826
 827         if (rdev->family == CHIP_R200) {
 828                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 829         } else {
 830                 if (is_tv)
 831                         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
 832                 else
 833                         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 834                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 835         }
 836
 837         if (rdev->is_atom_bios)
 838                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 839         else
 840                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 841
 842 }
 843
 844 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
 845 {
 846         struct radeon_device *rdev = encoder->dev->dev_private;
 847
 848         if (rdev->is_atom_bios)
 849                 radeon_atom_output_lock(encoder, true);
 850         else
 851                 radeon_combios_output_lock(encoder, true);
 852         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 853 }
 854
 855 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
 856 {
 857         struct radeon_device *rdev = encoder->dev->dev_private;
 858
 859         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 860
 861         if (rdev->is_atom_bios)
 862                 radeon_atom_output_lock(encoder, true);
 863         else
 864                 radeon_combios_output_lock(encoder, true);
 865 }
 866
 867 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
 868                 struct drm_display_mode *mode,
 869                 struct drm_display_mode *adjusted_mode)
 870 {
 871         struct drm_device *dev = encoder->dev;
 872         struct radeon_device *rdev = dev->dev_private;
 873         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 874         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 875         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
 876         uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
 877         uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
 878         bool is_tv = false;
 879
 880         DRM_DEBUG_KMS("\n");
 881
 882         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
 883
 884         if (rdev->family != CHIP_R200) {
 885                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 886                 if (rdev->family == CHIP_R420 ||
 887                     rdev->family == CHIP_R423 ||
 888                     rdev->family == CHIP_RV410) {
 889                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
 890                                          RADEON_TV_DAC_BGADJ_MASK |
 891                                          R420_TV_DAC_DACADJ_MASK |
 892                                          R420_TV_DAC_RDACPD |
 893                                          R420_TV_DAC_GDACPD |
 894                                          R420_TV_DAC_BDACPD |
 895                                          R420_TV_DAC_TVENABLE);
 896                 } else {
 897                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
 898                                          RADEON_TV_DAC_BGADJ_MASK |
 899                                          RADEON_TV_DAC_DACADJ_MASK |
 900                                          RADEON_TV_DAC_RDACPD |
 901                                          RADEON_TV_DAC_GDACPD |
 902                                          RADEON_TV_DAC_BDACPD);
 903                 }
 904
 905                 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
 906
 907                 if (is_tv) {
 908                         if (tv_dac->tv_std == TV_STD_NTSC ||
 909                             tv_dac->tv_std == TV_STD_NTSC_J ||
 910                             tv_dac->tv_std == TV_STD_PAL_M ||
 911                             tv_dac->tv_std == TV_STD_PAL_60)
 912                                 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
 913                         else
 914                                 tv_dac_cntl |= tv_dac->pal_tvdac_adj;
 915
 916                         if (tv_dac->tv_std == TV_STD_NTSC ||
 917                             tv_dac->tv_std == TV_STD_NTSC_J)
 918                                 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
 919                         else
 920                                 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
 921                 } else
 922                         tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
 923                                         tv_dac->ps2_tvdac_adj);
 924
 925                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 926         }
 927
 928         if (ASIC_IS_R300(rdev)) {
 929                 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
 930                 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
 931         } else if (rdev->family != CHIP_R200)
 932                 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
 933         else if (rdev->family == CHIP_R200)
 934                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 935
 936         if (rdev->family >= CHIP_R200)
 937                 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
 938
 939         if (is_tv) {
 940                 uint32_t dac_cntl;
 941
 942                 dac_cntl = RREG32(RADEON_DAC_CNTL);
 943                 dac_cntl &= ~RADEON_DAC_TVO_EN;
 944                 WREG32(RADEON_DAC_CNTL, dac_cntl);
 945
 946                 if (ASIC_IS_R300(rdev))
 947                         gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
 948
 949                 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
 950                 if (radeon_crtc->crtc_id == 0) {
 951                         if (ASIC_IS_R300(rdev)) {
 952                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 953                                 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
 954                                                      RADEON_DISP_TV_SOURCE_CRTC);
 955                         }
 956                         if (rdev->family >= CHIP_R200) {
 957                                 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
 958                         } else {
 959                                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 960                         }
 961                 } else {
 962                         if (ASIC_IS_R300(rdev)) {
 963                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 964                                 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
 965                         }
 966                         if (rdev->family >= CHIP_R200) {
 967                                 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
 968                         } else {
 969                                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
 970                         }
 971                 }
 972                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 973         } else {
 974
 975                 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
 976
 977                 if (radeon_crtc->crtc_id == 0) {
 978                         if (ASIC_IS_R300(rdev)) {
 979                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 980                                 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
 981                         } else if (rdev->family == CHIP_R200) {
 982                                 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
 983                                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 984                         } else
 985                                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 986                 } else {
 987                         if (ASIC_IS_R300(rdev)) {
 988                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 989                                 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
 990                         } else if (rdev->family == CHIP_R200) {
 991                                 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
 992                                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 993                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 994                         } else
 995                                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
 996                 }
 997                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 998         }
 999
1000         if (ASIC_IS_R300(rdev)) {
1001                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1002                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1003         } else if (rdev->family != CHIP_R200)
1004                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1005         else if (rdev->family == CHIP_R200)
1006                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1007
1008         if (rdev->family >= CHIP_R200)
1009                 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1010
1011         if (is_tv)
1012                 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1013
1014         if (rdev->is_atom_bios)
1015                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1016         else
1017                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1018
1019 }
1020
1021 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1022                                   struct drm_connector *connector)
1023 {
1024         struct drm_device *dev = encoder->dev;
1025         struct radeon_device *rdev = dev->dev_private;
1026         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1027         uint32_t disp_output_cntl, gpiopad_a, tmp;
1028         bool found = false;
1029
1030         /* save regs needed */
1031         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1032         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1033         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1034         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1035         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1036         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1037
1038         WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1039
1040         WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1041
1042         WREG32(RADEON_CRTC2_GEN_CNTL,
1043                RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1044
1045         tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1046         tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1047         WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1048
1049         WREG32(RADEON_DAC_EXT_CNTL,
1050                RADEON_DAC2_FORCE_BLANK_OFF_EN |
1051                RADEON_DAC2_FORCE_DATA_EN |
1052                RADEON_DAC_FORCE_DATA_SEL_RGB |
1053                (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1054
1055         WREG32(RADEON_TV_DAC_CNTL,
1056                RADEON_TV_DAC_STD_NTSC |
1057                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1058                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1059
1060         RREG32(RADEON_TV_DAC_CNTL);
1061         mdelay(4);
1062
1063         WREG32(RADEON_TV_DAC_CNTL,
1064                RADEON_TV_DAC_NBLANK |
1065                RADEON_TV_DAC_NHOLD |
1066                RADEON_TV_MONITOR_DETECT_EN |
1067                RADEON_TV_DAC_STD_NTSC |
1068                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1069                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1070
1071         RREG32(RADEON_TV_DAC_CNTL);
1072         mdelay(6);
1073
1074         tmp = RREG32(RADEON_TV_DAC_CNTL);
1075         if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1076                 found = true;
1077                 DRM_DEBUG_KMS("S-video TV connection detected\n");
1078         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1079                 found = true;
1080                 DRM_DEBUG_KMS("Composite TV connection detected\n");
1081         }
1082
1083         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1084         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1085         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1086         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1087         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1088         WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1089         return found;
1090 }
1091
1092 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1093                                     struct drm_connector *connector)
1094 {
1095         struct drm_device *dev = encoder->dev;
1096         struct radeon_device *rdev = dev->dev_private;
1097         uint32_t tv_dac_cntl, dac_cntl2;
1098         uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1099         bool found = false;
1100
1101         if (ASIC_IS_R300(rdev))
1102                 return r300_legacy_tv_detect(encoder, connector);
1103
1104         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1105         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1106         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1107         config_cntl = RREG32(RADEON_CONFIG_CNTL);
1108         tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1109
1110         tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1111         WREG32(RADEON_DAC_CNTL2, tmp);
1112
1113         tmp = tv_master_cntl | RADEON_TV_ON;
1114         tmp &= ~(RADEON_TV_ASYNC_RST |
1115                  RADEON_RESTART_PHASE_FIX |
1116                  RADEON_CRT_FIFO_CE_EN |
1117                  RADEON_TV_FIFO_CE_EN |
1118                  RADEON_RE_SYNC_NOW_SEL_MASK);
1119         tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1120         WREG32(RADEON_TV_MASTER_CNTL, tmp);
1121
1122         tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1123                 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1124                 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1125
1126         if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1127                 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1128         else
1129                 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1130         WREG32(RADEON_TV_DAC_CNTL, tmp);
1131
1132         tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1133                 RADEON_RED_MX_FORCE_DAC_DATA |
1134                 RADEON_GRN_MX_FORCE_DAC_DATA |
1135                 RADEON_BLU_MX_FORCE_DAC_DATA |
1136                 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1137         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1138
1139         mdelay(3);
1140         tmp = RREG32(RADEON_TV_DAC_CNTL);
1141         if (tmp & RADEON_TV_DAC_GDACDET) {
1142                 found = true;
1143                 DRM_DEBUG_KMS("S-video TV connection detected\n");
1144         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1145                 found = true;
1146                 DRM_DEBUG_KMS("Composite TV connection detected\n");
1147         }
1148
1149         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1150         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1151         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1152         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1153         return found;
1154 }
1155
1156 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1157                                                              struct drm_connector *connector)
1158 {
1159         struct drm_device *dev = encoder->dev;
1160         struct radeon_device *rdev = dev->dev_private;
1161         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1162         uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
1163         enum drm_connector_status found = connector_status_disconnected;
1164         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1165         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1166         bool color = true;
1167         struct drm_crtc *crtc;
1168
1169         /* find out if crtc2 is in use or if this encoder is using it */
1170         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1171                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1172                 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1173                         if (encoder->crtc != crtc) {
1174                                 return connector_status_disconnected;
1175                         }
1176                 }
1177         }
1178
1179         if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1180             connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1181             connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1182                 bool tv_detect;
1183
1184                 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1185                         return connector_status_disconnected;
1186
1187                 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1188                 if (tv_detect && tv_dac)
1189                         found = connector_status_connected;
1190                 return found;
1191         }
1192
1193         /* don't probe if the encoder is being used for something else not CRT related */
1194         if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1195                 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1196                 return connector_status_disconnected;
1197         }
1198
1199         /* save the regs we need */
1200         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1201         gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
1202         disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
1203         disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
1204         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1205         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1206         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1207         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1208
1209         tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1210                                | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1211         WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1212
1213         if (ASIC_IS_R300(rdev))
1214                 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1215
1216         tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1217         tmp |= RADEON_CRTC2_CRT2_ON |
1218                 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1219
1220         WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1221
1222         if (ASIC_IS_R300(rdev)) {
1223                 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1224                 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1225                 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1226         } else {
1227                 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1228                 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1229         }
1230
1231         tmp = RADEON_TV_DAC_NBLANK |
1232                 RADEON_TV_DAC_NHOLD |
1233                 RADEON_TV_MONITOR_DETECT_EN |
1234                 RADEON_TV_DAC_STD_PS2;
1235
1236         WREG32(RADEON_TV_DAC_CNTL, tmp);
1237
1238         tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1239                 RADEON_DAC2_FORCE_DATA_EN;
1240
1241         if (color)
1242                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1243         else
1244                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1245
1246         if (ASIC_IS_R300(rdev))
1247                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1248         else
1249                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1250
1251         WREG32(RADEON_DAC_EXT_CNTL, tmp);
1252
1253         tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1254         WREG32(RADEON_DAC_CNTL2, tmp);
1255
1256         udelay(10000);
1257
1258         if (ASIC_IS_R300(rdev)) {
1259                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1260                         found = connector_status_connected;
1261         } else {
1262                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1263                         found = connector_status_connected;
1264         }
1265
1266         /* restore regs we used */
1267         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1268         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1269         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1270         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1271
1272         if (ASIC_IS_R300(rdev)) {
1273                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1274                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1275         } else {
1276                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1277         }
1278         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1279
1280         return found;
1281
1282 }
1283
1284 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1285         .dpms = radeon_legacy_tv_dac_dpms,
1286         .mode_fixup = radeon_legacy_mode_fixup,
1287         .prepare = radeon_legacy_tv_dac_prepare,
1288         .mode_set = radeon_legacy_tv_dac_mode_set,
1289         .commit = radeon_legacy_tv_dac_commit,
1290         .detect = radeon_legacy_tv_dac_detect,
1291         .disable = radeon_legacy_encoder_disable,
1292 };
1293
1294
1295 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1296         .destroy = radeon_enc_destroy,
1297 };
1298
1299
1300 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1301 {
1302         struct drm_device *dev = encoder->base.dev;
1303         struct radeon_device *rdev = dev->dev_private;
1304         struct radeon_encoder_int_tmds *tmds = NULL;
1305         bool ret;
1306
1307         tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1308
1309         if (!tmds)
1310                 return NULL;
1311
1312         if (rdev->is_atom_bios)
1313                 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1314         else
1315                 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1316
1317         if (ret == false)
1318                 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1319
1320         return tmds;
1321 }
1322
1323 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1324 {
1325         struct drm_device *dev = encoder->base.dev;
1326         struct radeon_device *rdev = dev->dev_private;
1327         struct radeon_encoder_ext_tmds *tmds = NULL;
1328         bool ret;
1329
1330         if (rdev->is_atom_bios)
1331                 return NULL;
1332
1333         tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1334
1335         if (!tmds)
1336                 return NULL;
1337
1338         ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1339
1340         if (ret == false)
1341                 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1342
1343         return tmds;
1344 }
1345
1346 void
1347 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1348 {
1349         struct radeon_device *rdev = dev->dev_private;
1350         struct drm_encoder *encoder;
1351         struct radeon_encoder *radeon_encoder;
1352
1353         /* see if we already added it */
1354         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1355                 radeon_encoder = to_radeon_encoder(encoder);
1356                 if (radeon_encoder->encoder_enum == encoder_enum) {
1357                         radeon_encoder->devices |= supported_device;
1358                         return;
1359                 }
1360
1361         }
1362
1363         /* add a new one */
1364         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1365         if (!radeon_encoder)
1366                 return;
1367
1368         encoder = &radeon_encoder->base;
1369         if (rdev->flags & RADEON_SINGLE_CRTC)
1370                 encoder->possible_crtcs = 0x1;
1371         else
1372                 encoder->possible_crtcs = 0x3;
1373
1374         radeon_encoder->enc_priv = NULL;
1375
1376         radeon_encoder->encoder_enum = encoder_enum;
1377         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1378         radeon_encoder->devices = supported_device;
1379         radeon_encoder->rmx_type = RMX_OFF;
1380
1381         switch (radeon_encoder->encoder_id) {
1382         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1383                 encoder->possible_crtcs = 0x1;
1384                 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1385                 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1386                 if (rdev->is_atom_bios)
1387                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1388                 else
1389                         radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1390                 radeon_encoder->rmx_type = RMX_FULL;
1391                 break;
1392         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1393                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1394                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1395                 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1396                 break;
1397         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1398                 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
1399                 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1400                 if (rdev->is_atom_bios)
1401                         radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1402                 else
1403                         radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1404                 break;
1405         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1406                 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1407                 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1408                 if (rdev->is_atom_bios)
1409                         radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1410                 else
1411                         radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1412                 break;
1413         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1414                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
1415                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1416                 if (!rdev->is_atom_bios)
1417                         radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1418                 break;
1419         }
1420 }