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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / gpu / drm / radeon / radeon_cp.c
blobb14879fc27975b9aa6e2fd05ef84b7ab9433e08e
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "drm_sarea.h"
35 #include "radeon_drm.h"
36 #include "radeon_drv.h"
37 #include "r300_reg.h"
38
39 #define RADEON_FIFO_DEBUG 0
40
41 /* Firmware Names */
42 #define FIRMWARE_R100 "radeon/R100_cp.bin"
43 #define FIRMWARE_R200 "radeon/R200_cp.bin"
44 #define FIRMWARE_R300 "radeon/R300_cp.bin"
45 #define FIRMWARE_R420 "radeon/R420_cp.bin"
46 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
47 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
48 #define FIRMWARE_R520 "radeon/R520_cp.bin"
49
50 MODULE_FIRMWARE(FIRMWARE_R100);
51 MODULE_FIRMWARE(FIRMWARE_R200);
52 MODULE_FIRMWARE(FIRMWARE_R300);
53 MODULE_FIRMWARE(FIRMWARE_R420);
54 MODULE_FIRMWARE(FIRMWARE_RS690);
55 MODULE_FIRMWARE(FIRMWARE_RS600);
56 MODULE_FIRMWARE(FIRMWARE_R520);
57
58 static int radeon_do_cleanup_cp(struct drm_device * dev);
59 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
60
61 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
62 {
63 u32 val;
64
65 if (dev_priv->flags & RADEON_IS_AGP) {
66 val = DRM_READ32(dev_priv->ring_rptr, off);
67 } else {
68 val = *(((volatile u32 *)
69 dev_priv->ring_rptr->handle) +
70 (off / sizeof(u32)));
71 val = le32_to_cpu(val);
72 }
73 return val;
74 }
75
76 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
77 {
78 if (dev_priv->writeback_works)
79 return radeon_read_ring_rptr(dev_priv, 0);
80 else {
81 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
82 return RADEON_READ(R600_CP_RB_RPTR);
83 else
84 return RADEON_READ(RADEON_CP_RB_RPTR);
85 }
86 }
87
88 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
89 {
90 if (dev_priv->flags & RADEON_IS_AGP)
91 DRM_WRITE32(dev_priv->ring_rptr, off, val);
92 else
93 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
94 (off / sizeof(u32))) = cpu_to_le32(val);
95 }
96
97 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
98 {
99 radeon_write_ring_rptr(dev_priv, 0, val);
100 }
101
102 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
103 {
104 if (dev_priv->writeback_works) {
105 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
106 return radeon_read_ring_rptr(dev_priv,
107 R600_SCRATCHOFF(index));
108 else
109 return radeon_read_ring_rptr(dev_priv,
110 RADEON_SCRATCHOFF(index));
111 } else {
112 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
113 return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
114 else
115 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
116 }
117 }
118
119 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
120 {
121 u32 ret;
122
123 if (addr < 0x10000)
124 ret = DRM_READ32(dev_priv->mmio, addr);
125 else {
126 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
127 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
128 }
129
130 return ret;
131 }
132
133 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
134 {
135 u32 ret;
136 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
137 ret = RADEON_READ(R520_MC_IND_DATA);
138 RADEON_WRITE(R520_MC_IND_INDEX, 0);
139 return ret;
140 }
141
142 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
143 {
144 u32 ret;
145 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
146 ret = RADEON_READ(RS480_NB_MC_DATA);
147 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
148 return ret;
149 }
150
151 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
152 {
153 u32 ret;
154 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
155 ret = RADEON_READ(RS690_MC_DATA);
156 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
157 return ret;
158 }
159
160 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
161 {
162 u32 ret;
163 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
164 RS600_MC_IND_CITF_ARB0));
165 ret = RADEON_READ(RS600_MC_DATA);
166 return ret;
167 }
168
169 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
170 {
171 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
172 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
173 return RS690_READ_MCIND(dev_priv, addr);
174 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
175 return RS600_READ_MCIND(dev_priv, addr);
176 else
177 return RS480_READ_MCIND(dev_priv, addr);
178 }
179
180 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
181 {
182
183 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
184 return RADEON_READ(R700_MC_VM_FB_LOCATION);
185 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
186 return RADEON_READ(R600_MC_VM_FB_LOCATION);
187 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
188 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
189 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
190 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
191 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
192 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
193 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
194 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
195 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
196 else
197 return RADEON_READ(RADEON_MC_FB_LOCATION);
198 }
199
200 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
201 {
202 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
203 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
204 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
205 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
206 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
207 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
208 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
209 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
210 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
211 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
212 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
213 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
214 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
215 else
216 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
217 }
218
219 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
220 {
221 /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
222 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
223 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
224 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
225 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
226 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
227 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
228 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
229 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
230 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
231 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
232 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
233 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
234 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
235 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
236 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
237 else
238 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
239 }
240
241 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
242 {
243 u32 agp_base_hi = upper_32_bits(agp_base);
244 u32 agp_base_lo = agp_base & 0xffffffff;
245 u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
246
247 /* R6xx/R7xx must be aligned to a 4MB boundry */
248 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
249 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
250 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
251 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
252 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
253 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
254 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
255 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
256 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
257 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
258 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
259 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
260 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
261 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
262 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
263 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
264 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
265 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
266 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
267 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
268 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
269 } else {
270 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
271 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
272 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
273 }
274 }
275
276 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
277 {
278 u32 tmp;
279 /* Turn on bus mastering */
280 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
281 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
282 /* rs600/rs690/rs740 */
283 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
284 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
285 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
286 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
287 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
288 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
289 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
290 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
291 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
292 } /* PCIE cards appears to not need this */
293 }
294
295 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
296 {
297 drm_radeon_private_t *dev_priv = dev->dev_private;
298
299 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
300 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
301 }
302
303 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
304 {
305 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
306 return RADEON_READ(RADEON_PCIE_DATA);
307 }
308
309 #if RADEON_FIFO_DEBUG
310 static void radeon_status(drm_radeon_private_t * dev_priv)
311 {
312 printk("%s:\n", __func__);
313 printk("RBBM_STATUS = 0x%08x\n",
314 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
315 printk("CP_RB_RTPR = 0x%08x\n",
316 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
317 printk("CP_RB_WTPR = 0x%08x\n",
318 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
319 printk("AIC_CNTL = 0x%08x\n",
320 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
321 printk("AIC_STAT = 0x%08x\n",
322 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
323 printk("AIC_PT_BASE = 0x%08x\n",
324 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
325 printk("TLB_ADDR = 0x%08x\n",
326 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
327 printk("TLB_DATA = 0x%08x\n",
328 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
329 }
330 #endif
331
332 /* ================================================================
333 * Engine, FIFO control
334 */
335
336 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
337 {
338 u32 tmp;
339 int i;
340
341 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
342
343 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
344 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
345 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
346 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
347
348 for (i = 0; i < dev_priv->usec_timeout; i++) {
349 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
350 & RADEON_RB3D_DC_BUSY)) {
351 return 0;
352 }
353 DRM_UDELAY(1);
354 }
355 } else {
356 /* don't flush or purge cache here or lockup */
357 return 0;
358 }
359
360 #if RADEON_FIFO_DEBUG
361 DRM_ERROR("failed!\n");
362 radeon_status(dev_priv);
363 #endif
364 return -EBUSY;
365 }
366
367 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
368 {
369 int i;
370
371 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
372
373 for (i = 0; i < dev_priv->usec_timeout; i++) {
374 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
375 & RADEON_RBBM_FIFOCNT_MASK);
376 if (slots >= entries)
377 return 0;
378 DRM_UDELAY(1);
379 }
380 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
381 RADEON_READ(RADEON_RBBM_STATUS),
382 RADEON_READ(R300_VAP_CNTL_STATUS));
383
384 #if RADEON_FIFO_DEBUG
385 DRM_ERROR("failed!\n");
386 radeon_status(dev_priv);
387 #endif
388 return -EBUSY;
389 }
390
391 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
392 {
393 int i, ret;
394
395 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
396
397 ret = radeon_do_wait_for_fifo(dev_priv, 64);
398 if (ret)
399 return ret;
400
401 for (i = 0; i < dev_priv->usec_timeout; i++) {
402 if (!(RADEON_READ(RADEON_RBBM_STATUS)
403 & RADEON_RBBM_ACTIVE)) {
404 radeon_do_pixcache_flush(dev_priv);
405 return 0;
406 }
407 DRM_UDELAY(1);
408 }
409 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
410 RADEON_READ(RADEON_RBBM_STATUS),
411 RADEON_READ(R300_VAP_CNTL_STATUS));
412
413 #if RADEON_FIFO_DEBUG
414 DRM_ERROR("failed!\n");
415 radeon_status(dev_priv);
416 #endif
417 return -EBUSY;
418 }
419
420 static void radeon_init_pipes(struct drm_device *dev)
421 {
422 drm_radeon_private_t *dev_priv = dev->dev_private;
423 uint32_t gb_tile_config, gb_pipe_sel = 0;
424
425 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
426 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
427 if ((z_pipe_sel & 3) == 3)
428 dev_priv->num_z_pipes = 2;
429 else
430 dev_priv->num_z_pipes = 1;
431 } else
432 dev_priv->num_z_pipes = 1;
433
434 /* RS4xx/RS6xx/R4xx/R5xx */
435 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
436 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
437 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
438 /* SE cards have 1 pipe */
439 if ((dev->pdev->device == 0x5e4c) ||
440 (dev->pdev->device == 0x5e4f))
441 dev_priv->num_gb_pipes = 1;
442 } else {
443 /* R3xx */
444 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
445 dev->pdev->device != 0x4144) ||
446 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350 &&
447 dev->pdev->device != 0x4148)) {
448 dev_priv->num_gb_pipes = 2;
449 } else {
450 /* RV3xx/R300 AD/R350 AH */
451 dev_priv->num_gb_pipes = 1;
452 }
453 }
454 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
455
456 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
457
458 switch (dev_priv->num_gb_pipes) {
459 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
460 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
461 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
462 default:
463 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
464 }
465
466 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
467 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
468 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
469 }
470 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
471 radeon_do_wait_for_idle(dev_priv);
472 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
473 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
474 R300_DC_AUTOFLUSH_ENABLE |
475 R300_DC_DC_DISABLE_IGNORE_PE));
476
477
478 }
479
480 /* ================================================================
481 * CP control, initialization
482 */
483
484 /* Load the microcode for the CP */
485 static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
486 {
487 struct platform_device *pdev;
488 const char *fw_name = NULL;
489 int err;
490
491 DRM_DEBUG("\n");
492
493 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
494 err = IS_ERR(pdev);
495 if (err) {
496 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
497 return -EINVAL;
498 }
499
500 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
501 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
502 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
503 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
504 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
505 DRM_INFO("Loading R100 Microcode\n");
506 fw_name = FIRMWARE_R100;
507 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
508 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
509 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
510 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
511 DRM_INFO("Loading R200 Microcode\n");
512 fw_name = FIRMWARE_R200;
513 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
514 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
515 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
516 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
517 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
518 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
519 DRM_INFO("Loading R300 Microcode\n");
520 fw_name = FIRMWARE_R300;
521 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
522 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
523 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
524 DRM_INFO("Loading R400 Microcode\n");
525 fw_name = FIRMWARE_R420;
526 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
527 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
528 DRM_INFO("Loading RS690/RS740 Microcode\n");
529 fw_name = FIRMWARE_RS690;
530 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
531 DRM_INFO("Loading RS600 Microcode\n");
532 fw_name = FIRMWARE_RS600;
533 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
534 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
535 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
536 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
537 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
538 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
539 DRM_INFO("Loading R500 Microcode\n");
540 fw_name = FIRMWARE_R520;
541 }
542
543 err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
544 platform_device_unregister(pdev);
545 if (err) {
546 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
547 fw_name);
548 } else if (dev_priv->me_fw->size % 8) {
549 printk(KERN_ERR
550 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
551 dev_priv->me_fw->size, fw_name);
552 err = -EINVAL;
553 release_firmware(dev_priv->me_fw);
554 dev_priv->me_fw = NULL;
555 }
556 return err;
557 }
558
559 static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
560 {
561 const __be32 *fw_data;
562 int i, size;
563
564 radeon_do_wait_for_idle(dev_priv);
565
566 if (dev_priv->me_fw) {
567 size = dev_priv->me_fw->size / 4;
568 fw_data = (const __be32 *)&dev_priv->me_fw->data[0];
569 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
570 for (i = 0; i < size; i += 2) {
571 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
572 be32_to_cpup(&fw_data[i]));
573 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
574 be32_to_cpup(&fw_data[i + 1]));
575 }
576 }
577 }
578
579 /* Flush any pending commands to the CP. This should only be used just
580 * prior to a wait for idle, as it informs the engine that the command
581 * stream is ending.
582 */
583 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
584 {
585 DRM_DEBUG("\n");
586 }
587
588 /* Wait for the CP to go idle.
589 */
590 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
591 {
592 RING_LOCALS;
593 DRM_DEBUG("\n");
594
595 BEGIN_RING(6);
596
597 RADEON_PURGE_CACHE();
598 RADEON_PURGE_ZCACHE();
599 RADEON_WAIT_UNTIL_IDLE();
600
601 ADVANCE_RING();
602 COMMIT_RING();
603
604 return radeon_do_wait_for_idle(dev_priv);
605 }
606
607 /* Start the Command Processor.
608 */
609 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
610 {
611 RING_LOCALS;
612 DRM_DEBUG("\n");
613
614 radeon_do_wait_for_idle(dev_priv);
615
616 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
617
618 dev_priv->cp_running = 1;
619
620 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
621 BEGIN_RING(3);
622 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
623 OUT_RING(5); /* scratch reg 5 */
624 OUT_RING(0xdeadbeef);
625 ADVANCE_RING();
626 COMMIT_RING();
627 }
628
629 BEGIN_RING(8);
630 /* isync can only be written through cp on r5xx write it here */
631 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
632 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
633 RADEON_ISYNC_ANY3D_IDLE2D |
634 RADEON_ISYNC_WAIT_IDLEGUI |
635 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
636 RADEON_PURGE_CACHE();
637 RADEON_PURGE_ZCACHE();
638 RADEON_WAIT_UNTIL_IDLE();
639 ADVANCE_RING();
640 COMMIT_RING();
641
642 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
643 }
644
645 /* Reset the Command Processor. This will not flush any pending
646 * commands, so you must wait for the CP command stream to complete
647 * before calling this routine.
648 */
649 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
650 {
651 u32 cur_read_ptr;
652 DRM_DEBUG("\n");
653
654 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
655 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
656 SET_RING_HEAD(dev_priv, cur_read_ptr);
657 dev_priv->ring.tail = cur_read_ptr;
658 }
659
660 /* Stop the Command Processor. This will not flush any pending
661 * commands, so you must flush the command stream and wait for the CP
662 * to go idle before calling this routine.
663 */
664 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
665 {
666 RING_LOCALS;
667 DRM_DEBUG("\n");
668
669 /* finish the pending CP_RESYNC token */
670 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
671 BEGIN_RING(2);
672 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
673 OUT_RING(R300_RB3D_DC_FINISH);
674 ADVANCE_RING();
675 COMMIT_RING();
676 radeon_do_wait_for_idle(dev_priv);
677 }
678
679 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
680
681 dev_priv->cp_running = 0;
682 }
683
684 /* Reset the engine. This will stop the CP if it is running.
685 */
686 static int radeon_do_engine_reset(struct drm_device * dev)
687 {
688 drm_radeon_private_t *dev_priv = dev->dev_private;
689 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
690 DRM_DEBUG("\n");
691
692 radeon_do_pixcache_flush(dev_priv);
693
694 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
695 /* may need something similar for newer chips */
696 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
697 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
698
699 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
700 RADEON_FORCEON_MCLKA |
701 RADEON_FORCEON_MCLKB |
702 RADEON_FORCEON_YCLKA |
703 RADEON_FORCEON_YCLKB |
704 RADEON_FORCEON_MC |
705 RADEON_FORCEON_AIC));
706 }
707
708 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
709
710 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
711 RADEON_SOFT_RESET_CP |
712 RADEON_SOFT_RESET_HI |
713 RADEON_SOFT_RESET_SE |
714 RADEON_SOFT_RESET_RE |
715 RADEON_SOFT_RESET_PP |
716 RADEON_SOFT_RESET_E2 |
717 RADEON_SOFT_RESET_RB));
718 RADEON_READ(RADEON_RBBM_SOFT_RESET);
719 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
720 ~(RADEON_SOFT_RESET_CP |
721 RADEON_SOFT_RESET_HI |
722 RADEON_SOFT_RESET_SE |
723 RADEON_SOFT_RESET_RE |
724 RADEON_SOFT_RESET_PP |
725 RADEON_SOFT_RESET_E2 |
726 RADEON_SOFT_RESET_RB)));
727 RADEON_READ(RADEON_RBBM_SOFT_RESET);
728
729 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
730 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
731 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
732 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
733 }
734
735 /* setup the raster pipes */
736 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
737 radeon_init_pipes(dev);
738
739 /* Reset the CP ring */
740 radeon_do_cp_reset(dev_priv);
741
742 /* The CP is no longer running after an engine reset */
743 dev_priv->cp_running = 0;
744
745 /* Reset any pending vertex, indirect buffers */
746 radeon_freelist_reset(dev);
747
748 return 0;
749 }
750
751 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
752 drm_radeon_private_t *dev_priv,
753 struct drm_file *file_priv)
754 {
755 struct drm_radeon_master_private *master_priv;
756 u32 ring_start, cur_read_ptr;
757
758 /* Initialize the memory controller. With new memory map, the fb location
759 * is not changed, it should have been properly initialized already. Part
760 * of the problem is that the code below is bogus, assuming the GART is
761 * always appended to the fb which is not necessarily the case
762 */
763 if (!dev_priv->new_memmap)
764 radeon_write_fb_location(dev_priv,
765 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
766 | (dev_priv->fb_location >> 16));
767
768 #if __OS_HAS_AGP
769 if (dev_priv->flags & RADEON_IS_AGP) {
770 radeon_write_agp_base(dev_priv, dev->agp->base);
771
772 radeon_write_agp_location(dev_priv,
773 (((dev_priv->gart_vm_start - 1 +
774 dev_priv->gart_size) & 0xffff0000) |
775 (dev_priv->gart_vm_start >> 16)));
776
777 ring_start = (dev_priv->cp_ring->offset
778 - dev->agp->base
779 + dev_priv->gart_vm_start);
780 } else
781 #endif
782 ring_start = (dev_priv->cp_ring->offset
783 - (unsigned long)dev->sg->virtual
784 + dev_priv->gart_vm_start);
785
786 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
787
788 /* Set the write pointer delay */
789 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
790
791 /* Initialize the ring buffer's read and write pointers */
792 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
793 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
794 SET_RING_HEAD(dev_priv, cur_read_ptr);
795 dev_priv->ring.tail = cur_read_ptr;
796
797 #if __OS_HAS_AGP
798 if (dev_priv->flags & RADEON_IS_AGP) {
799 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
800 dev_priv->ring_rptr->offset
801 - dev->agp->base + dev_priv->gart_vm_start);
802 } else
803 #endif
804 {
805 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
806 dev_priv->ring_rptr->offset
807 - ((unsigned long) dev->sg->virtual)
808 + dev_priv->gart_vm_start);
809 }
810
811 /* Set ring buffer size */
812 #ifdef __BIG_ENDIAN
813 RADEON_WRITE(RADEON_CP_RB_CNTL,
814 RADEON_BUF_SWAP_32BIT |
815 (dev_priv->ring.fetch_size_l2ow << 18) |
816 (dev_priv->ring.rptr_update_l2qw << 8) |
817 dev_priv->ring.size_l2qw);
818 #else
819 RADEON_WRITE(RADEON_CP_RB_CNTL,
820 (dev_priv->ring.fetch_size_l2ow << 18) |
821 (dev_priv->ring.rptr_update_l2qw << 8) |
822 dev_priv->ring.size_l2qw);
823 #endif
824
825
826 /* Initialize the scratch register pointer. This will cause
827 * the scratch register values to be written out to memory
828 * whenever they are updated.
829 *
830 * We simply put this behind the ring read pointer, this works
831 * with PCI GART as well as (whatever kind of) AGP GART
832 */
833 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
834 + RADEON_SCRATCH_REG_OFFSET);
835
836 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
837
838 radeon_enable_bm(dev_priv);
839
840 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
841 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
842
843 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
844 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
845
846 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
847 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
848
849 /* reset sarea copies of these */
850 master_priv = file_priv->master->driver_priv;
851 if (master_priv->sarea_priv) {
852 master_priv->sarea_priv->last_frame = 0;
853 master_priv->sarea_priv->last_dispatch = 0;
854 master_priv->sarea_priv->last_clear = 0;
855 }
856
857 radeon_do_wait_for_idle(dev_priv);
858
859 /* Sync everything up */
860 RADEON_WRITE(RADEON_ISYNC_CNTL,
861 (RADEON_ISYNC_ANY2D_IDLE3D |
862 RADEON_ISYNC_ANY3D_IDLE2D |
863 RADEON_ISYNC_WAIT_IDLEGUI |
864 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
865
866 }
867
868 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
869 {
870 u32 tmp;
871
872 /* Start with assuming that writeback doesn't work */
873 dev_priv->writeback_works = 0;
874
875 /* Writeback doesn't seem to work everywhere, test it here and possibly
876 * enable it if it appears to work
877 */
878 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
879
880 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
881
882 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
883 u32 val;
884
885 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
886 if (val == 0xdeadbeef)
887 break;
888 DRM_UDELAY(1);
889 }
890
891 if (tmp < dev_priv->usec_timeout) {
892 dev_priv->writeback_works = 1;
893 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
894 } else {
895 dev_priv->writeback_works = 0;
896 DRM_INFO("writeback test failed\n");
897 }
898 if (radeon_no_wb == 1) {
899 dev_priv->writeback_works = 0;
900 DRM_INFO("writeback forced off\n");
901 }
902
903 if (!dev_priv->writeback_works) {
904 /* Disable writeback to avoid unnecessary bus master transfer */
905 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
906 RADEON_RB_NO_UPDATE);
907 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
908 }
909 }
910
911 /* Enable or disable IGP GART on the chip */
912 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
913 {
914 u32 temp;
915
916 if (on) {
917 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
918 dev_priv->gart_vm_start,
919 (long)dev_priv->gart_info.bus_addr,
920 dev_priv->gart_size);
921
922 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
923 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
924 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
925 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
926 RS690_BLOCK_GFX_D3_EN));
927 else
928 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
929
930 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
931 RS480_VA_SIZE_32MB));
932
933 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
934 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
935 RS480_TLB_ENABLE |
936 RS480_GTW_LAC_EN |
937 RS480_1LEVEL_GART));
938
939 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
940 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
941 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
942
943 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
944 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
945 RS480_REQ_TYPE_SNOOP_DIS));
946
947 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
948
949 dev_priv->gart_size = 32*1024*1024;
950 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
951 0xffff0000) | (dev_priv->gart_vm_start >> 16));
952
953 radeon_write_agp_location(dev_priv, temp);
954
955 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
956 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
957 RS480_VA_SIZE_32MB));
958
959 do {
960 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
961 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
962 break;
963 DRM_UDELAY(1);
964 } while (1);
965
966 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
967 RS480_GART_CACHE_INVALIDATE);
968
969 do {
970 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
971 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
972 break;
973 DRM_UDELAY(1);
974 } while (1);
975
976 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
977 } else {
978 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
979 }
980 }
981
982 /* Enable or disable IGP GART on the chip */
983 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
984 {
985 u32 temp;
986 int i;
987
988 if (on) {
989 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
990 dev_priv->gart_vm_start,
991 (long)dev_priv->gart_info.bus_addr,
992 dev_priv->gart_size);
993
994 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
995 RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
996
997 for (i = 0; i < 19; i++)
998 IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
999 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
1000 RS600_SYSTEM_ACCESS_MODE_IN_SYS |
1001 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
1002 RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
1003 RS600_ENABLE_FRAGMENT_PROCESSING |
1004 RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
1005
1006 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
1007 RS600_PAGE_TABLE_TYPE_FLAT));
1008
1009 /* disable all other contexts */
1010 for (i = 1; i < 8; i++)
1011 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
1012
1013 /* setup the page table aperture */
1014 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
1015 dev_priv->gart_info.bus_addr);
1016 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
1017 dev_priv->gart_vm_start);
1018 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
1019 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1020 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
1021
1022 /* setup the system aperture */
1023 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
1024 dev_priv->gart_vm_start);
1025 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
1026 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1027
1028 /* enable page tables */
1029 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1030 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
1031
1032 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1033 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
1034
1035 /* invalidate the cache */
1036 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1037
1038 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1039 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1040 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1041
1042 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
1043 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1044 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1045
1046 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1047 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1048 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1049
1050 } else {
1051 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
1052 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1053 temp &= ~RS600_ENABLE_PAGE_TABLES;
1054 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
1055 }
1056 }
1057
1058 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1059 {
1060 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1061 if (on) {
1062
1063 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1064 dev_priv->gart_vm_start,
1065 (long)dev_priv->gart_info.bus_addr,
1066 dev_priv->gart_size);
1067 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1068 dev_priv->gart_vm_start);
1069 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1070 dev_priv->gart_info.bus_addr);
1071 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1072 dev_priv->gart_vm_start);
1073 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1074 dev_priv->gart_vm_start +
1075 dev_priv->gart_size - 1);
1076
1077 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1078
1079 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1080 RADEON_PCIE_TX_GART_EN);
1081 } else {
1082 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1083 tmp & ~RADEON_PCIE_TX_GART_EN);
1084 }
1085 }
1086
1087 /* Enable or disable PCI GART on the chip */
1088 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1089 {
1090 u32 tmp;
1091
1092 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1093 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1094 (dev_priv->flags & RADEON_IS_IGPGART)) {
1095 radeon_set_igpgart(dev_priv, on);
1096 return;
1097 }
1098
1099 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1100 rs600_set_igpgart(dev_priv, on);
1101 return;
1102 }
1103
1104 if (dev_priv->flags & RADEON_IS_PCIE) {
1105 radeon_set_pciegart(dev_priv, on);
1106 return;
1107 }
1108
1109 tmp = RADEON_READ(RADEON_AIC_CNTL);
1110
1111 if (on) {
1112 RADEON_WRITE(RADEON_AIC_CNTL,
1113 tmp | RADEON_PCIGART_TRANSLATE_EN);
1114
1115 /* set PCI GART page-table base address
1116 */
1117 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1118
1119 /* set address range for PCI address translate
1120 */
1121 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1122 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1123 + dev_priv->gart_size - 1);
1124
1125 /* Turn off AGP aperture -- is this required for PCI GART?
1126 */
1127 radeon_write_agp_location(dev_priv, 0xffffffc0);
1128 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1129 } else {
1130 RADEON_WRITE(RADEON_AIC_CNTL,
1131 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1132 }
1133 }
1134
1135 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1136 {
1137 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1138 struct radeon_virt_surface *vp;
1139 int i;
1140
1141 for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1142 if (!dev_priv->virt_surfaces[i].file_priv ||
1143 dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1144 break;
1145 }
1146 if (i >= 2 * RADEON_MAX_SURFACES)
1147 return -ENOMEM;
1148 vp = &dev_priv->virt_surfaces[i];
1149
1150 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1151 struct radeon_surface *sp = &dev_priv->surfaces[i];
1152 if (sp->refcount)
1153 continue;
1154
1155 vp->surface_index = i;
1156 vp->lower = gart_info->bus_addr;
1157 vp->upper = vp->lower + gart_info->table_size;
1158 vp->flags = 0;
1159 vp->file_priv = PCIGART_FILE_PRIV;
1160
1161 sp->refcount = 1;
1162 sp->lower = vp->lower;
1163 sp->upper = vp->upper;
1164 sp->flags = 0;
1165
1166 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1167 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1168 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1169 return 0;
1170 }
1171
1172 return -ENOMEM;
1173 }
1174
1175 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1176 struct drm_file *file_priv)
1177 {
1178 drm_radeon_private_t *dev_priv = dev->dev_private;
1179 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1180
1181 DRM_DEBUG("\n");
1182
1183 /* if we require new memory map but we don't have it fail */
1184 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1185 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1186 radeon_do_cleanup_cp(dev);
1187 return -EINVAL;
1188 }
1189
1190 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1191 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1192 dev_priv->flags &= ~RADEON_IS_AGP;
1193 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1194 && !init->is_pci) {
1195 DRM_DEBUG("Restoring AGP flag\n");
1196 dev_priv->flags |= RADEON_IS_AGP;
1197 }
1198
1199 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1200 DRM_ERROR("PCI GART memory not allocated!\n");
1201 radeon_do_cleanup_cp(dev);
1202 return -EINVAL;
1203 }
1204
1205 dev_priv->usec_timeout = init->usec_timeout;
1206 if (dev_priv->usec_timeout < 1 ||
1207 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1208 DRM_DEBUG("TIMEOUT problem!\n");
1209 radeon_do_cleanup_cp(dev);
1210 return -EINVAL;
1211 }
1212
1213 /* Enable vblank on CRTC1 for older X servers
1214 */
1215 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1216
1217 switch(init->func) {
1218 case RADEON_INIT_R200_CP:
1219 dev_priv->microcode_version = UCODE_R200;
1220 break;
1221 case RADEON_INIT_R300_CP:
1222 dev_priv->microcode_version = UCODE_R300;
1223 break;
1224 default:
1225 dev_priv->microcode_version = UCODE_R100;
1226 }
1227
1228 dev_priv->do_boxes = 0;
1229 dev_priv->cp_mode = init->cp_mode;
1230
1231 /* We don't support anything other than bus-mastering ring mode,
1232 * but the ring can be in either AGP or PCI space for the ring
1233 * read pointer.
1234 */
1235 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1236 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1237 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1238 radeon_do_cleanup_cp(dev);
1239 return -EINVAL;
1240 }
1241
1242 switch (init->fb_bpp) {
1243 case 16:
1244 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1245 break;
1246 case 32:
1247 default:
1248 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1249 break;
1250 }
1251 dev_priv->front_offset = init->front_offset;
1252 dev_priv->front_pitch = init->front_pitch;
1253 dev_priv->back_offset = init->back_offset;
1254 dev_priv->back_pitch = init->back_pitch;
1255
1256 switch (init->depth_bpp) {
1257 case 16:
1258 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1259 break;
1260 case 32:
1261 default:
1262 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1263 break;
1264 }
1265 dev_priv->depth_offset = init->depth_offset;
1266 dev_priv->depth_pitch = init->depth_pitch;
1267
1268 /* Hardware state for depth clears. Remove this if/when we no
1269 * longer clear the depth buffer with a 3D rectangle. Hard-code
1270 * all values to prevent unwanted 3D state from slipping through
1271 * and screwing with the clear operation.
1272 */
1273 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1274 (dev_priv->color_fmt << 10) |
1275 (dev_priv->microcode_version ==
1276 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1277
1278 dev_priv->depth_clear.rb3d_zstencilcntl =
1279 (dev_priv->depth_fmt |
1280 RADEON_Z_TEST_ALWAYS |
1281 RADEON_STENCIL_TEST_ALWAYS |
1282 RADEON_STENCIL_S_FAIL_REPLACE |
1283 RADEON_STENCIL_ZPASS_REPLACE |
1284 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1285
1286 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1287 RADEON_BFACE_SOLID |
1288 RADEON_FFACE_SOLID |
1289 RADEON_FLAT_SHADE_VTX_LAST |
1290 RADEON_DIFFUSE_SHADE_FLAT |
1291 RADEON_ALPHA_SHADE_FLAT |
1292 RADEON_SPECULAR_SHADE_FLAT |
1293 RADEON_FOG_SHADE_FLAT |
1294 RADEON_VTX_PIX_CENTER_OGL |
1295 RADEON_ROUND_MODE_TRUNC |
1296 RADEON_ROUND_PREC_8TH_PIX);
1297
1298
1299 dev_priv->ring_offset = init->ring_offset;
1300 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1301 dev_priv->buffers_offset = init->buffers_offset;
1302 dev_priv->gart_textures_offset = init->gart_textures_offset;
1303
1304 master_priv->sarea = drm_getsarea(dev);
1305 if (!master_priv->sarea) {
1306 DRM_ERROR("could not find sarea!\n");
1307 radeon_do_cleanup_cp(dev);
1308 return -EINVAL;
1309 }
1310
1311 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1312 if (!dev_priv->cp_ring) {
1313 DRM_ERROR("could not find cp ring region!\n");
1314 radeon_do_cleanup_cp(dev);
1315 return -EINVAL;
1316 }
1317 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1318 if (!dev_priv->ring_rptr) {
1319 DRM_ERROR("could not find ring read pointer!\n");
1320 radeon_do_cleanup_cp(dev);
1321 return -EINVAL;
1322 }
1323 dev->agp_buffer_token = init->buffers_offset;
1324 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1325 if (!dev->agp_buffer_map) {
1326 DRM_ERROR("could not find dma buffer region!\n");
1327 radeon_do_cleanup_cp(dev);
1328 return -EINVAL;
1329 }
1330
1331 if (init->gart_textures_offset) {
1332 dev_priv->gart_textures =
1333 drm_core_findmap(dev, init->gart_textures_offset);
1334 if (!dev_priv->gart_textures) {
1335 DRM_ERROR("could not find GART texture region!\n");
1336 radeon_do_cleanup_cp(dev);
1337 return -EINVAL;
1338 }
1339 }
1340
1341 #if __OS_HAS_AGP
1342 if (dev_priv->flags & RADEON_IS_AGP) {
1343 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1344 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1345 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1346 if (!dev_priv->cp_ring->handle ||
1347 !dev_priv->ring_rptr->handle ||
1348 !dev->agp_buffer_map->handle) {
1349 DRM_ERROR("could not find ioremap agp regions!\n");
1350 radeon_do_cleanup_cp(dev);
1351 return -EINVAL;
1352 }
1353 } else
1354 #endif
1355 {
1356 dev_priv->cp_ring->handle =
1357 (void *)(unsigned long)dev_priv->cp_ring->offset;
1358 dev_priv->ring_rptr->handle =
1359 (void *)(unsigned long)dev_priv->ring_rptr->offset;
1360 dev->agp_buffer_map->handle =
1361 (void *)(unsigned long)dev->agp_buffer_map->offset;
1362
1363 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1364 dev_priv->cp_ring->handle);
1365 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1366 dev_priv->ring_rptr->handle);
1367 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1368 dev->agp_buffer_map->handle);
1369 }
1370
1371 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1372 dev_priv->fb_size =
1373 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1374 - dev_priv->fb_location;
1375
1376 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1377 ((dev_priv->front_offset
1378 + dev_priv->fb_location) >> 10));
1379
1380 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1381 ((dev_priv->back_offset
1382 + dev_priv->fb_location) >> 10));
1383
1384 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1385 ((dev_priv->depth_offset
1386 + dev_priv->fb_location) >> 10));
1387
1388 dev_priv->gart_size = init->gart_size;
1389
1390 /* New let's set the memory map ... */
1391 if (dev_priv->new_memmap) {
1392 u32 base = 0;
1393
1394 DRM_INFO("Setting GART location based on new memory map\n");
1395
1396 /* If using AGP, try to locate the AGP aperture at the same
1397 * location in the card and on the bus, though we have to
1398 * align it down.
1399 */
1400 #if __OS_HAS_AGP
1401 if (dev_priv->flags & RADEON_IS_AGP) {
1402 base = dev->agp->base;
1403 /* Check if valid */
1404 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1405 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1406 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1407 dev->agp->base);
1408 base = 0;
1409 }
1410 }
1411 #endif
1412 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1413 if (base == 0) {
1414 base = dev_priv->fb_location + dev_priv->fb_size;
1415 if (base < dev_priv->fb_location ||
1416 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1417 base = dev_priv->fb_location
1418 - dev_priv->gart_size;
1419 }
1420 dev_priv->gart_vm_start = base & 0xffc00000u;
1421 if (dev_priv->gart_vm_start != base)
1422 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1423 base, dev_priv->gart_vm_start);
1424 } else {
1425 DRM_INFO("Setting GART location based on old memory map\n");
1426 dev_priv->gart_vm_start = dev_priv->fb_location +
1427 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1428 }
1429
1430 #if __OS_HAS_AGP
1431 if (dev_priv->flags & RADEON_IS_AGP)
1432 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1433 - dev->agp->base
1434 + dev_priv->gart_vm_start);
1435 else
1436 #endif
1437 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1438 - (unsigned long)dev->sg->virtual
1439 + dev_priv->gart_vm_start);
1440
1441 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1442 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1443 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1444 dev_priv->gart_buffers_offset);
1445
1446 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1447 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1448 + init->ring_size / sizeof(u32));
1449 dev_priv->ring.size = init->ring_size;
1450 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1451
1452 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1453 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1454
1455 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1456 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1457 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1458
1459 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1460
1461 #if __OS_HAS_AGP
1462 if (dev_priv->flags & RADEON_IS_AGP) {
1463 /* Turn off PCI GART */
1464 radeon_set_pcigart(dev_priv, 0);
1465 } else
1466 #endif
1467 {
1468 u32 sctrl;
1469 int ret;
1470
1471 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1472 /* if we have an offset set from userspace */
1473 if (dev_priv->pcigart_offset_set) {
1474 dev_priv->gart_info.bus_addr =
1475 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1476 dev_priv->gart_info.mapping.offset =
1477 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1478 dev_priv->gart_info.mapping.size =
1479 dev_priv->gart_info.table_size;
1480
1481 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1482 dev_priv->gart_info.addr =
1483 dev_priv->gart_info.mapping.handle;
1484
1485 if (dev_priv->flags & RADEON_IS_PCIE)
1486 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1487 else
1488 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1489 dev_priv->gart_info.gart_table_location =
1490 DRM_ATI_GART_FB;
1491
1492 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1493 dev_priv->gart_info.addr,
1494 dev_priv->pcigart_offset);
1495 } else {
1496 if (dev_priv->flags & RADEON_IS_IGPGART)
1497 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1498 else
1499 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1500 dev_priv->gart_info.gart_table_location =
1501 DRM_ATI_GART_MAIN;
1502 dev_priv->gart_info.addr = NULL;
1503 dev_priv->gart_info.bus_addr = 0;
1504 if (dev_priv->flags & RADEON_IS_PCIE) {
1505 DRM_ERROR
1506 ("Cannot use PCI Express without GART in FB memory\n");
1507 radeon_do_cleanup_cp(dev);
1508 return -EINVAL;
1509 }
1510 }
1511
1512 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1513 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1514 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1515 ret = r600_page_table_init(dev);
1516 else
1517 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1518 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1519
1520 if (!ret) {
1521 DRM_ERROR("failed to init PCI GART!\n");
1522 radeon_do_cleanup_cp(dev);
1523 return -ENOMEM;
1524 }
1525
1526 ret = radeon_setup_pcigart_surface(dev_priv);
1527 if (ret) {
1528 DRM_ERROR("failed to setup GART surface!\n");
1529 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1530 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1531 else
1532 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1533 radeon_do_cleanup_cp(dev);
1534 return ret;
1535 }
1536
1537 /* Turn on PCI GART */
1538 radeon_set_pcigart(dev_priv, 1);
1539 }
1540
1541 if (!dev_priv->me_fw) {
1542 int err = radeon_cp_init_microcode(dev_priv);
1543 if (err) {
1544 DRM_ERROR("Failed to load firmware!\n");
1545 radeon_do_cleanup_cp(dev);
1546 return err;
1547 }
1548 }
1549 radeon_cp_load_microcode(dev_priv);
1550 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1551
1552 dev_priv->last_buf = 0;
1553
1554 radeon_do_engine_reset(dev);
1555 radeon_test_writeback(dev_priv);
1556
1557 return 0;
1558 }
1559
1560 static int radeon_do_cleanup_cp(struct drm_device * dev)
1561 {
1562 drm_radeon_private_t *dev_priv = dev->dev_private;
1563 DRM_DEBUG("\n");
1564
1565 /* Make sure interrupts are disabled here because the uninstall ioctl
1566 * may not have been called from userspace and after dev_private
1567 * is freed, it's too late.
1568 */
1569 if (dev->irq_enabled)
1570 drm_irq_uninstall(dev);
1571
1572 #if __OS_HAS_AGP
1573 if (dev_priv->flags & RADEON_IS_AGP) {
1574 if (dev_priv->cp_ring != NULL) {
1575 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1576 dev_priv->cp_ring = NULL;
1577 }
1578 if (dev_priv->ring_rptr != NULL) {
1579 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1580 dev_priv->ring_rptr = NULL;
1581 }
1582 if (dev->agp_buffer_map != NULL) {
1583 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1584 dev->agp_buffer_map = NULL;
1585 }
1586 } else
1587 #endif
1588 {
1589
1590 if (dev_priv->gart_info.bus_addr) {
1591 /* Turn off PCI GART */
1592 radeon_set_pcigart(dev_priv, 0);
1593 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1594 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1595 else {
1596 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1597 DRM_ERROR("failed to cleanup PCI GART!\n");
1598 }
1599 }
1600
1601 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1602 {
1603 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1604 dev_priv->gart_info.addr = NULL;
1605 }
1606 }
1607 /* only clear to the start of flags */
1608 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1609
1610 return 0;
1611 }
1612
1613 /* This code will reinit the Radeon CP hardware after a resume from disc.
1614 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1615 * here we make sure that all Radeon hardware initialisation is re-done without
1616 * affecting running applications.
1617 *
1618 * Charl P. Botha <http://cpbotha.net>
1619 */
1620 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1621 {
1622 drm_radeon_private_t *dev_priv = dev->dev_private;
1623
1624 if (!dev_priv) {
1625 DRM_ERROR("Called with no initialization\n");
1626 return -EINVAL;
1627 }
1628
1629 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1630
1631 #if __OS_HAS_AGP
1632 if (dev_priv->flags & RADEON_IS_AGP) {
1633 /* Turn off PCI GART */
1634 radeon_set_pcigart(dev_priv, 0);
1635 } else
1636 #endif
1637 {
1638 /* Turn on PCI GART */
1639 radeon_set_pcigart(dev_priv, 1);
1640 }
1641
1642 radeon_cp_load_microcode(dev_priv);
1643 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1644
1645 dev_priv->have_z_offset = 0;
1646 radeon_do_engine_reset(dev);
1647 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1648
1649 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1650
1651 return 0;
1652 }
1653
1654 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1655 {
1656 drm_radeon_private_t *dev_priv = dev->dev_private;
1657 drm_radeon_init_t *init = data;
1658
1659 LOCK_TEST_WITH_RETURN(dev, file_priv);
1660
1661 if (init->func == RADEON_INIT_R300_CP)
1662 r300_init_reg_flags(dev);
1663
1664 switch (init->func) {
1665 case RADEON_INIT_CP:
1666 case RADEON_INIT_R200_CP:
1667 case RADEON_INIT_R300_CP:
1668 return radeon_do_init_cp(dev, init, file_priv);
1669 case RADEON_INIT_R600_CP:
1670 return r600_do_init_cp(dev, init, file_priv);
1671 case RADEON_CLEANUP_CP:
1672 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1673 return r600_do_cleanup_cp(dev);
1674 else
1675 return radeon_do_cleanup_cp(dev);
1676 }
1677
1678 return -EINVAL;
1679 }
1680
1681 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1682 {
1683 drm_radeon_private_t *dev_priv = dev->dev_private;
1684 DRM_DEBUG("\n");
1685
1686 LOCK_TEST_WITH_RETURN(dev, file_priv);
1687
1688 if (dev_priv->cp_running) {
1689 DRM_DEBUG("while CP running\n");
1690 return 0;
1691 }
1692 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1693 DRM_DEBUG("called with bogus CP mode (%d)\n",
1694 dev_priv->cp_mode);
1695 return 0;
1696 }
1697
1698 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1699 r600_do_cp_start(dev_priv);
1700 else
1701 radeon_do_cp_start(dev_priv);
1702
1703 return 0;
1704 }
1705
1706 /* Stop the CP. The engine must have been idled before calling this
1707 * routine.
1708 */
1709 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1710 {
1711 drm_radeon_private_t *dev_priv = dev->dev_private;
1712 drm_radeon_cp_stop_t *stop = data;
1713 int ret;
1714 DRM_DEBUG("\n");
1715
1716 LOCK_TEST_WITH_RETURN(dev, file_priv);
1717
1718 if (!dev_priv->cp_running)
1719 return 0;
1720
1721 /* Flush any pending CP commands. This ensures any outstanding
1722 * commands are exectuted by the engine before we turn it off.
1723 */
1724 if (stop->flush) {
1725 radeon_do_cp_flush(dev_priv);
1726 }
1727
1728 /* If we fail to make the engine go idle, we return an error
1729 * code so that the DRM ioctl wrapper can try again.
1730 */
1731 if (stop->idle) {
1732 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1733 ret = r600_do_cp_idle(dev_priv);
1734 else
1735 ret = radeon_do_cp_idle(dev_priv);
1736 if (ret)
1737 return ret;
1738 }
1739
1740 /* Finally, we can turn off the CP. If the engine isn't idle,
1741 * we will get some dropped triangles as they won't be fully
1742 * rendered before the CP is shut down.
1743 */
1744 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1745 r600_do_cp_stop(dev_priv);
1746 else
1747 radeon_do_cp_stop(dev_priv);
1748
1749 /* Reset the engine */
1750 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1751 r600_do_engine_reset(dev);
1752 else
1753 radeon_do_engine_reset(dev);
1754
1755 return 0;
1756 }
1757
1758 void radeon_do_release(struct drm_device * dev)
1759 {
1760 drm_radeon_private_t *dev_priv = dev->dev_private;
1761 int i, ret;
1762
1763 if (dev_priv) {
1764 if (dev_priv->cp_running) {
1765 /* Stop the cp */
1766 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1767 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1768 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1769 #ifdef __linux__
1770 schedule();
1771 #else
1772 tsleep(&ret, PZERO, "rdnrel", 1);
1773 #endif
1774 }
1775 } else {
1776 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1777 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1778 #ifdef __linux__
1779 schedule();
1780 #else
1781 tsleep(&ret, PZERO, "rdnrel", 1);
1782 #endif
1783 }
1784 }
1785 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1786 r600_do_cp_stop(dev_priv);
1787 r600_do_engine_reset(dev);
1788 } else {
1789 radeon_do_cp_stop(dev_priv);
1790 radeon_do_engine_reset(dev);
1791 }
1792 }
1793
1794 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1795 /* Disable *all* interrupts */
1796 if (dev_priv->mmio) /* remove this after permanent addmaps */
1797 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1798
1799 if (dev_priv->mmio) { /* remove all surfaces */
1800 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1801 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1802 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1803 16 * i, 0);
1804 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1805 16 * i, 0);
1806 }
1807 }
1808 }
1809
1810 /* Free memory heap structures */
1811 radeon_mem_takedown(&(dev_priv->gart_heap));
1812 radeon_mem_takedown(&(dev_priv->fb_heap));
1813
1814 /* deallocate kernel resources */
1815 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1816 r600_do_cleanup_cp(dev);
1817 else
1818 radeon_do_cleanup_cp(dev);
1819 if (dev_priv->me_fw) {
1820 release_firmware(dev_priv->me_fw);
1821 dev_priv->me_fw = NULL;
1822 }
1823 if (dev_priv->pfp_fw) {
1824 release_firmware(dev_priv->pfp_fw);
1825 dev_priv->pfp_fw = NULL;
1826 }
1827 }
1828 }
1829
1830 /* Just reset the CP ring. Called as part of an X Server engine reset.
1831 */
1832 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1833 {
1834 drm_radeon_private_t *dev_priv = dev->dev_private;
1835 DRM_DEBUG("\n");
1836
1837 LOCK_TEST_WITH_RETURN(dev, file_priv);
1838
1839 if (!dev_priv) {
1840 DRM_DEBUG("called before init done\n");
1841 return -EINVAL;
1842 }
1843
1844 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1845 r600_do_cp_reset(dev_priv);
1846 else
1847 radeon_do_cp_reset(dev_priv);
1848
1849 /* The CP is no longer running after an engine reset */
1850 dev_priv->cp_running = 0;
1851
1852 return 0;
1853 }
1854
1855 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1856 {
1857 drm_radeon_private_t *dev_priv = dev->dev_private;
1858 DRM_DEBUG("\n");
1859
1860 LOCK_TEST_WITH_RETURN(dev, file_priv);
1861
1862 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1863 return r600_do_cp_idle(dev_priv);
1864 else
1865 return radeon_do_cp_idle(dev_priv);
1866 }
1867
1868 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1869 */
1870 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1871 {
1872 drm_radeon_private_t *dev_priv = dev->dev_private;
1873 DRM_DEBUG("\n");
1874
1875 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1876 return r600_do_resume_cp(dev, file_priv);
1877 else
1878 return radeon_do_resume_cp(dev, file_priv);
1879 }
1880
1881 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1882 {
1883 drm_radeon_private_t *dev_priv = dev->dev_private;
1884 DRM_DEBUG("\n");
1885
1886 LOCK_TEST_WITH_RETURN(dev, file_priv);
1887
1888 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1889 return r600_do_engine_reset(dev);
1890 else
1891 return radeon_do_engine_reset(dev);
1892 }
1893
1894 /* ================================================================
1895 * Fullscreen mode
1896 */
1897
1898 /* KW: Deprecated to say the least:
1899 */
1900 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1901 {
1902 return 0;
1903 }
1904
1905 /* ================================================================
1906 * Freelist management
1907 */
1908
1909
1910 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1911 {
1912 struct drm_device_dma *dma = dev->dma;
1913 drm_radeon_private_t *dev_priv = dev->dev_private;
1914 drm_radeon_buf_priv_t *buf_priv;
1915 struct drm_buf *buf;
1916 int i, t;
1917 int start;
1918
1919 if (++dev_priv->last_buf >= dma->buf_count)
1920 dev_priv->last_buf = 0;
1921
1922 start = dev_priv->last_buf;
1923
1924 for (t = 0; t < dev_priv->usec_timeout; t++) {
1925 u32 done_age = GET_SCRATCH(dev_priv, 1);
1926 DRM_DEBUG("done_age = %d\n", done_age);
1927 for (i = 0; i < dma->buf_count; i++) {
1928 buf = dma->buflist[start];
1929 buf_priv = buf->dev_private;
1930 if (buf->file_priv == NULL || (buf->pending &&
1931 buf_priv->age <=
1932 done_age)) {
1933 dev_priv->stats.requested_bufs++;
1934 buf->pending = 0;
1935 return buf;
1936 }
1937 if (++start >= dma->buf_count)
1938 start = 0;
1939 }
1940
1941 if (t) {
1942 DRM_UDELAY(1);
1943 dev_priv->stats.freelist_loops++;
1944 }
1945 }
1946
1947 return NULL;
1948 }
1949
1950 void radeon_freelist_reset(struct drm_device * dev)
1951 {
1952 struct drm_device_dma *dma = dev->dma;
1953 drm_radeon_private_t *dev_priv = dev->dev_private;
1954 int i;
1955
1956 dev_priv->last_buf = 0;
1957 for (i = 0; i < dma->buf_count; i++) {
1958 struct drm_buf *buf = dma->buflist[i];
1959 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1960 buf_priv->age = 0;
1961 }
1962 }
1963
1964 /* ================================================================
1965 * CP command submission
1966 */
1967
1968 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1969 {
1970 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1971 int i;
1972 u32 last_head = GET_RING_HEAD(dev_priv);
1973
1974 for (i = 0; i < dev_priv->usec_timeout; i++) {
1975 u32 head = GET_RING_HEAD(dev_priv);
1976
1977 ring->space = (head - ring->tail) * sizeof(u32);
1978 if (ring->space <= 0)
1979 ring->space += ring->size;
1980 if (ring->space > n)
1981 return 0;
1982
1983 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1984
1985 if (head != last_head)
1986 i = 0;
1987 last_head = head;
1988
1989 DRM_UDELAY(1);
1990 }
1991
1992 #if RADEON_FIFO_DEBUG
1993 radeon_status(dev_priv);
1994 DRM_ERROR("failed!\n");
1995 #endif
1996 return -EBUSY;
1997 }
1998
1999 static int radeon_cp_get_buffers(struct drm_device *dev,
2000 struct drm_file *file_priv,
2001 struct drm_dma * d)
2002 {
2003 int i;
2004 struct drm_buf *buf;
2005
2006 for (i = d->granted_count; i < d->request_count; i++) {
2007 buf = radeon_freelist_get(dev);
2008 if (!buf)
2009 return -EBUSY; /* NOTE: broken client */
2010
2011 buf->file_priv = file_priv;
2012
2013 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2014 sizeof(buf->idx)))
2015 return -EFAULT;
2016 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2017 sizeof(buf->total)))
2018 return -EFAULT;
2019
2020 d->granted_count++;
2021 }
2022 return 0;
2023 }
2024
2025 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2026 {
2027 struct drm_device_dma *dma = dev->dma;
2028 int ret = 0;
2029 struct drm_dma *d = data;
2030
2031 LOCK_TEST_WITH_RETURN(dev, file_priv);
2032
2033 /* Please don't send us buffers.
2034 */
2035 if (d->send_count != 0) {
2036 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2037 DRM_CURRENTPID, d->send_count);
2038 return -EINVAL;
2039 }
2040
2041 /* We'll send you buffers.
2042 */
2043 if (d->request_count < 0 || d->request_count > dma->buf_count) {
2044 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2045 DRM_CURRENTPID, d->request_count, dma->buf_count);
2046 return -EINVAL;
2047 }
2048
2049 d->granted_count = 0;
2050
2051 if (d->request_count) {
2052 ret = radeon_cp_get_buffers(dev, file_priv, d);
2053 }
2054
2055 return ret;
2056 }
2057
2058 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2059 {
2060 drm_radeon_private_t *dev_priv;
2061 int ret = 0;
2062
2063 dev_priv = kzalloc(sizeof(drm_radeon_private_t), GFP_KERNEL);
2064 if (dev_priv == NULL)
2065 return -ENOMEM;
2066
2067 dev->dev_private = (void *)dev_priv;
2068 dev_priv->flags = flags;
2069
2070 switch (flags & RADEON_FAMILY_MASK) {
2071 case CHIP_R100:
2072 case CHIP_RV200:
2073 case CHIP_R200:
2074 case CHIP_R300:
2075 case CHIP_R350:
2076 case CHIP_R420:
2077 case CHIP_R423:
2078 case CHIP_RV410:
2079 case CHIP_RV515:
2080 case CHIP_R520:
2081 case CHIP_RV570:
2082 case CHIP_R580:
2083 dev_priv->flags |= RADEON_HAS_HIERZ;
2084 break;
2085 default:
2086 /* all other chips have no hierarchical z buffer */
2087 break;
2088 }
2089
2090 if (drm_device_is_agp(dev))
2091 dev_priv->flags |= RADEON_IS_AGP;
2092 else if (drm_device_is_pcie(dev))
2093 dev_priv->flags |= RADEON_IS_PCIE;
2094 else
2095 dev_priv->flags |= RADEON_IS_PCI;
2096
2097 ret = drm_addmap(dev, pci_resource_start(dev->pdev, 2),
2098 pci_resource_len(dev->pdev, 2), _DRM_REGISTERS,
2099 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2100 if (ret != 0)
2101 return ret;
2102
2103 ret = drm_vblank_init(dev, 2);
2104 if (ret) {
2105 radeon_driver_unload(dev);
2106 return ret;
2107 }
2108
2109 DRM_DEBUG("%s card detected\n",
2110 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2111 return ret;
2112 }
2113
2114 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2115 {
2116 struct drm_radeon_master_private *master_priv;
2117 unsigned long sareapage;
2118 int ret;
2119
2120 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
2121 if (!master_priv)
2122 return -ENOMEM;
2123
2124 /* prebuild the SAREA */
2125 sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
2126 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK,
2127 &master_priv->sarea);
2128 if (ret) {
2129 DRM_ERROR("SAREA setup failed\n");
2130 kfree(master_priv);
2131 return ret;
2132 }
2133 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
2134 master_priv->sarea_priv->pfCurrentPage = 0;
2135
2136 master->driver_priv = master_priv;
2137 return 0;
2138 }
2139
2140 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2141 {
2142 struct drm_radeon_master_private *master_priv = master->driver_priv;
2143
2144 if (!master_priv)
2145 return;
2146
2147 if (master_priv->sarea_priv &&
2148 master_priv->sarea_priv->pfCurrentPage != 0)
2149 radeon_cp_dispatch_flip(dev, master);
2150
2151 master_priv->sarea_priv = NULL;
2152 if (master_priv->sarea)
2153 drm_rmmap_locked(dev, master_priv->sarea);
2154
2155 kfree(master_priv);
2156
2157 master->driver_priv = NULL;
2158 }
2159
2160 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2161 * have to find them.
2162 */
2163 int radeon_driver_firstopen(struct drm_device *dev)
2164 {
2165 int ret;
2166 drm_local_map_t *map;
2167 drm_radeon_private_t *dev_priv = dev->dev_private;
2168
2169 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2170
2171 dev_priv->fb_aper_offset = pci_resource_start(dev->pdev, 0);
2172 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2173 pci_resource_len(dev->pdev, 0), _DRM_FRAME_BUFFER,
2174 _DRM_WRITE_COMBINING, &map);
2175 if (ret != 0)
2176 return ret;
2177
2178 return 0;
2179 }
2180
2181 int radeon_driver_unload(struct drm_device *dev)
2182 {
2183 drm_radeon_private_t *dev_priv = dev->dev_private;
2184
2185 DRM_DEBUG("\n");
2186
2187 drm_rmmap(dev, dev_priv->mmio);
2188
2189 kfree(dev_priv);
2190
2191 dev->dev_private = NULL;
2192 return 0;
2193 }
2194
2195 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2196 {
2197 int i;
2198 u32 *ring;
2199 int tail_aligned;
2200
2201 /* check if the ring is padded out to 16-dword alignment */
2202
2203 tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1);
2204 if (tail_aligned) {
2205 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
2206
2207 ring = dev_priv->ring.start;
2208 /* pad with some CP_PACKET2 */
2209 for (i = 0; i < num_p2; i++)
2210 ring[dev_priv->ring.tail + i] = CP_PACKET2();
2211
2212 dev_priv->ring.tail += i;
2213
2214 dev_priv->ring.space -= num_p2 * sizeof(u32);
2215 }
2216
2217 dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2218
2219 DRM_MEMORYBARRIER();
2220 GET_RING_HEAD( dev_priv );
2221
2222 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2223 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2224 /* read from PCI bus to ensure correct posting */
2225 RADEON_READ(R600_CP_RB_RPTR);
2226 } else {
2227 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2228 /* read from PCI bus to ensure correct posting */
2229 RADEON_READ(RADEON_CP_RB_RPTR);
2230 }
2231 }
Tomato firmware and modifications.