2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
28 #include "radeon_drm.h"
32 #include "r600_blit_shaders.h"
34 #define DI_PT_RECTLIST 0x11
35 #define DI_INDEX_SIZE_16_BIT 0x0
36 #define DI_SRC_SEL_AUTO_INDEX 0x2
40 #define FMT_8_8_8_8 0x1a
42 #define COLOR_5_6_5 0x8
43 #define COLOR_8_8_8_8 0x1a
45 /* emits 21 on rv770+, 23 on r600 */
47 set_render_target(struct radeon_device
*rdev
, int format
,
48 int w
, int h
, u64 gpu_addr
)
57 cb_color_info
= ((format
<< 2) | (1 << 27));
59 slice
= ((w
* h
) / 64) - 1;
61 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
62 radeon_ring_write(rdev
, (CB_COLOR0_BASE
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
63 radeon_ring_write(rdev
, gpu_addr
>> 8);
65 if (rdev
->family
> CHIP_R600
&& rdev
->family
< CHIP_RV770
) {
66 radeon_ring_write(rdev
, PACKET3(PACKET3_SURFACE_BASE_UPDATE
, 0));
67 radeon_ring_write(rdev
, 2 << 0);
70 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
71 radeon_ring_write(rdev
, (CB_COLOR0_SIZE
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
72 radeon_ring_write(rdev
, (pitch
<< 0) | (slice
<< 10));
74 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
75 radeon_ring_write(rdev
, (CB_COLOR0_VIEW
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
76 radeon_ring_write(rdev
, 0);
78 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
79 radeon_ring_write(rdev
, (CB_COLOR0_INFO
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
80 radeon_ring_write(rdev
, cb_color_info
);
82 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
83 radeon_ring_write(rdev
, (CB_COLOR0_TILE
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
84 radeon_ring_write(rdev
, 0);
86 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
87 radeon_ring_write(rdev
, (CB_COLOR0_FRAG
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
88 radeon_ring_write(rdev
, 0);
90 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
91 radeon_ring_write(rdev
, (CB_COLOR0_MASK
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
92 radeon_ring_write(rdev
, 0);
97 cp_set_surface_sync(struct radeon_device
*rdev
,
98 u32 sync_type
, u32 size
,
103 if (size
== 0xffffffff)
104 cp_coher_size
= 0xffffffff;
106 cp_coher_size
= ((size
+ 255) >> 8);
108 radeon_ring_write(rdev
, PACKET3(PACKET3_SURFACE_SYNC
, 3));
109 radeon_ring_write(rdev
, sync_type
);
110 radeon_ring_write(rdev
, cp_coher_size
);
111 radeon_ring_write(rdev
, mc_addr
>> 8);
112 radeon_ring_write(rdev
, 10); /* poll interval */
115 /* emits 21dw + 1 surface sync = 26dw */
117 set_shaders(struct radeon_device
*rdev
)
120 u32 sq_pgm_resources
;
122 /* setup shader regs */
123 sq_pgm_resources
= (1 << 0);
126 gpu_addr
= rdev
->r600_blit
.shader_gpu_addr
+ rdev
->r600_blit
.vs_offset
;
127 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
128 radeon_ring_write(rdev
, (SQ_PGM_START_VS
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
129 radeon_ring_write(rdev
, gpu_addr
>> 8);
131 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
132 radeon_ring_write(rdev
, (SQ_PGM_RESOURCES_VS
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
133 radeon_ring_write(rdev
, sq_pgm_resources
);
135 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
136 radeon_ring_write(rdev
, (SQ_PGM_CF_OFFSET_VS
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
137 radeon_ring_write(rdev
, 0);
140 gpu_addr
= rdev
->r600_blit
.shader_gpu_addr
+ rdev
->r600_blit
.ps_offset
;
141 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
142 radeon_ring_write(rdev
, (SQ_PGM_START_PS
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
143 radeon_ring_write(rdev
, gpu_addr
>> 8);
145 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
146 radeon_ring_write(rdev
, (SQ_PGM_RESOURCES_PS
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
147 radeon_ring_write(rdev
, sq_pgm_resources
| (1 << 28));
149 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
150 radeon_ring_write(rdev
, (SQ_PGM_EXPORTS_PS
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
151 radeon_ring_write(rdev
, 2);
153 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
154 radeon_ring_write(rdev
, (SQ_PGM_CF_OFFSET_PS
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
155 radeon_ring_write(rdev
, 0);
157 gpu_addr
= rdev
->r600_blit
.shader_gpu_addr
+ rdev
->r600_blit
.vs_offset
;
158 cp_set_surface_sync(rdev
, PACKET3_SH_ACTION_ENA
, 512, gpu_addr
);
161 /* emits 9 + 1 sync (5) = 14*/
163 set_vtx_resource(struct radeon_device
*rdev
, u64 gpu_addr
)
165 u32 sq_vtx_constant_word2
;
167 sq_vtx_constant_word2
= ((upper_32_bits(gpu_addr
) & 0xff) | (16 << 8));
169 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_RESOURCE
, 7));
170 radeon_ring_write(rdev
, 0x460);
171 radeon_ring_write(rdev
, gpu_addr
& 0xffffffff);
172 radeon_ring_write(rdev
, 48 - 1);
173 radeon_ring_write(rdev
, sq_vtx_constant_word2
);
174 radeon_ring_write(rdev
, 1 << 0);
175 radeon_ring_write(rdev
, 0);
176 radeon_ring_write(rdev
, 0);
177 radeon_ring_write(rdev
, SQ_TEX_VTX_VALID_BUFFER
<< 30);
179 if ((rdev
->family
== CHIP_RV610
) ||
180 (rdev
->family
== CHIP_RV620
) ||
181 (rdev
->family
== CHIP_RS780
) ||
182 (rdev
->family
== CHIP_RS880
) ||
183 (rdev
->family
== CHIP_RV710
))
184 cp_set_surface_sync(rdev
,
185 PACKET3_TC_ACTION_ENA
, 48, gpu_addr
);
187 cp_set_surface_sync(rdev
,
188 PACKET3_VC_ACTION_ENA
, 48, gpu_addr
);
193 set_tex_resource(struct radeon_device
*rdev
,
194 int format
, int w
, int h
, int pitch
,
197 uint32_t sq_tex_resource_word0
, sq_tex_resource_word1
, sq_tex_resource_word4
;
202 sq_tex_resource_word0
= (1 << 0);
203 sq_tex_resource_word0
|= ((((pitch
>> 3) - 1) << 8) |
206 sq_tex_resource_word1
= (format
<< 26);
207 sq_tex_resource_word1
|= ((h
- 1) << 0);
209 sq_tex_resource_word4
= ((1 << 14) |
215 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_RESOURCE
, 7));
216 radeon_ring_write(rdev
, 0);
217 radeon_ring_write(rdev
, sq_tex_resource_word0
);
218 radeon_ring_write(rdev
, sq_tex_resource_word1
);
219 radeon_ring_write(rdev
, gpu_addr
>> 8);
220 radeon_ring_write(rdev
, gpu_addr
>> 8);
221 radeon_ring_write(rdev
, sq_tex_resource_word4
);
222 radeon_ring_write(rdev
, 0);
223 radeon_ring_write(rdev
, SQ_TEX_VTX_VALID_TEXTURE
<< 30);
228 set_scissors(struct radeon_device
*rdev
, int x1
, int y1
,
231 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONTEXT_REG
, 2));
232 radeon_ring_write(rdev
, (PA_SC_SCREEN_SCISSOR_TL
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
233 radeon_ring_write(rdev
, (x1
<< 0) | (y1
<< 16));
234 radeon_ring_write(rdev
, (x2
<< 0) | (y2
<< 16));
236 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONTEXT_REG
, 2));
237 radeon_ring_write(rdev
, (PA_SC_GENERIC_SCISSOR_TL
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
238 radeon_ring_write(rdev
, (x1
<< 0) | (y1
<< 16) | (1 << 31));
239 radeon_ring_write(rdev
, (x2
<< 0) | (y2
<< 16));
241 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONTEXT_REG
, 2));
242 radeon_ring_write(rdev
, (PA_SC_WINDOW_SCISSOR_TL
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
243 radeon_ring_write(rdev
, (x1
<< 0) | (y1
<< 16) | (1 << 31));
244 radeon_ring_write(rdev
, (x2
<< 0) | (y2
<< 16));
249 draw_auto(struct radeon_device
*rdev
)
251 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
252 radeon_ring_write(rdev
, (VGT_PRIMITIVE_TYPE
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2);
253 radeon_ring_write(rdev
, DI_PT_RECTLIST
);
255 radeon_ring_write(rdev
, PACKET3(PACKET3_INDEX_TYPE
, 0));
256 radeon_ring_write(rdev
, DI_INDEX_SIZE_16_BIT
);
258 radeon_ring_write(rdev
, PACKET3(PACKET3_NUM_INSTANCES
, 0));
259 radeon_ring_write(rdev
, 1);
261 radeon_ring_write(rdev
, PACKET3(PACKET3_DRAW_INDEX_AUTO
, 1));
262 radeon_ring_write(rdev
, 3);
263 radeon_ring_write(rdev
, DI_SRC_SEL_AUTO_INDEX
);
269 set_default_state(struct radeon_device
*rdev
)
271 u32 sq_config
, sq_gpr_resource_mgmt_1
, sq_gpr_resource_mgmt_2
;
272 u32 sq_thread_resource_mgmt
, sq_stack_resource_mgmt_1
, sq_stack_resource_mgmt_2
;
273 int num_ps_gprs
, num_vs_gprs
, num_temp_gprs
, num_gs_gprs
, num_es_gprs
;
274 int num_ps_threads
, num_vs_threads
, num_gs_threads
, num_es_threads
;
275 int num_ps_stack_entries
, num_vs_stack_entries
, num_gs_stack_entries
, num_es_stack_entries
;
279 switch (rdev
->family
) {
286 num_ps_threads
= 136;
290 num_ps_stack_entries
= 128;
291 num_vs_stack_entries
= 128;
292 num_gs_stack_entries
= 0;
293 num_es_stack_entries
= 0;
302 num_ps_threads
= 144;
306 num_ps_stack_entries
= 40;
307 num_vs_stack_entries
= 40;
308 num_gs_stack_entries
= 32;
309 num_es_stack_entries
= 16;
321 num_ps_threads
= 136;
325 num_ps_stack_entries
= 40;
326 num_vs_stack_entries
= 40;
327 num_gs_stack_entries
= 32;
328 num_es_stack_entries
= 16;
336 num_ps_threads
= 136;
340 num_ps_stack_entries
= 40;
341 num_vs_stack_entries
= 40;
342 num_gs_stack_entries
= 32;
343 num_es_stack_entries
= 16;
351 num_ps_threads
= 188;
355 num_ps_stack_entries
= 256;
356 num_vs_stack_entries
= 256;
357 num_gs_stack_entries
= 0;
358 num_es_stack_entries
= 0;
367 num_ps_threads
= 188;
371 num_ps_stack_entries
= 128;
372 num_vs_stack_entries
= 128;
373 num_gs_stack_entries
= 0;
374 num_es_stack_entries
= 0;
382 num_ps_threads
= 144;
386 num_ps_stack_entries
= 128;
387 num_vs_stack_entries
= 128;
388 num_gs_stack_entries
= 0;
389 num_es_stack_entries
= 0;
393 if ((rdev
->family
== CHIP_RV610
) ||
394 (rdev
->family
== CHIP_RV620
) ||
395 (rdev
->family
== CHIP_RS780
) ||
396 (rdev
->family
== CHIP_RS880
) ||
397 (rdev
->family
== CHIP_RV710
))
400 sq_config
= VC_ENABLE
;
402 sq_config
|= (DX9_CONSTS
|
403 ALU_INST_PREFER_VECTOR
|
409 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(num_ps_gprs
) |
410 NUM_VS_GPRS(num_vs_gprs
) |
411 NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
));
412 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(num_gs_gprs
) |
413 NUM_ES_GPRS(num_es_gprs
));
414 sq_thread_resource_mgmt
= (NUM_PS_THREADS(num_ps_threads
) |
415 NUM_VS_THREADS(num_vs_threads
) |
416 NUM_GS_THREADS(num_gs_threads
) |
417 NUM_ES_THREADS(num_es_threads
));
418 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(num_ps_stack_entries
) |
419 NUM_VS_STACK_ENTRIES(num_vs_stack_entries
));
420 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(num_gs_stack_entries
) |
421 NUM_ES_STACK_ENTRIES(num_es_stack_entries
));
423 /* emit an IB pointing at default state */
424 dwords
= ALIGN(rdev
->r600_blit
.state_len
, 0x10);
425 gpu_addr
= rdev
->r600_blit
.shader_gpu_addr
+ rdev
->r600_blit
.state_offset
;
426 radeon_ring_write(rdev
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
427 radeon_ring_write(rdev
, gpu_addr
& 0xFFFFFFFC);
428 radeon_ring_write(rdev
, upper_32_bits(gpu_addr
) & 0xFF);
429 radeon_ring_write(rdev
, dwords
);
432 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONFIG_REG
, 6));
433 radeon_ring_write(rdev
, (SQ_CONFIG
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2);
434 radeon_ring_write(rdev
, sq_config
);
435 radeon_ring_write(rdev
, sq_gpr_resource_mgmt_1
);
436 radeon_ring_write(rdev
, sq_gpr_resource_mgmt_2
);
437 radeon_ring_write(rdev
, sq_thread_resource_mgmt
);
438 radeon_ring_write(rdev
, sq_stack_resource_mgmt_1
);
439 radeon_ring_write(rdev
, sq_stack_resource_mgmt_2
);
442 static inline uint32_t i2f(uint32_t input
)
444 u32 result
, i
, exponent
, fraction
;
446 if ((input
& 0x3fff) == 0)
447 result
= 0; /* 0 is a special case */
449 exponent
= 140; /* exponent biased by 127; */
450 fraction
= (input
& 0x3fff) << 10; /* cheat and only
451 handle numbers below 2^^15 */
452 for (i
= 0; i
< 14; i
++) {
453 if (fraction
& 0x800000)
456 fraction
= fraction
<< 1; /* keep
457 shifting left until top bit = 1 */
458 exponent
= exponent
- 1;
461 result
= exponent
<< 23 | (fraction
& 0x7fffff); /* mask
462 off top bit; assumed 1 */
467 int r600_blit_init(struct radeon_device
*rdev
)
473 int num_packet2s
= 0;
475 /* don't reinitialize blit */
476 if (rdev
->r600_blit
.shader_obj
)
478 mutex_init(&rdev
->r600_blit
.mutex
);
479 rdev
->r600_blit
.state_offset
= 0;
481 if (rdev
->family
>= CHIP_RV770
)
482 rdev
->r600_blit
.state_len
= r7xx_default_size
;
484 rdev
->r600_blit
.state_len
= r6xx_default_size
;
486 dwords
= rdev
->r600_blit
.state_len
;
487 while (dwords
& 0xf) {
488 packet2s
[num_packet2s
++] = PACKET2(0);
492 obj_size
= dwords
* 4;
493 obj_size
= ALIGN(obj_size
, 256);
495 rdev
->r600_blit
.vs_offset
= obj_size
;
496 obj_size
+= r6xx_vs_size
* 4;
497 obj_size
= ALIGN(obj_size
, 256);
499 rdev
->r600_blit
.ps_offset
= obj_size
;
500 obj_size
+= r6xx_ps_size
* 4;
501 obj_size
= ALIGN(obj_size
, 256);
503 r
= radeon_bo_create(rdev
, NULL
, obj_size
, true, RADEON_GEM_DOMAIN_VRAM
,
504 &rdev
->r600_blit
.shader_obj
);
506 DRM_ERROR("r600 failed to allocate shader\n");
510 DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
512 rdev
->r600_blit
.vs_offset
, rdev
->r600_blit
.ps_offset
);
514 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
515 if (unlikely(r
!= 0))
517 r
= radeon_bo_kmap(rdev
->r600_blit
.shader_obj
, &ptr
);
519 DRM_ERROR("failed to map blit object %d\n", r
);
522 if (rdev
->family
>= CHIP_RV770
)
523 memcpy_toio(ptr
+ rdev
->r600_blit
.state_offset
,
524 r7xx_default_state
, rdev
->r600_blit
.state_len
* 4);
526 memcpy_toio(ptr
+ rdev
->r600_blit
.state_offset
,
527 r6xx_default_state
, rdev
->r600_blit
.state_len
* 4);
529 memcpy_toio(ptr
+ rdev
->r600_blit
.state_offset
+ (rdev
->r600_blit
.state_len
* 4),
530 packet2s
, num_packet2s
* 4);
531 memcpy(ptr
+ rdev
->r600_blit
.vs_offset
, r6xx_vs
, r6xx_vs_size
* 4);
532 memcpy(ptr
+ rdev
->r600_blit
.ps_offset
, r6xx_ps
, r6xx_ps_size
* 4);
533 radeon_bo_kunmap(rdev
->r600_blit
.shader_obj
);
534 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
535 rdev
->mc
.active_vram_size
= rdev
->mc
.real_vram_size
;
539 void r600_blit_fini(struct radeon_device
*rdev
)
543 rdev
->mc
.active_vram_size
= rdev
->mc
.visible_vram_size
;
544 if (rdev
->r600_blit
.shader_obj
== NULL
)
546 /* If we can't reserve the bo, unref should be enough to destroy
547 * it when it becomes idle.
549 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
551 radeon_bo_unpin(rdev
->r600_blit
.shader_obj
);
552 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
554 radeon_bo_unref(&rdev
->r600_blit
.shader_obj
);
557 int r600_vb_ib_get(struct radeon_device
*rdev
)
560 r
= radeon_ib_get(rdev
, &rdev
->r600_blit
.vb_ib
);
562 DRM_ERROR("failed to get IB for vertex buffer\n");
566 rdev
->r600_blit
.vb_total
= 64*1024;
567 rdev
->r600_blit
.vb_used
= 0;
571 void r600_vb_ib_put(struct radeon_device
*rdev
)
573 radeon_fence_emit(rdev
, rdev
->r600_blit
.vb_ib
->fence
);
574 radeon_ib_free(rdev
, &rdev
->r600_blit
.vb_ib
);
577 int r600_blit_prepare_copy(struct radeon_device
*rdev
, int size_bytes
)
580 int ring_size
, line_size
;
582 /* loops of emits 64 + fence emit possible */
583 int dwords_per_loop
= 76, num_loops
;
585 r
= r600_vb_ib_get(rdev
);
589 /* set_render_target emits 2 extra dwords on rv6xx */
590 if (rdev
->family
> CHIP_R600
&& rdev
->family
< CHIP_RV770
)
591 dwords_per_loop
+= 2;
593 /* 8 bpp vs 32 bpp for xfer unit */
599 max_size
= 8192 * line_size
;
601 /* major loops cover the max size transfer */
602 num_loops
= ((size_bytes
+ max_size
) / max_size
);
603 /* minor loops cover the extra non aligned bits */
604 num_loops
+= ((size_bytes
% line_size
) ? 1 : 0);
605 /* calculate number of loops correctly */
606 ring_size
= num_loops
* dwords_per_loop
;
607 /* set default + shaders */
608 ring_size
+= 40; /* shaders + def state */
609 ring_size
+= 10; /* fence emit for VB IB */
610 ring_size
+= 5; /* done copy */
611 ring_size
+= 10; /* fence emit for done copy */
612 r
= radeon_ring_lock(rdev
, ring_size
);
616 set_default_state(rdev
); /* 14 */
617 set_shaders(rdev
); /* 26 */
621 void r600_blit_done_copy(struct radeon_device
*rdev
, struct radeon_fence
*fence
)
625 if (rdev
->r600_blit
.vb_ib
)
626 r600_vb_ib_put(rdev
);
629 r
= radeon_fence_emit(rdev
, fence
);
631 radeon_ring_unlock_commit(rdev
);
634 void r600_kms_blit_copy(struct radeon_device
*rdev
,
635 u64 src_gpu_addr
, u64 dst_gpu_addr
,
642 DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr
, dst_gpu_addr
,
643 size_bytes
, rdev
->r600_blit
.vb_used
);
644 vb
= (u32
*)(rdev
->r600_blit
.vb_ib
->ptr
+ rdev
->r600_blit
.vb_used
);
645 if ((size_bytes
& 3) || (src_gpu_addr
& 3) || (dst_gpu_addr
& 3)) {
649 int cur_size
= size_bytes
;
650 int src_x
= src_gpu_addr
& 255;
651 int dst_x
= dst_gpu_addr
& 255;
653 src_gpu_addr
= src_gpu_addr
& ~255ULL;
654 dst_gpu_addr
= dst_gpu_addr
& ~255ULL;
656 if (!src_x
&& !dst_x
) {
657 h
= (cur_size
/ max_bytes
);
663 cur_size
= max_bytes
;
665 if (cur_size
> max_bytes
)
666 cur_size
= max_bytes
;
667 if (cur_size
> (max_bytes
- dst_x
))
668 cur_size
= (max_bytes
- dst_x
);
669 if (cur_size
> (max_bytes
- src_x
))
670 cur_size
= (max_bytes
- src_x
);
673 if ((rdev
->r600_blit
.vb_used
+ 48) > rdev
->r600_blit
.vb_total
) {
688 vb
[8] = i2f(dst_x
+ cur_size
);
690 vb
[10] = i2f(src_x
+ cur_size
);
694 set_tex_resource(rdev
, FMT_8
,
695 src_x
+ cur_size
, h
, src_x
+ cur_size
,
699 cp_set_surface_sync(rdev
,
700 PACKET3_TC_ACTION_ENA
, (src_x
+ cur_size
* h
), src_gpu_addr
);
703 set_render_target(rdev
, COLOR_8
,
708 set_scissors(rdev
, dst_x
, 0, dst_x
+ cur_size
, h
);
711 vb_gpu_addr
= rdev
->r600_blit
.vb_ib
->gpu_addr
+ rdev
->r600_blit
.vb_used
;
712 set_vtx_resource(rdev
, vb_gpu_addr
);
718 cp_set_surface_sync(rdev
,
719 PACKET3_CB_ACTION_ENA
| PACKET3_CB0_DEST_BASE_ENA
,
720 cur_size
* h
, dst_gpu_addr
);
723 rdev
->r600_blit
.vb_used
+= 12 * 4;
725 src_gpu_addr
+= cur_size
* h
;
726 dst_gpu_addr
+= cur_size
* h
;
727 size_bytes
-= cur_size
* h
;
730 max_bytes
= 8192 * 4;
733 int cur_size
= size_bytes
;
734 int src_x
= (src_gpu_addr
& 255);
735 int dst_x
= (dst_gpu_addr
& 255);
737 src_gpu_addr
= src_gpu_addr
& ~255ULL;
738 dst_gpu_addr
= dst_gpu_addr
& ~255ULL;
740 if (!src_x
&& !dst_x
) {
741 h
= (cur_size
/ max_bytes
);
747 cur_size
= max_bytes
;
749 if (cur_size
> max_bytes
)
750 cur_size
= max_bytes
;
751 if (cur_size
> (max_bytes
- dst_x
))
752 cur_size
= (max_bytes
- dst_x
);
753 if (cur_size
> (max_bytes
- src_x
))
754 cur_size
= (max_bytes
- src_x
);
757 if ((rdev
->r600_blit
.vb_used
+ 48) > rdev
->r600_blit
.vb_total
) {
761 vb
[0] = i2f(dst_x
/ 4);
763 vb
[2] = i2f(src_x
/ 4);
766 vb
[4] = i2f(dst_x
/ 4);
768 vb
[6] = i2f(src_x
/ 4);
771 vb
[8] = i2f((dst_x
+ cur_size
) / 4);
773 vb
[10] = i2f((src_x
+ cur_size
) / 4);
777 set_tex_resource(rdev
, FMT_8_8_8_8
,
778 (src_x
+ cur_size
) / 4,
779 h
, (src_x
+ cur_size
) / 4,
782 cp_set_surface_sync(rdev
,
783 PACKET3_TC_ACTION_ENA
, (src_x
+ cur_size
* h
), src_gpu_addr
);
786 set_render_target(rdev
, COLOR_8_8_8_8
,
787 (dst_x
+ cur_size
) / 4, h
,
791 set_scissors(rdev
, (dst_x
/ 4), 0, (dst_x
+ cur_size
/ 4), h
);
793 /* Vertex buffer setup 14 */
794 vb_gpu_addr
= rdev
->r600_blit
.vb_ib
->gpu_addr
+ rdev
->r600_blit
.vb_used
;
795 set_vtx_resource(rdev
, vb_gpu_addr
);
801 cp_set_surface_sync(rdev
,
802 PACKET3_CB_ACTION_ENA
| PACKET3_CB0_DEST_BASE_ENA
,
803 cur_size
* h
, dst_gpu_addr
);
805 /* 78 ring dwords per loop */
807 rdev
->r600_blit
.vb_used
+= 12 * 4;
809 src_gpu_addr
+= cur_size
* h
;
810 dst_gpu_addr
+= cur_size
* h
;
811 size_bytes
-= cur_size
* h
;