release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/gpu/drm/radeon/r420.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "radeon_reg.h"
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include "atom.h"
  35 #include "r100d.h"
  36 #include "r420d.h"
  37 #include "r420_reg_safe.h"
  38
  39 void r420_pm_init_profile(struct radeon_device *rdev)
  40 {
  41         /* default */
  42         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
  43         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  44         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
  45         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
  46         /* low sh */
  47         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
  48         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
  49         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
  50         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
  51         /* mid sh */
  52         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
  53         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
  54         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
  55         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
  56         /* high sh */
  57         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
  58         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  59         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
  60         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
  61         /* low mh */
  62         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
  63         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  64         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
  65         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
  66         /* mid mh */
  67         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
  68         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  69         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
  70         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
  71         /* high mh */
  72         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
  73         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  74         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
  75         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
  76 }
  77
  78 static void r420_set_reg_safe(struct radeon_device *rdev)
  79 {
  80         rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
  81         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
  82 }
  83
  84 void r420_pipes_init(struct radeon_device *rdev)
  85 {
  86         unsigned tmp;
  87         unsigned gb_pipe_select;
  88         unsigned num_pipes;
  89
  90         WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
  91                (1 << 2) | (1 << 3));
  92         /* add idle wait as per freedesktop.org bug 24041 */
  93         if (r100_gui_wait_for_idle(rdev)) {
  94                 printk(KERN_WARNING "Failed to wait GUI idle while "
  95                        "programming pipes. Bad things might happen.\n");
  96         }
  97         /* get max number of pipes */
  98         gb_pipe_select = RREG32(0x402C);
  99         num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
 100
 101         /* SE chips have 1 pipe */
 102         if ((rdev->pdev->device == 0x5e4c) ||
 103             (rdev->pdev->device == 0x5e4f))
 104                 num_pipes = 1;
 105
 106         rdev->num_gb_pipes = num_pipes;
 107         tmp = 0;
 108         switch (num_pipes) {
 109         default:
 110                 /* force to 1 pipe */
 111                 num_pipes = 1;
 112         case 1:
 113                 tmp = (0 << 1);
 114                 break;
 115         case 2:
 116                 tmp = (3 << 1);
 117                 break;
 118         case 3:
 119                 tmp = (6 << 1);
 120                 break;
 121         case 4:
 122                 tmp = (7 << 1);
 123                 break;
 124         }
 125         WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
 126         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
 127         tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
 128         WREG32(R300_GB_TILE_CONFIG, tmp);
 129         if (r100_gui_wait_for_idle(rdev)) {
 130                 printk(KERN_WARNING "Failed to wait GUI idle while "
 131                        "programming pipes. Bad things might happen.\n");
 132         }
 133
 134         tmp = RREG32(R300_DST_PIPE_CONFIG);
 135         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
 136
 137         WREG32(R300_RB2D_DSTCACHE_MODE,
 138                RREG32(R300_RB2D_DSTCACHE_MODE) |
 139                R300_DC_AUTOFLUSH_ENABLE |
 140                R300_DC_DC_DISABLE_IGNORE_PE);
 141
 142         if (r100_gui_wait_for_idle(rdev)) {
 143                 printk(KERN_WARNING "Failed to wait GUI idle while "
 144                        "programming pipes. Bad things might happen.\n");
 145         }
 146
 147         if (rdev->family == CHIP_RV530) {
 148                 tmp = RREG32(RV530_GB_PIPE_SELECT2);
 149                 if ((tmp & 3) == 3)
 150                         rdev->num_z_pipes = 2;
 151                 else
 152                         rdev->num_z_pipes = 1;
 153         } else
 154                 rdev->num_z_pipes = 1;
 155
 156         DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
 157                  rdev->num_gb_pipes, rdev->num_z_pipes);
 158 }
 159
 160 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
 161 {
 162         u32 r;
 163
 164         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
 165         r = RREG32(R_0001FC_MC_IND_DATA);
 166         return r;
 167 }
 168
 169 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 170 {
 171         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
 172                 S_0001F8_MC_IND_WR_EN(1));
 173         WREG32(R_0001FC_MC_IND_DATA, v);
 174 }
 175
 176 static void r420_debugfs(struct radeon_device *rdev)
 177 {
 178         if (r100_debugfs_rbbm_init(rdev)) {
 179                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 180         }
 181         if (r420_debugfs_pipes_info_init(rdev)) {
 182                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
 183         }
 184 }
 185
 186 static void r420_clock_resume(struct radeon_device *rdev)
 187 {
 188         u32 sclk_cntl;
 189
 190         if (radeon_dynclks != -1 && radeon_dynclks)
 191                 radeon_atom_set_clock_gating(rdev, 1);
 192         sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
 193         sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
 194         if (rdev->family == CHIP_R420)
 195                 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
 196         WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
 197 }
 198
 199 static void r420_cp_errata_init(struct radeon_device *rdev)
 200 {
 201         radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
 202         radeon_ring_lock(rdev, 8);
 203         radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
 204         radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
 205         radeon_ring_write(rdev, 0xDEADBEEF);
 206         radeon_ring_unlock_commit(rdev);
 207 }
 208
 209 static void r420_cp_errata_fini(struct radeon_device *rdev)
 210 {
 211         /* Catch the RESYNC we dispatched all the way back,
 212          * at the very beginning of the CP init.
 213          */
 214         radeon_ring_lock(rdev, 8);
 215         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 216         radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
 217         radeon_ring_unlock_commit(rdev);
 218         radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
 219 }
 220
 221 static int r420_startup(struct radeon_device *rdev)
 222 {
 223         int r;
 224
 225         /* set common regs */
 226         r100_set_common_regs(rdev);
 227         /* program mc */
 228         r300_mc_program(rdev);
 229         /* Resume clock */
 230         r420_clock_resume(rdev);
 231         /* Initialize GART (initialize after TTM so we can allocate
 232          * memory through TTM but finalize after TTM) */
 233         if (rdev->flags & RADEON_IS_PCIE) {
 234                 r = rv370_pcie_gart_enable(rdev);
 235                 if (r)
 236                         return r;
 237         }
 238         if (rdev->flags & RADEON_IS_PCI) {
 239                 r = r100_pci_gart_enable(rdev);
 240                 if (r)
 241                         return r;
 242         }
 243         r420_pipes_init(rdev);
 244         /* Enable IRQ */
 245         r100_irq_set(rdev);
 246         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 247         /* 1M ring buffer */
 248         r = r100_cp_init(rdev, 1024 * 1024);
 249         if (r) {
 250                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 251                 return r;
 252         }
 253         r420_cp_errata_init(rdev);
 254         r = r100_wb_init(rdev);
 255         if (r) {
 256                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 257         }
 258         r = r100_ib_init(rdev);
 259         if (r) {
 260                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 261                 return r;
 262         }
 263         return 0;
 264 }
 265
 266 int r420_resume(struct radeon_device *rdev)
 267 {
 268         /* Make sur GART are not working */
 269         if (rdev->flags & RADEON_IS_PCIE)
 270                 rv370_pcie_gart_disable(rdev);
 271         if (rdev->flags & RADEON_IS_PCI)
 272                 r100_pci_gart_disable(rdev);
 273         /* Resume clock before doing reset */
 274         r420_clock_resume(rdev);
 275         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 276         if (radeon_asic_reset(rdev)) {
 277                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 278                         RREG32(R_000E40_RBBM_STATUS),
 279                         RREG32(R_0007C0_CP_STAT));
 280         }
 281         /* check if cards are posted or not */
 282         if (rdev->is_atom_bios) {
 283                 atom_asic_init(rdev->mode_info.atom_context);
 284         } else {
 285                 radeon_combios_asic_init(rdev->ddev);
 286         }
 287         /* Resume clock after posting */
 288         r420_clock_resume(rdev);
 289         /* Initialize surface registers */
 290         radeon_surface_init(rdev);
 291         return r420_startup(rdev);
 292 }
 293
 294 int r420_suspend(struct radeon_device *rdev)
 295 {
 296         r420_cp_errata_fini(rdev);
 297         r100_cp_disable(rdev);
 298         r100_wb_disable(rdev);
 299         r100_irq_disable(rdev);
 300         if (rdev->flags & RADEON_IS_PCIE)
 301                 rv370_pcie_gart_disable(rdev);
 302         if (rdev->flags & RADEON_IS_PCI)
 303                 r100_pci_gart_disable(rdev);
 304         return 0;
 305 }
 306
 307 void r420_fini(struct radeon_device *rdev)
 308 {
 309         r100_cp_fini(rdev);
 310         r100_wb_fini(rdev);
 311         r100_ib_fini(rdev);
 312         radeon_gem_fini(rdev);
 313         if (rdev->flags & RADEON_IS_PCIE)
 314                 rv370_pcie_gart_fini(rdev);
 315         if (rdev->flags & RADEON_IS_PCI)
 316                 r100_pci_gart_fini(rdev);
 317         radeon_agp_fini(rdev);
 318         radeon_irq_kms_fini(rdev);
 319         radeon_fence_driver_fini(rdev);
 320         radeon_bo_fini(rdev);
 321         if (rdev->is_atom_bios) {
 322                 radeon_atombios_fini(rdev);
 323         } else {
 324                 radeon_combios_fini(rdev);
 325         }
 326         kfree(rdev->bios);
 327         rdev->bios = NULL;
 328 }
 329
 330 int r420_init(struct radeon_device *rdev)
 331 {
 332         int r;
 333
 334         /* Initialize scratch registers */
 335         radeon_scratch_init(rdev);
 336         /* Initialize surface registers */
 337         radeon_surface_init(rdev);
 338         /* TODO: disable VGA need to use VGA request */
 339         /* restore some register to sane defaults */
 340         r100_restore_sanity(rdev);
 341         /* BIOS*/
 342         if (!radeon_get_bios(rdev)) {
 343                 if (ASIC_IS_AVIVO(rdev))
 344                         return -EINVAL;
 345         }
 346         if (rdev->is_atom_bios) {
 347                 r = radeon_atombios_init(rdev);
 348                 if (r) {
 349                         return r;
 350                 }
 351         } else {
 352                 r = radeon_combios_init(rdev);
 353                 if (r) {
 354                         return r;
 355                 }
 356         }
 357         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 358         if (radeon_asic_reset(rdev)) {
 359                 dev_warn(rdev->dev,
 360                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 361                         RREG32(R_000E40_RBBM_STATUS),
 362                         RREG32(R_0007C0_CP_STAT));
 363         }
 364         /* check if cards are posted or not */
 365         if (radeon_boot_test_post_card(rdev) == false)
 366                 return -EINVAL;
 367
 368         /* Initialize clocks */
 369         radeon_get_clock_info(rdev->ddev);
 370         /* initialize AGP */
 371         if (rdev->flags & RADEON_IS_AGP) {
 372                 r = radeon_agp_init(rdev);
 373                 if (r) {
 374                         radeon_agp_disable(rdev);
 375                 }
 376         }
 377         /* initialize memory controller */
 378         r300_mc_init(rdev);
 379         r420_debugfs(rdev);
 380         /* Fence driver */
 381         r = radeon_fence_driver_init(rdev);
 382         if (r) {
 383                 return r;
 384         }
 385         r = radeon_irq_kms_init(rdev);
 386         if (r) {
 387                 return r;
 388         }
 389         /* Memory manager */
 390         r = radeon_bo_init(rdev);
 391         if (r) {
 392                 return r;
 393         }
 394         if (rdev->family == CHIP_R420)
 395                 r100_enable_bm(rdev);
 396
 397         if (rdev->flags & RADEON_IS_PCIE) {
 398                 r = rv370_pcie_gart_init(rdev);
 399                 if (r)
 400                         return r;
 401         }
 402         if (rdev->flags & RADEON_IS_PCI) {
 403                 r = r100_pci_gart_init(rdev);
 404                 if (r)
 405                         return r;
 406         }
 407         r420_set_reg_safe(rdev);
 408         rdev->accel_working = true;
 409         r = r420_startup(rdev);
 410         if (r) {
 411                 /* Somethings want wront with the accel init stop accel */
 412                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 413                 r100_cp_fini(rdev);
 414                 r100_wb_fini(rdev);
 415                 r100_ib_fini(rdev);
 416                 radeon_irq_kms_fini(rdev);
 417                 if (rdev->flags & RADEON_IS_PCIE)
 418                         rv370_pcie_gart_fini(rdev);
 419                 if (rdev->flags & RADEON_IS_PCI)
 420                         r100_pci_gart_fini(rdev);
 421                 radeon_agp_fini(rdev);
 422                 rdev->accel_working = false;
 423         }
 424         return 0;
 425 }
 426
 427 /*
 428  * Debugfs info
 429  */
 430 #if defined(CONFIG_DEBUG_FS)
 431 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
 432 {
 433         struct drm_info_node *node = (struct drm_info_node *) m->private;
 434         struct drm_device *dev = node->minor->dev;
 435         struct radeon_device *rdev = dev->dev_private;
 436         uint32_t tmp;
 437
 438         tmp = RREG32(R400_GB_PIPE_SELECT);
 439         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 440         tmp = RREG32(R300_GB_TILE_CONFIG);
 441         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 442         tmp = RREG32(R300_DST_PIPE_CONFIG);
 443         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 444         return 0;
 445 }
 446
 447 static struct drm_info_list r420_pipes_info_list[] = {
 448         {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
 449 };
 450 #endif
 451
 452 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
 453 {
 454 #if defined(CONFIG_DEBUG_FS)
 455         return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
 456 #else
 457         return 0;
 458 #endif
 459 }