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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / gpu / drm / radeon / r100.c
blob22e3cf9b2c67f8c04f6688b02264aac77b60ff5c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "r100d.h"
37 #include "rs100d.h"
38 #include "rv200d.h"
39 #include "rv250d.h"
40 #include "atom.h"
41
42 #include <linux/firmware.h>
43 #include <linux/platform_device.h>
44
45 #include "r100_reg_safe.h"
46 #include "rn50_reg_safe.h"
47
48 /* Firmware Names */
49 #define FIRMWARE_R100 "radeon/R100_cp.bin"
50 #define FIRMWARE_R200 "radeon/R200_cp.bin"
51 #define FIRMWARE_R300 "radeon/R300_cp.bin"
52 #define FIRMWARE_R420 "radeon/R420_cp.bin"
53 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
54 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
55 #define FIRMWARE_R520 "radeon/R520_cp.bin"
56
57 MODULE_FIRMWARE(FIRMWARE_R100);
58 MODULE_FIRMWARE(FIRMWARE_R200);
59 MODULE_FIRMWARE(FIRMWARE_R300);
60 MODULE_FIRMWARE(FIRMWARE_R420);
61 MODULE_FIRMWARE(FIRMWARE_RS690);
62 MODULE_FIRMWARE(FIRMWARE_RS600);
63 MODULE_FIRMWARE(FIRMWARE_R520);
64
65 #include "r100_track.h"
66
67 /* This files gather functions specifics to:
68 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
69 */
70
71 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
72 {
73 int i;
74 rdev->pm.dynpm_can_upclock = true;
75 rdev->pm.dynpm_can_downclock = true;
76
77 switch (rdev->pm.dynpm_planned_action) {
78 case DYNPM_ACTION_MINIMUM:
79 rdev->pm.requested_power_state_index = 0;
80 rdev->pm.dynpm_can_downclock = false;
81 break;
82 case DYNPM_ACTION_DOWNCLOCK:
83 if (rdev->pm.current_power_state_index == 0) {
84 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
85 rdev->pm.dynpm_can_downclock = false;
86 } else {
87 if (rdev->pm.active_crtc_count > 1) {
88 for (i = 0; i < rdev->pm.num_power_states; i++) {
89 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
90 continue;
91 else if (i >= rdev->pm.current_power_state_index) {
92 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
93 break;
94 } else {
95 rdev->pm.requested_power_state_index = i;
96 break;
97 }
98 }
99 } else
100 rdev->pm.requested_power_state_index =
101 rdev->pm.current_power_state_index - 1;
102 }
103 /* don't use the power state if crtcs are active and no display flag is set */
104 if ((rdev->pm.active_crtc_count > 0) &&
105 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
106 RADEON_PM_MODE_NO_DISPLAY)) {
107 rdev->pm.requested_power_state_index++;
108 }
109 break;
110 case DYNPM_ACTION_UPCLOCK:
111 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
112 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
113 rdev->pm.dynpm_can_upclock = false;
114 } else {
115 if (rdev->pm.active_crtc_count > 1) {
116 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
117 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
118 continue;
119 else if (i <= rdev->pm.current_power_state_index) {
120 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
121 break;
122 } else {
123 rdev->pm.requested_power_state_index = i;
124 break;
125 }
126 }
127 } else
128 rdev->pm.requested_power_state_index =
129 rdev->pm.current_power_state_index + 1;
130 }
131 break;
132 case DYNPM_ACTION_DEFAULT:
133 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
134 rdev->pm.dynpm_can_upclock = false;
135 break;
136 case DYNPM_ACTION_NONE:
137 default:
138 DRM_ERROR("Requested mode for not defined action\n");
139 return;
140 }
141 /* only one clock mode per power state */
142 rdev->pm.requested_clock_mode_index = 0;
143
144 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
145 rdev->pm.power_state[rdev->pm.requested_power_state_index].
146 clock_info[rdev->pm.requested_clock_mode_index].sclk,
147 rdev->pm.power_state[rdev->pm.requested_power_state_index].
148 clock_info[rdev->pm.requested_clock_mode_index].mclk,
149 rdev->pm.power_state[rdev->pm.requested_power_state_index].
150 pcie_lanes);
151 }
152
153 void r100_pm_init_profile(struct radeon_device *rdev)
154 {
155 /* default */
156 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
157 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
158 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
159 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
160 /* low sh */
161 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
162 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
163 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
164 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
165 /* mid sh */
166 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
167 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
168 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
169 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
170 /* high sh */
171 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
172 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
173 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
174 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
175 /* low mh */
176 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
177 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
178 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
179 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
180 /* mid mh */
181 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
182 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
183 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
184 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
185 /* high mh */
186 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
187 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
188 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
189 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
190 }
191
192 void r100_pm_misc(struct radeon_device *rdev)
193 {
194 int requested_index = rdev->pm.requested_power_state_index;
195 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
196 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
197 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
198
199 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
200 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
201 tmp = RREG32(voltage->gpio.reg);
202 if (voltage->active_high)
203 tmp |= voltage->gpio.mask;
204 else
205 tmp &= ~(voltage->gpio.mask);
206 WREG32(voltage->gpio.reg, tmp);
207 if (voltage->delay)
208 udelay(voltage->delay);
209 } else {
210 tmp = RREG32(voltage->gpio.reg);
211 if (voltage->active_high)
212 tmp &= ~voltage->gpio.mask;
213 else
214 tmp |= voltage->gpio.mask;
215 WREG32(voltage->gpio.reg, tmp);
216 if (voltage->delay)
217 udelay(voltage->delay);
218 }
219 }
220
221 sclk_cntl = RREG32_PLL(SCLK_CNTL);
222 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
223 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
224 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
225 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
226 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
227 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
228 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
229 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
230 else
231 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
232 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
233 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
234 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
235 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
236 } else
237 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
238
239 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
240 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
241 if (voltage->delay) {
242 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
243 switch (voltage->delay) {
244 case 33:
245 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
246 break;
247 case 66:
248 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
249 break;
250 case 99:
251 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
252 break;
253 case 132:
254 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
255 break;
256 }
257 } else
258 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
259 } else
260 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
261
262 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
263 sclk_cntl &= ~FORCE_HDP;
264 else
265 sclk_cntl |= FORCE_HDP;
266
267 WREG32_PLL(SCLK_CNTL, sclk_cntl);
268 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
269 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
270
271 /* set pcie lanes */
272 if ((rdev->flags & RADEON_IS_PCIE) &&
273 !(rdev->flags & RADEON_IS_IGP) &&
274 rdev->asic->set_pcie_lanes &&
275 (ps->pcie_lanes !=
276 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
277 radeon_set_pcie_lanes(rdev,
278 ps->pcie_lanes);
279 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
280 }
281 }
282
283 void r100_pm_prepare(struct radeon_device *rdev)
284 {
285 struct drm_device *ddev = rdev->ddev;
286 struct drm_crtc *crtc;
287 struct radeon_crtc *radeon_crtc;
288 u32 tmp;
289
290 /* disable any active CRTCs */
291 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
292 radeon_crtc = to_radeon_crtc(crtc);
293 if (radeon_crtc->enabled) {
294 if (radeon_crtc->crtc_id) {
295 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
296 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
297 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
298 } else {
299 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
300 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
301 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
302 }
303 }
304 }
305 }
306
307 void r100_pm_finish(struct radeon_device *rdev)
308 {
309 struct drm_device *ddev = rdev->ddev;
310 struct drm_crtc *crtc;
311 struct radeon_crtc *radeon_crtc;
312 u32 tmp;
313
314 /* enable any active CRTCs */
315 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
316 radeon_crtc = to_radeon_crtc(crtc);
317 if (radeon_crtc->enabled) {
318 if (radeon_crtc->crtc_id) {
319 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
320 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
321 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
322 } else {
323 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
324 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
325 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
326 }
327 }
328 }
329 }
330
331 bool r100_gui_idle(struct radeon_device *rdev)
332 {
333 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
334 return false;
335 else
336 return true;
337 }
338
339 /* hpd for digital panel detect/disconnect */
340 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
341 {
342 bool connected = false;
343
344 switch (hpd) {
345 case RADEON_HPD_1:
346 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
347 connected = true;
348 break;
349 case RADEON_HPD_2:
350 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
351 connected = true;
352 break;
353 default:
354 break;
355 }
356 return connected;
357 }
358
359 void r100_hpd_set_polarity(struct radeon_device *rdev,
360 enum radeon_hpd_id hpd)
361 {
362 u32 tmp;
363 bool connected = r100_hpd_sense(rdev, hpd);
364
365 switch (hpd) {
366 case RADEON_HPD_1:
367 tmp = RREG32(RADEON_FP_GEN_CNTL);
368 if (connected)
369 tmp &= ~RADEON_FP_DETECT_INT_POL;
370 else
371 tmp |= RADEON_FP_DETECT_INT_POL;
372 WREG32(RADEON_FP_GEN_CNTL, tmp);
373 break;
374 case RADEON_HPD_2:
375 tmp = RREG32(RADEON_FP2_GEN_CNTL);
376 if (connected)
377 tmp &= ~RADEON_FP2_DETECT_INT_POL;
378 else
379 tmp |= RADEON_FP2_DETECT_INT_POL;
380 WREG32(RADEON_FP2_GEN_CNTL, tmp);
381 break;
382 default:
383 break;
384 }
385 }
386
387 void r100_hpd_init(struct radeon_device *rdev)
388 {
389 struct drm_device *dev = rdev->ddev;
390 struct drm_connector *connector;
391
392 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
393 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
394 switch (radeon_connector->hpd.hpd) {
395 case RADEON_HPD_1:
396 rdev->irq.hpd[0] = true;
397 break;
398 case RADEON_HPD_2:
399 rdev->irq.hpd[1] = true;
400 break;
401 default:
402 break;
403 }
404 }
405 if (rdev->irq.installed)
406 r100_irq_set(rdev);
407 }
408
409 void r100_hpd_fini(struct radeon_device *rdev)
410 {
411 struct drm_device *dev = rdev->ddev;
412 struct drm_connector *connector;
413
414 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
415 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
416 switch (radeon_connector->hpd.hpd) {
417 case RADEON_HPD_1:
418 rdev->irq.hpd[0] = false;
419 break;
420 case RADEON_HPD_2:
421 rdev->irq.hpd[1] = false;
422 break;
423 default:
424 break;
425 }
426 }
427 }
428
429 /*
430 * PCI GART
431 */
432 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
433 {
434 /* TODO: can we do somethings here ? */
435 /* It seems hw only cache one entry so we should discard this
436 * entry otherwise if first GPU GART read hit this entry it
437 * could end up in wrong address. */
438 }
439
440 int r100_pci_gart_init(struct radeon_device *rdev)
441 {
442 int r;
443
444 if (rdev->gart.table.ram.ptr) {
445 WARN(1, "R100 PCI GART already initialized.\n");
446 return 0;
447 }
448 /* Initialize common gart structure */
449 r = radeon_gart_init(rdev);
450 if (r)
451 return r;
452 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
453 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
454 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
455 return radeon_gart_table_ram_alloc(rdev);
456 }
457
458 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
459 void r100_enable_bm(struct radeon_device *rdev)
460 {
461 uint32_t tmp;
462 /* Enable bus mastering */
463 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
464 WREG32(RADEON_BUS_CNTL, tmp);
465 }
466
467 int r100_pci_gart_enable(struct radeon_device *rdev)
468 {
469 uint32_t tmp;
470
471 radeon_gart_restore(rdev);
472 /* discard memory request outside of configured range */
473 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
474 WREG32(RADEON_AIC_CNTL, tmp);
475 /* set address range for PCI address translate */
476 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
477 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
478 /* set PCI GART page-table base address */
479 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
480 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
481 WREG32(RADEON_AIC_CNTL, tmp);
482 r100_pci_gart_tlb_flush(rdev);
483 rdev->gart.ready = true;
484 return 0;
485 }
486
487 void r100_pci_gart_disable(struct radeon_device *rdev)
488 {
489 uint32_t tmp;
490
491 /* discard memory request outside of configured range */
492 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
493 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
494 WREG32(RADEON_AIC_LO_ADDR, 0);
495 WREG32(RADEON_AIC_HI_ADDR, 0);
496 }
497
498 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
499 {
500 if (i < 0 || i > rdev->gart.num_gpu_pages) {
501 return -EINVAL;
502 }
503 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
504 return 0;
505 }
506
507 void r100_pci_gart_fini(struct radeon_device *rdev)
508 {
509 radeon_gart_fini(rdev);
510 r100_pci_gart_disable(rdev);
511 radeon_gart_table_ram_free(rdev);
512 }
513
514 int r100_irq_set(struct radeon_device *rdev)
515 {
516 uint32_t tmp = 0;
517
518 if (!rdev->irq.installed) {
519 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
520 WREG32(R_000040_GEN_INT_CNTL, 0);
521 return -EINVAL;
522 }
523 if (rdev->irq.sw_int) {
524 tmp |= RADEON_SW_INT_ENABLE;
525 }
526 if (rdev->irq.gui_idle) {
527 tmp |= RADEON_GUI_IDLE_MASK;
528 }
529 if (rdev->irq.crtc_vblank_int[0]) {
530 tmp |= RADEON_CRTC_VBLANK_MASK;
531 }
532 if (rdev->irq.crtc_vblank_int[1]) {
533 tmp |= RADEON_CRTC2_VBLANK_MASK;
534 }
535 if (rdev->irq.hpd[0]) {
536 tmp |= RADEON_FP_DETECT_MASK;
537 }
538 if (rdev->irq.hpd[1]) {
539 tmp |= RADEON_FP2_DETECT_MASK;
540 }
541 WREG32(RADEON_GEN_INT_CNTL, tmp);
542 return 0;
543 }
544
545 void r100_irq_disable(struct radeon_device *rdev)
546 {
547 u32 tmp;
548
549 WREG32(R_000040_GEN_INT_CNTL, 0);
550 /* Wait and acknowledge irq */
551 mdelay(1);
552 tmp = RREG32(R_000044_GEN_INT_STATUS);
553 WREG32(R_000044_GEN_INT_STATUS, tmp);
554 }
555
556 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
557 {
558 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
559 uint32_t irq_mask = RADEON_SW_INT_TEST |
560 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
561 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
562
563 /* the interrupt works, but the status bit is permanently asserted */
564 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
565 if (!rdev->irq.gui_idle_acked)
566 irq_mask |= RADEON_GUI_IDLE_STAT;
567 }
568
569 if (irqs) {
570 WREG32(RADEON_GEN_INT_STATUS, irqs);
571 }
572 return irqs & irq_mask;
573 }
574
575 int r100_irq_process(struct radeon_device *rdev)
576 {
577 uint32_t status, msi_rearm;
578 bool queue_hotplug = false;
579
580 /* reset gui idle ack. the status bit is broken */
581 rdev->irq.gui_idle_acked = false;
582
583 status = r100_irq_ack(rdev);
584 if (!status) {
585 return IRQ_NONE;
586 }
587 if (rdev->shutdown) {
588 return IRQ_NONE;
589 }
590 while (status) {
591 /* SW interrupt */
592 if (status & RADEON_SW_INT_TEST) {
593 radeon_fence_process(rdev);
594 }
595 /* gui idle interrupt */
596 if (status & RADEON_GUI_IDLE_STAT) {
597 rdev->irq.gui_idle_acked = true;
598 rdev->pm.gui_idle = true;
599 wake_up(&rdev->irq.idle_queue);
600 }
601 /* Vertical blank interrupts */
602 if (status & RADEON_CRTC_VBLANK_STAT) {
603 drm_handle_vblank(rdev->ddev, 0);
604 rdev->pm.vblank_sync = true;
605 wake_up(&rdev->irq.vblank_queue);
606 }
607 if (status & RADEON_CRTC2_VBLANK_STAT) {
608 drm_handle_vblank(rdev->ddev, 1);
609 rdev->pm.vblank_sync = true;
610 wake_up(&rdev->irq.vblank_queue);
611 }
612 if (status & RADEON_FP_DETECT_STAT) {
613 queue_hotplug = true;
614 DRM_DEBUG("HPD1\n");
615 }
616 if (status & RADEON_FP2_DETECT_STAT) {
617 queue_hotplug = true;
618 DRM_DEBUG("HPD2\n");
619 }
620 status = r100_irq_ack(rdev);
621 }
622 /* reset gui idle ack. the status bit is broken */
623 rdev->irq.gui_idle_acked = false;
624 if (queue_hotplug)
625 queue_work(rdev->wq, &rdev->hotplug_work);
626 if (rdev->msi_enabled) {
627 switch (rdev->family) {
628 case CHIP_RS400:
629 case CHIP_RS480:
630 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
631 WREG32(RADEON_AIC_CNTL, msi_rearm);
632 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
633 break;
634 default:
635 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
636 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
637 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
638 break;
639 }
640 }
641 return IRQ_HANDLED;
642 }
643
644 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
645 {
646 if (crtc == 0)
647 return RREG32(RADEON_CRTC_CRNT_FRAME);
648 else
649 return RREG32(RADEON_CRTC2_CRNT_FRAME);
650 }
651
652 /* Who ever call radeon_fence_emit should call ring_lock and ask
653 * for enough space (today caller are ib schedule and buffer move) */
654 void r100_fence_ring_emit(struct radeon_device *rdev,
655 struct radeon_fence *fence)
656 {
657 /* We have to make sure that caches are flushed before
658 * CPU might read something from VRAM. */
659 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
660 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
661 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
662 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
663 /* Wait until IDLE & CLEAN */
664 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
665 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
666 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
667 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
668 RADEON_HDP_READ_BUFFER_INVALIDATE);
669 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
670 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
671 /* Emit fence sequence & fire IRQ */
672 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
673 radeon_ring_write(rdev, fence->seq);
674 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
675 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
676 }
677
678 int r100_wb_init(struct radeon_device *rdev)
679 {
680 int r;
681
682 if (rdev->wb.wb_obj == NULL) {
683 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
684 RADEON_GEM_DOMAIN_GTT,
685 &rdev->wb.wb_obj);
686 if (r) {
687 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
688 return r;
689 }
690 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
691 if (unlikely(r != 0))
692 return r;
693 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
694 &rdev->wb.gpu_addr);
695 if (r) {
696 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
697 radeon_bo_unreserve(rdev->wb.wb_obj);
698 return r;
699 }
700 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
701 radeon_bo_unreserve(rdev->wb.wb_obj);
702 if (r) {
703 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
704 return r;
705 }
706 }
707 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
708 WREG32(R_00070C_CP_RB_RPTR_ADDR,
709 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
710 WREG32(R_000770_SCRATCH_UMSK, 0xff);
711 return 0;
712 }
713
714 void r100_wb_disable(struct radeon_device *rdev)
715 {
716 WREG32(R_000770_SCRATCH_UMSK, 0);
717 }
718
719 void r100_wb_fini(struct radeon_device *rdev)
720 {
721 int r;
722
723 r100_wb_disable(rdev);
724 if (rdev->wb.wb_obj) {
725 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
726 if (unlikely(r != 0)) {
727 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
728 return;
729 }
730 radeon_bo_kunmap(rdev->wb.wb_obj);
731 radeon_bo_unpin(rdev->wb.wb_obj);
732 radeon_bo_unreserve(rdev->wb.wb_obj);
733 radeon_bo_unref(&rdev->wb.wb_obj);
734 rdev->wb.wb = NULL;
735 rdev->wb.wb_obj = NULL;
736 }
737 }
738
739 int r100_copy_blit(struct radeon_device *rdev,
740 uint64_t src_offset,
741 uint64_t dst_offset,
742 unsigned num_pages,
743 struct radeon_fence *fence)
744 {
745 uint32_t cur_pages;
746 uint32_t stride_bytes = PAGE_SIZE;
747 uint32_t pitch;
748 uint32_t stride_pixels;
749 unsigned ndw;
750 int num_loops;
751 int r = 0;
752
753 /* radeon limited to 16k stride */
754 stride_bytes &= 0x3fff;
755 /* radeon pitch is /64 */
756 pitch = stride_bytes / 64;
757 stride_pixels = stride_bytes / 4;
758 num_loops = DIV_ROUND_UP(num_pages, 8191);
759
760 /* Ask for enough room for blit + flush + fence */
761 ndw = 64 + (10 * num_loops);
762 r = radeon_ring_lock(rdev, ndw);
763 if (r) {
764 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
765 return -EINVAL;
766 }
767 while (num_pages > 0) {
768 cur_pages = num_pages;
769 if (cur_pages > 8191) {
770 cur_pages = 8191;
771 }
772 num_pages -= cur_pages;
773
774 /* pages are in Y direction - height
775 page width in X direction - width */
776 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
777 radeon_ring_write(rdev,
778 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
779 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
780 RADEON_GMC_SRC_CLIPPING |
781 RADEON_GMC_DST_CLIPPING |
782 RADEON_GMC_BRUSH_NONE |
783 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
784 RADEON_GMC_SRC_DATATYPE_COLOR |
785 RADEON_ROP3_S |
786 RADEON_DP_SRC_SOURCE_MEMORY |
787 RADEON_GMC_CLR_CMP_CNTL_DIS |
788 RADEON_GMC_WR_MSK_DIS);
789 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
790 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
791 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
792 radeon_ring_write(rdev, 0);
793 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
794 radeon_ring_write(rdev, num_pages);
795 radeon_ring_write(rdev, num_pages);
796 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
797 }
798 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
799 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
800 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
801 radeon_ring_write(rdev,
802 RADEON_WAIT_2D_IDLECLEAN |
803 RADEON_WAIT_HOST_IDLECLEAN |
804 RADEON_WAIT_DMA_GUI_IDLE);
805 if (fence) {
806 r = radeon_fence_emit(rdev, fence);
807 }
808 radeon_ring_unlock_commit(rdev);
809 return r;
810 }
811
812 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
813 {
814 unsigned i;
815 u32 tmp;
816
817 for (i = 0; i < rdev->usec_timeout; i++) {
818 tmp = RREG32(R_000E40_RBBM_STATUS);
819 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
820 return 0;
821 }
822 udelay(1);
823 }
824 return -1;
825 }
826
827 void r100_ring_start(struct radeon_device *rdev)
828 {
829 int r;
830
831 r = radeon_ring_lock(rdev, 2);
832 if (r) {
833 return;
834 }
835 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
836 radeon_ring_write(rdev,
837 RADEON_ISYNC_ANY2D_IDLE3D |
838 RADEON_ISYNC_ANY3D_IDLE2D |
839 RADEON_ISYNC_WAIT_IDLEGUI |
840 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
841 radeon_ring_unlock_commit(rdev);
842 }
843
844
845 /* Load the microcode for the CP */
846 static int r100_cp_init_microcode(struct radeon_device *rdev)
847 {
848 struct platform_device *pdev;
849 const char *fw_name = NULL;
850 int err;
851
852 DRM_DEBUG_KMS("\n");
853
854 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
855 err = IS_ERR(pdev);
856 if (err) {
857 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
858 return -EINVAL;
859 }
860 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
861 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
862 (rdev->family == CHIP_RS200)) {
863 DRM_INFO("Loading R100 Microcode\n");
864 fw_name = FIRMWARE_R100;
865 } else if ((rdev->family == CHIP_R200) ||
866 (rdev->family == CHIP_RV250) ||
867 (rdev->family == CHIP_RV280) ||
868 (rdev->family == CHIP_RS300)) {
869 DRM_INFO("Loading R200 Microcode\n");
870 fw_name = FIRMWARE_R200;
871 } else if ((rdev->family == CHIP_R300) ||
872 (rdev->family == CHIP_R350) ||
873 (rdev->family == CHIP_RV350) ||
874 (rdev->family == CHIP_RV380) ||
875 (rdev->family == CHIP_RS400) ||
876 (rdev->family == CHIP_RS480)) {
877 DRM_INFO("Loading R300 Microcode\n");
878 fw_name = FIRMWARE_R300;
879 } else if ((rdev->family == CHIP_R420) ||
880 (rdev->family == CHIP_R423) ||
881 (rdev->family == CHIP_RV410)) {
882 DRM_INFO("Loading R400 Microcode\n");
883 fw_name = FIRMWARE_R420;
884 } else if ((rdev->family == CHIP_RS690) ||
885 (rdev->family == CHIP_RS740)) {
886 DRM_INFO("Loading RS690/RS740 Microcode\n");
887 fw_name = FIRMWARE_RS690;
888 } else if (rdev->family == CHIP_RS600) {
889 DRM_INFO("Loading RS600 Microcode\n");
890 fw_name = FIRMWARE_RS600;
891 } else if ((rdev->family == CHIP_RV515) ||
892 (rdev->family == CHIP_R520) ||
893 (rdev->family == CHIP_RV530) ||
894 (rdev->family == CHIP_R580) ||
895 (rdev->family == CHIP_RV560) ||
896 (rdev->family == CHIP_RV570)) {
897 DRM_INFO("Loading R500 Microcode\n");
898 fw_name = FIRMWARE_R520;
899 }
900
901 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
902 platform_device_unregister(pdev);
903 if (err) {
904 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
905 fw_name);
906 } else if (rdev->me_fw->size % 8) {
907 printk(KERN_ERR
908 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
909 rdev->me_fw->size, fw_name);
910 err = -EINVAL;
911 release_firmware(rdev->me_fw);
912 rdev->me_fw = NULL;
913 }
914 return err;
915 }
916
917 static void r100_cp_load_microcode(struct radeon_device *rdev)
918 {
919 const __be32 *fw_data;
920 int i, size;
921
922 if (r100_gui_wait_for_idle(rdev)) {
923 printk(KERN_WARNING "Failed to wait GUI idle while "
924 "programming pipes. Bad things might happen.\n");
925 }
926
927 if (rdev->me_fw) {
928 size = rdev->me_fw->size / 4;
929 fw_data = (const __be32 *)&rdev->me_fw->data[0];
930 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
931 for (i = 0; i < size; i += 2) {
932 WREG32(RADEON_CP_ME_RAM_DATAH,
933 be32_to_cpup(&fw_data[i]));
934 WREG32(RADEON_CP_ME_RAM_DATAL,
935 be32_to_cpup(&fw_data[i + 1]));
936 }
937 }
938 }
939
940 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
941 {
942 unsigned rb_bufsz;
943 unsigned rb_blksz;
944 unsigned max_fetch;
945 unsigned pre_write_timer;
946 unsigned pre_write_limit;
947 unsigned indirect2_start;
948 unsigned indirect1_start;
949 uint32_t tmp;
950 int r;
951
952 if (r100_debugfs_cp_init(rdev)) {
953 DRM_ERROR("Failed to register debugfs file for CP !\n");
954 }
955 if (!rdev->me_fw) {
956 r = r100_cp_init_microcode(rdev);
957 if (r) {
958 DRM_ERROR("Failed to load firmware!\n");
959 return r;
960 }
961 }
962
963 /* Align ring size */
964 rb_bufsz = drm_order(ring_size / 8);
965 ring_size = (1 << (rb_bufsz + 1)) * 4;
966 r100_cp_load_microcode(rdev);
967 r = radeon_ring_init(rdev, ring_size);
968 if (r) {
969 return r;
970 }
971 /* Each time the cp read 1024 bytes (16 dword/quadword) update
972 * the rptr copy in system ram */
973 rb_blksz = 9;
974 /* cp will read 128bytes at a time (4 dwords) */
975 max_fetch = 1;
976 rdev->cp.align_mask = 16 - 1;
977 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
978 pre_write_timer = 64;
979 /* Force CP_RB_WPTR write if written more than one time before the
980 * delay expire
981 */
982 pre_write_limit = 0;
983 /* Setup the cp cache like this (cache size is 96 dwords) :
984 * RING 0 to 15
985 * INDIRECT1 16 to 79
986 * INDIRECT2 80 to 95
987 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
988 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
989 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
990 * Idea being that most of the gpu cmd will be through indirect1 buffer
991 * so it gets the bigger cache.
992 */
993 indirect2_start = 80;
994 indirect1_start = 16;
995 /* cp setup */
996 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
997 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
998 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
999 REG_SET(RADEON_MAX_FETCH, max_fetch) |
1000 RADEON_RB_NO_UPDATE);
1001 #ifdef __BIG_ENDIAN
1002 tmp |= RADEON_BUF_SWAP_32BIT;
1003 #endif
1004 WREG32(RADEON_CP_RB_CNTL, tmp);
1005
1006 /* Set ring address */
1007 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
1008 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
1009 /* Force read & write ptr to 0 */
1010 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
1011 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1012 WREG32(RADEON_CP_RB_WPTR, 0);
1013 WREG32(RADEON_CP_RB_CNTL, tmp);
1014 udelay(10);
1015 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1016 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
1017 /* protect against crazy HW on resume */
1018 rdev->cp.wptr &= rdev->cp.ptr_mask;
1019 /* Set cp mode to bus mastering & enable cp*/
1020 WREG32(RADEON_CP_CSQ_MODE,
1021 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1022 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1023 WREG32(0x718, 0);
1024 WREG32(0x744, 0x00004D4D);
1025 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1026 radeon_ring_start(rdev);
1027 r = radeon_ring_test(rdev);
1028 if (r) {
1029 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1030 return r;
1031 }
1032 rdev->cp.ready = true;
1033 rdev->mc.active_vram_size = rdev->mc.real_vram_size;
1034 return 0;
1035 }
1036
1037 void r100_cp_fini(struct radeon_device *rdev)
1038 {
1039 if (r100_cp_wait_for_idle(rdev)) {
1040 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1041 }
1042 /* Disable ring */
1043 r100_cp_disable(rdev);
1044 radeon_ring_fini(rdev);
1045 DRM_INFO("radeon: cp finalized\n");
1046 }
1047
1048 void r100_cp_disable(struct radeon_device *rdev)
1049 {
1050 /* Disable ring */
1051 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1052 rdev->cp.ready = false;
1053 WREG32(RADEON_CP_CSQ_MODE, 0);
1054 WREG32(RADEON_CP_CSQ_CNTL, 0);
1055 if (r100_gui_wait_for_idle(rdev)) {
1056 printk(KERN_WARNING "Failed to wait GUI idle while "
1057 "programming pipes. Bad things might happen.\n");
1058 }
1059 }
1060
1061 void r100_cp_commit(struct radeon_device *rdev)
1062 {
1063 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1064 (void)RREG32(RADEON_CP_RB_WPTR);
1065 }
1066
1067
1068 /*
1069 * CS functions
1070 */
1071 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1072 struct radeon_cs_packet *pkt,
1073 const unsigned *auth, unsigned n,
1074 radeon_packet0_check_t check)
1075 {
1076 unsigned reg;
1077 unsigned i, j, m;
1078 unsigned idx;
1079 int r;
1080
1081 idx = pkt->idx + 1;
1082 reg = pkt->reg;
1083 /* Check that register fall into register range
1084 * determined by the number of entry (n) in the
1085 * safe register bitmap.
1086 */
1087 if (pkt->one_reg_wr) {
1088 if ((reg >> 7) > n) {
1089 return -EINVAL;
1090 }
1091 } else {
1092 if (((reg + (pkt->count << 2)) >> 7) > n) {
1093 return -EINVAL;
1094 }
1095 }
1096 for (i = 0; i <= pkt->count; i++, idx++) {
1097 j = (reg >> 7);
1098 m = 1 << ((reg >> 2) & 31);
1099 if (auth[j] & m) {
1100 r = check(p, pkt, idx, reg);
1101 if (r) {
1102 return r;
1103 }
1104 }
1105 if (pkt->one_reg_wr) {
1106 if (!(auth[j] & m)) {
1107 break;
1108 }
1109 } else {
1110 reg += 4;
1111 }
1112 }
1113 return 0;
1114 }
1115
1116 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1117 struct radeon_cs_packet *pkt)
1118 {
1119 volatile uint32_t *ib;
1120 unsigned i;
1121 unsigned idx;
1122
1123 ib = p->ib->ptr;
1124 idx = pkt->idx;
1125 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1126 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1127 }
1128 }
1129
1130 /**
1131 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1132 * @parser: parser structure holding parsing context.
1133 * @pkt: where to store packet informations
1134 *
1135 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1136 * if packet is bigger than remaining ib size. or if packets is unknown.
1137 **/
1138 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1139 struct radeon_cs_packet *pkt,
1140 unsigned idx)
1141 {
1142 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1143 uint32_t header;
1144
1145 if (idx >= ib_chunk->length_dw) {
1146 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1147 idx, ib_chunk->length_dw);
1148 return -EINVAL;
1149 }
1150 header = radeon_get_ib_value(p, idx);
1151 pkt->idx = idx;
1152 pkt->type = CP_PACKET_GET_TYPE(header);
1153 pkt->count = CP_PACKET_GET_COUNT(header);
1154 switch (pkt->type) {
1155 case PACKET_TYPE0:
1156 pkt->reg = CP_PACKET0_GET_REG(header);
1157 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1158 break;
1159 case PACKET_TYPE3:
1160 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1161 break;
1162 case PACKET_TYPE2:
1163 pkt->count = -1;
1164 break;
1165 default:
1166 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1167 return -EINVAL;
1168 }
1169 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1170 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1171 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1172 return -EINVAL;
1173 }
1174 return 0;
1175 }
1176
1177 /**
1178 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1179 * @parser: parser structure holding parsing context.
1180 *
1181 * Userspace sends a special sequence for VLINE waits.
1182 * PACKET0 - VLINE_START_END + value
1183 * PACKET0 - WAIT_UNTIL +_value
1184 * RELOC (P3) - crtc_id in reloc.
1185 *
1186 * This function parses this and relocates the VLINE START END
1187 * and WAIT UNTIL packets to the correct crtc.
1188 * It also detects a switched off crtc and nulls out the
1189 * wait in that case.
1190 */
1191 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1192 {
1193 struct drm_mode_object *obj;
1194 struct drm_crtc *crtc;
1195 struct radeon_crtc *radeon_crtc;
1196 struct radeon_cs_packet p3reloc, waitreloc;
1197 int crtc_id;
1198 int r;
1199 uint32_t header, h_idx, reg;
1200 volatile uint32_t *ib;
1201
1202 ib = p->ib->ptr;
1203
1204 /* parse the wait until */
1205 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1206 if (r)
1207 return r;
1208
1209 /* check its a wait until and only 1 count */
1210 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1211 waitreloc.count != 0) {
1212 DRM_ERROR("vline wait had illegal wait until segment\n");
1213 r = -EINVAL;
1214 return r;
1215 }
1216
1217 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1218 DRM_ERROR("vline wait had illegal wait until\n");
1219 r = -EINVAL;
1220 return r;
1221 }
1222
1223 /* jump over the NOP */
1224 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1225 if (r)
1226 return r;
1227
1228 h_idx = p->idx - 2;
1229 p->idx += waitreloc.count + 2;
1230 p->idx += p3reloc.count + 2;
1231
1232 header = radeon_get_ib_value(p, h_idx);
1233 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1234 reg = CP_PACKET0_GET_REG(header);
1235 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1236 if (!obj) {
1237 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1238 r = -EINVAL;
1239 goto out;
1240 }
1241 crtc = obj_to_crtc(obj);
1242 radeon_crtc = to_radeon_crtc(crtc);
1243 crtc_id = radeon_crtc->crtc_id;
1244
1245 if (!crtc->enabled) {
1246 /* if the CRTC isn't enabled - we need to nop out the wait until */
1247 ib[h_idx + 2] = PACKET2(0);
1248 ib[h_idx + 3] = PACKET2(0);
1249 } else if (crtc_id == 1) {
1250 switch (reg) {
1251 case AVIVO_D1MODE_VLINE_START_END:
1252 header &= ~R300_CP_PACKET0_REG_MASK;
1253 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1254 break;
1255 case RADEON_CRTC_GUI_TRIG_VLINE:
1256 header &= ~R300_CP_PACKET0_REG_MASK;
1257 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1258 break;
1259 default:
1260 DRM_ERROR("unknown crtc reloc\n");
1261 r = -EINVAL;
1262 goto out;
1263 }
1264 ib[h_idx] = header;
1265 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1266 }
1267 out:
1268 return r;
1269 }
1270
1271 /**
1272 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1273 * @parser: parser structure holding parsing context.
1274 * @data: pointer to relocation data
1275 * @offset_start: starting offset
1276 * @offset_mask: offset mask (to align start offset on)
1277 * @reloc: reloc informations
1278 *
1279 * Check next packet is relocation packet3, do bo validation and compute
1280 * GPU offset using the provided start.
1281 **/
1282 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1283 struct radeon_cs_reloc **cs_reloc)
1284 {
1285 struct radeon_cs_chunk *relocs_chunk;
1286 struct radeon_cs_packet p3reloc;
1287 unsigned idx;
1288 int r;
1289
1290 if (p->chunk_relocs_idx == -1) {
1291 DRM_ERROR("No relocation chunk !\n");
1292 return -EINVAL;
1293 }
1294 *cs_reloc = NULL;
1295 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1296 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1297 if (r) {
1298 return r;
1299 }
1300 p->idx += p3reloc.count + 2;
1301 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1302 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1303 p3reloc.idx);
1304 r100_cs_dump_packet(p, &p3reloc);
1305 return -EINVAL;
1306 }
1307 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1308 if (idx >= relocs_chunk->length_dw) {
1309 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1310 idx, relocs_chunk->length_dw);
1311 r100_cs_dump_packet(p, &p3reloc);
1312 return -EINVAL;
1313 }
1314 *cs_reloc = p->relocs_ptr[(idx / 4)];
1315 return 0;
1316 }
1317
1318 static int r100_get_vtx_size(uint32_t vtx_fmt)
1319 {
1320 int vtx_size;
1321 vtx_size = 2;
1322 /* ordered according to bits in spec */
1323 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1324 vtx_size++;
1325 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1326 vtx_size += 3;
1327 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1328 vtx_size++;
1329 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1330 vtx_size++;
1331 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1332 vtx_size += 3;
1333 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1334 vtx_size++;
1335 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1336 vtx_size++;
1337 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1338 vtx_size += 2;
1339 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1340 vtx_size += 2;
1341 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1342 vtx_size++;
1343 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1344 vtx_size += 2;
1345 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1346 vtx_size++;
1347 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1348 vtx_size += 2;
1349 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1350 vtx_size++;
1351 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1352 vtx_size++;
1353 /* blend weight */
1354 if (vtx_fmt & (0x7 << 15))
1355 vtx_size += (vtx_fmt >> 15) & 0x7;
1356 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1357 vtx_size += 3;
1358 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1359 vtx_size += 2;
1360 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1361 vtx_size++;
1362 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1363 vtx_size++;
1364 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1365 vtx_size++;
1366 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1367 vtx_size++;
1368 return vtx_size;
1369 }
1370
1371 static int r100_packet0_check(struct radeon_cs_parser *p,
1372 struct radeon_cs_packet *pkt,
1373 unsigned idx, unsigned reg)
1374 {
1375 struct radeon_cs_reloc *reloc;
1376 struct r100_cs_track *track;
1377 volatile uint32_t *ib;
1378 uint32_t tmp;
1379 int r;
1380 int i, face;
1381 u32 tile_flags = 0;
1382 u32 idx_value;
1383
1384 ib = p->ib->ptr;
1385 track = (struct r100_cs_track *)p->track;
1386
1387 idx_value = radeon_get_ib_value(p, idx);
1388
1389 switch (reg) {
1390 case RADEON_CRTC_GUI_TRIG_VLINE:
1391 r = r100_cs_packet_parse_vline(p);
1392 if (r) {
1393 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1394 idx, reg);
1395 r100_cs_dump_packet(p, pkt);
1396 return r;
1397 }
1398 break;
1399 case RADEON_DST_PITCH_OFFSET:
1400 case RADEON_SRC_PITCH_OFFSET:
1401 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1402 if (r)
1403 return r;
1404 break;
1405 case RADEON_RB3D_DEPTHOFFSET:
1406 r = r100_cs_packet_next_reloc(p, &reloc);
1407 if (r) {
1408 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1409 idx, reg);
1410 r100_cs_dump_packet(p, pkt);
1411 return r;
1412 }
1413 track->zb.robj = reloc->robj;
1414 track->zb.offset = idx_value;
1415 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1416 break;
1417 case RADEON_RB3D_COLOROFFSET:
1418 r = r100_cs_packet_next_reloc(p, &reloc);
1419 if (r) {
1420 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1421 idx, reg);
1422 r100_cs_dump_packet(p, pkt);
1423 return r;
1424 }
1425 track->cb[0].robj = reloc->robj;
1426 track->cb[0].offset = idx_value;
1427 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1428 break;
1429 case RADEON_PP_TXOFFSET_0:
1430 case RADEON_PP_TXOFFSET_1:
1431 case RADEON_PP_TXOFFSET_2:
1432 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1433 r = r100_cs_packet_next_reloc(p, &reloc);
1434 if (r) {
1435 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1436 idx, reg);
1437 r100_cs_dump_packet(p, pkt);
1438 return r;
1439 }
1440 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1441 track->textures[i].robj = reloc->robj;
1442 break;
1443 case RADEON_PP_CUBIC_OFFSET_T0_0:
1444 case RADEON_PP_CUBIC_OFFSET_T0_1:
1445 case RADEON_PP_CUBIC_OFFSET_T0_2:
1446 case RADEON_PP_CUBIC_OFFSET_T0_3:
1447 case RADEON_PP_CUBIC_OFFSET_T0_4:
1448 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1449 r = r100_cs_packet_next_reloc(p, &reloc);
1450 if (r) {
1451 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1452 idx, reg);
1453 r100_cs_dump_packet(p, pkt);
1454 return r;
1455 }
1456 track->textures[0].cube_info[i].offset = idx_value;
1457 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1458 track->textures[0].cube_info[i].robj = reloc->robj;
1459 break;
1460 case RADEON_PP_CUBIC_OFFSET_T1_0:
1461 case RADEON_PP_CUBIC_OFFSET_T1_1:
1462 case RADEON_PP_CUBIC_OFFSET_T1_2:
1463 case RADEON_PP_CUBIC_OFFSET_T1_3:
1464 case RADEON_PP_CUBIC_OFFSET_T1_4:
1465 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1466 r = r100_cs_packet_next_reloc(p, &reloc);
1467 if (r) {
1468 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1469 idx, reg);
1470 r100_cs_dump_packet(p, pkt);
1471 return r;
1472 }
1473 track->textures[1].cube_info[i].offset = idx_value;
1474 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1475 track->textures[1].cube_info[i].robj = reloc->robj;
1476 break;
1477 case RADEON_PP_CUBIC_OFFSET_T2_0:
1478 case RADEON_PP_CUBIC_OFFSET_T2_1:
1479 case RADEON_PP_CUBIC_OFFSET_T2_2:
1480 case RADEON_PP_CUBIC_OFFSET_T2_3:
1481 case RADEON_PP_CUBIC_OFFSET_T2_4:
1482 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1483 r = r100_cs_packet_next_reloc(p, &reloc);
1484 if (r) {
1485 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1486 idx, reg);
1487 r100_cs_dump_packet(p, pkt);
1488 return r;
1489 }
1490 track->textures[2].cube_info[i].offset = idx_value;
1491 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1492 track->textures[2].cube_info[i].robj = reloc->robj;
1493 break;
1494 case RADEON_RE_WIDTH_HEIGHT:
1495 track->maxy = ((idx_value >> 16) & 0x7FF);
1496 break;
1497 case RADEON_RB3D_COLORPITCH:
1498 r = r100_cs_packet_next_reloc(p, &reloc);
1499 if (r) {
1500 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1501 idx, reg);
1502 r100_cs_dump_packet(p, pkt);
1503 return r;
1504 }
1505
1506 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1507 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1508 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1509 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1510
1511 tmp = idx_value & ~(0x7 << 16);
1512 tmp |= tile_flags;
1513 ib[idx] = tmp;
1514
1515 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1516 break;
1517 case RADEON_RB3D_DEPTHPITCH:
1518 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1519 break;
1520 case RADEON_RB3D_CNTL:
1521 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1522 case 7:
1523 case 8:
1524 case 9:
1525 case 11:
1526 case 12:
1527 track->cb[0].cpp = 1;
1528 break;
1529 case 3:
1530 case 4:
1531 case 15:
1532 track->cb[0].cpp = 2;
1533 break;
1534 case 6:
1535 track->cb[0].cpp = 4;
1536 break;
1537 default:
1538 DRM_ERROR("Invalid color buffer format (%d) !\n",
1539 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1540 return -EINVAL;
1541 }
1542 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1543 break;
1544 case RADEON_RB3D_ZSTENCILCNTL:
1545 switch (idx_value & 0xf) {
1546 case 0:
1547 track->zb.cpp = 2;
1548 break;
1549 case 2:
1550 case 3:
1551 case 4:
1552 case 5:
1553 case 9:
1554 case 11:
1555 track->zb.cpp = 4;
1556 break;
1557 default:
1558 break;
1559 }
1560 break;
1561 case RADEON_RB3D_ZPASS_ADDR:
1562 r = r100_cs_packet_next_reloc(p, &reloc);
1563 if (r) {
1564 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1565 idx, reg);
1566 r100_cs_dump_packet(p, pkt);
1567 return r;
1568 }
1569 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1570 break;
1571 case RADEON_PP_CNTL:
1572 {
1573 uint32_t temp = idx_value >> 4;
1574 for (i = 0; i < track->num_texture; i++)
1575 track->textures[i].enabled = !!(temp & (1 << i));
1576 }
1577 break;
1578 case RADEON_SE_VF_CNTL:
1579 track->vap_vf_cntl = idx_value;
1580 break;
1581 case RADEON_SE_VTX_FMT:
1582 track->vtx_size = r100_get_vtx_size(idx_value);
1583 break;
1584 case RADEON_PP_TEX_SIZE_0:
1585 case RADEON_PP_TEX_SIZE_1:
1586 case RADEON_PP_TEX_SIZE_2:
1587 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1588 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1589 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1590 break;
1591 case RADEON_PP_TEX_PITCH_0:
1592 case RADEON_PP_TEX_PITCH_1:
1593 case RADEON_PP_TEX_PITCH_2:
1594 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1595 track->textures[i].pitch = idx_value + 32;
1596 break;
1597 case RADEON_PP_TXFILTER_0:
1598 case RADEON_PP_TXFILTER_1:
1599 case RADEON_PP_TXFILTER_2:
1600 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1601 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1602 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1603 tmp = (idx_value >> 23) & 0x7;
1604 if (tmp == 2 || tmp == 6)
1605 track->textures[i].roundup_w = false;
1606 tmp = (idx_value >> 27) & 0x7;
1607 if (tmp == 2 || tmp == 6)
1608 track->textures[i].roundup_h = false;
1609 break;
1610 case RADEON_PP_TXFORMAT_0:
1611 case RADEON_PP_TXFORMAT_1:
1612 case RADEON_PP_TXFORMAT_2:
1613 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1614 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1615 track->textures[i].use_pitch = 1;
1616 } else {
1617 track->textures[i].use_pitch = 0;
1618 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1619 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1620 }
1621 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1622 track->textures[i].tex_coord_type = 2;
1623 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1624 case RADEON_TXFORMAT_I8:
1625 case RADEON_TXFORMAT_RGB332:
1626 case RADEON_TXFORMAT_Y8:
1627 track->textures[i].cpp = 1;
1628 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1629 break;
1630 case RADEON_TXFORMAT_AI88:
1631 case RADEON_TXFORMAT_ARGB1555:
1632 case RADEON_TXFORMAT_RGB565:
1633 case RADEON_TXFORMAT_ARGB4444:
1634 case RADEON_TXFORMAT_VYUY422:
1635 case RADEON_TXFORMAT_YVYU422:
1636 case RADEON_TXFORMAT_SHADOW16:
1637 case RADEON_TXFORMAT_LDUDV655:
1638 case RADEON_TXFORMAT_DUDV88:
1639 track->textures[i].cpp = 2;
1640 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1641 break;
1642 case RADEON_TXFORMAT_ARGB8888:
1643 case RADEON_TXFORMAT_RGBA8888:
1644 case RADEON_TXFORMAT_SHADOW32:
1645 case RADEON_TXFORMAT_LDUDUV8888:
1646 track->textures[i].cpp = 4;
1647 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1648 break;
1649 case RADEON_TXFORMAT_DXT1:
1650 track->textures[i].cpp = 1;
1651 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1652 break;
1653 case RADEON_TXFORMAT_DXT23:
1654 case RADEON_TXFORMAT_DXT45:
1655 track->textures[i].cpp = 1;
1656 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1657 break;
1658 }
1659 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1660 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1661 break;
1662 case RADEON_PP_CUBIC_FACES_0:
1663 case RADEON_PP_CUBIC_FACES_1:
1664 case RADEON_PP_CUBIC_FACES_2:
1665 tmp = idx_value;
1666 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1667 for (face = 0; face < 4; face++) {
1668 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1669 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1670 }
1671 break;
1672 default:
1673 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1674 reg, idx);
1675 return -EINVAL;
1676 }
1677 return 0;
1678 }
1679
1680 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1681 struct radeon_cs_packet *pkt,
1682 struct radeon_bo *robj)
1683 {
1684 unsigned idx;
1685 u32 value;
1686 idx = pkt->idx + 1;
1687 value = radeon_get_ib_value(p, idx + 2);
1688 if ((value + 1) > radeon_bo_size(robj)) {
1689 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1690 "(need %u have %lu) !\n",
1691 value + 1,
1692 radeon_bo_size(robj));
1693 return -EINVAL;
1694 }
1695 return 0;
1696 }
1697
1698 static int r100_packet3_check(struct radeon_cs_parser *p,
1699 struct radeon_cs_packet *pkt)
1700 {
1701 struct radeon_cs_reloc *reloc;
1702 struct r100_cs_track *track;
1703 unsigned idx;
1704 volatile uint32_t *ib;
1705 int r;
1706
1707 ib = p->ib->ptr;
1708 idx = pkt->idx + 1;
1709 track = (struct r100_cs_track *)p->track;
1710 switch (pkt->opcode) {
1711 case PACKET3_3D_LOAD_VBPNTR:
1712 r = r100_packet3_load_vbpntr(p, pkt, idx);
1713 if (r)
1714 return r;
1715 break;
1716 case PACKET3_INDX_BUFFER:
1717 r = r100_cs_packet_next_reloc(p, &reloc);
1718 if (r) {
1719 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1720 r100_cs_dump_packet(p, pkt);
1721 return r;
1722 }
1723 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1724 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1725 if (r) {
1726 return r;
1727 }
1728 break;
1729 case 0x23:
1730 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1731 r = r100_cs_packet_next_reloc(p, &reloc);
1732 if (r) {
1733 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1734 r100_cs_dump_packet(p, pkt);
1735 return r;
1736 }
1737 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1738 track->num_arrays = 1;
1739 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1740
1741 track->arrays[0].robj = reloc->robj;
1742 track->arrays[0].esize = track->vtx_size;
1743
1744 track->max_indx = radeon_get_ib_value(p, idx+1);
1745
1746 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1747 track->immd_dwords = pkt->count - 1;
1748 r = r100_cs_track_check(p->rdev, track);
1749 if (r)
1750 return r;
1751 break;
1752 case PACKET3_3D_DRAW_IMMD:
1753 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1754 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1755 return -EINVAL;
1756 }
1757 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1758 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1759 track->immd_dwords = pkt->count - 1;
1760 r = r100_cs_track_check(p->rdev, track);
1761 if (r)
1762 return r;
1763 break;
1764 /* triggers drawing using in-packet vertex data */
1765 case PACKET3_3D_DRAW_IMMD_2:
1766 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1767 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1768 return -EINVAL;
1769 }
1770 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1771 track->immd_dwords = pkt->count;
1772 r = r100_cs_track_check(p->rdev, track);
1773 if (r)
1774 return r;
1775 break;
1776 /* triggers drawing using in-packet vertex data */
1777 case PACKET3_3D_DRAW_VBUF_2:
1778 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1779 r = r100_cs_track_check(p->rdev, track);
1780 if (r)
1781 return r;
1782 break;
1783 /* triggers drawing of vertex buffers setup elsewhere */
1784 case PACKET3_3D_DRAW_INDX_2:
1785 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1786 r = r100_cs_track_check(p->rdev, track);
1787 if (r)
1788 return r;
1789 break;
1790 /* triggers drawing using indices to vertex buffer */
1791 case PACKET3_3D_DRAW_VBUF:
1792 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1793 r = r100_cs_track_check(p->rdev, track);
1794 if (r)
1795 return r;
1796 break;
1797 /* triggers drawing of vertex buffers setup elsewhere */
1798 case PACKET3_3D_DRAW_INDX:
1799 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1800 r = r100_cs_track_check(p->rdev, track);
1801 if (r)
1802 return r;
1803 break;
1804 /* triggers drawing using indices to vertex buffer */
1805 case PACKET3_3D_CLEAR_HIZ:
1806 case PACKET3_3D_CLEAR_ZMASK:
1807 if (p->rdev->hyperz_filp != p->filp)
1808 return -EINVAL;
1809 break;
1810 case PACKET3_NOP:
1811 break;
1812 default:
1813 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1814 return -EINVAL;
1815 }
1816 return 0;
1817 }
1818
1819 int r100_cs_parse(struct radeon_cs_parser *p)
1820 {
1821 struct radeon_cs_packet pkt;
1822 struct r100_cs_track *track;
1823 int r;
1824
1825 track = kzalloc(sizeof(*track), GFP_KERNEL);
1826 r100_cs_track_clear(p->rdev, track);
1827 p->track = track;
1828 do {
1829 r = r100_cs_packet_parse(p, &pkt, p->idx);
1830 if (r) {
1831 return r;
1832 }
1833 p->idx += pkt.count + 2;
1834 switch (pkt.type) {
1835 case PACKET_TYPE0:
1836 if (p->rdev->family >= CHIP_R200)
1837 r = r100_cs_parse_packet0(p, &pkt,
1838 p->rdev->config.r100.reg_safe_bm,
1839 p->rdev->config.r100.reg_safe_bm_size,
1840 &r200_packet0_check);
1841 else
1842 r = r100_cs_parse_packet0(p, &pkt,
1843 p->rdev->config.r100.reg_safe_bm,
1844 p->rdev->config.r100.reg_safe_bm_size,
1845 &r100_packet0_check);
1846 break;
1847 case PACKET_TYPE2:
1848 break;
1849 case PACKET_TYPE3:
1850 r = r100_packet3_check(p, &pkt);
1851 break;
1852 default:
1853 DRM_ERROR("Unknown packet type %d !\n",
1854 pkt.type);
1855 return -EINVAL;
1856 }
1857 if (r) {
1858 return r;
1859 }
1860 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1861 return 0;
1862 }
1863
1864
1865 /*
1866 * Global GPU functions
1867 */
1868 void r100_errata(struct radeon_device *rdev)
1869 {
1870 rdev->pll_errata = 0;
1871
1872 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1873 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1874 }
1875
1876 if (rdev->family == CHIP_RV100 ||
1877 rdev->family == CHIP_RS100 ||
1878 rdev->family == CHIP_RS200) {
1879 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1880 }
1881 }
1882
1883 /* Wait for vertical sync on primary CRTC */
1884 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1885 {
1886 uint32_t crtc_gen_cntl, tmp;
1887 int i;
1888
1889 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1890 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1891 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1892 return;
1893 }
1894 /* Clear the CRTC_VBLANK_SAVE bit */
1895 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1896 for (i = 0; i < rdev->usec_timeout; i++) {
1897 tmp = RREG32(RADEON_CRTC_STATUS);
1898 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1899 return;
1900 }
1901 DRM_UDELAY(1);
1902 }
1903 }
1904
1905 /* Wait for vertical sync on secondary CRTC */
1906 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1907 {
1908 uint32_t crtc2_gen_cntl, tmp;
1909 int i;
1910
1911 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1912 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1913 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1914 return;
1915
1916 /* Clear the CRTC_VBLANK_SAVE bit */
1917 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1918 for (i = 0; i < rdev->usec_timeout; i++) {
1919 tmp = RREG32(RADEON_CRTC2_STATUS);
1920 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1921 return;
1922 }
1923 DRM_UDELAY(1);
1924 }
1925 }
1926
1927 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1928 {
1929 unsigned i;
1930 uint32_t tmp;
1931
1932 for (i = 0; i < rdev->usec_timeout; i++) {
1933 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1934 if (tmp >= n) {
1935 return 0;
1936 }
1937 DRM_UDELAY(1);
1938 }
1939 return -1;
1940 }
1941
1942 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1943 {
1944 unsigned i;
1945 uint32_t tmp;
1946
1947 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1948 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1949 " Bad things might happen.\n");
1950 }
1951 for (i = 0; i < rdev->usec_timeout; i++) {
1952 tmp = RREG32(RADEON_RBBM_STATUS);
1953 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1954 return 0;
1955 }
1956 DRM_UDELAY(1);
1957 }
1958 return -1;
1959 }
1960
1961 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1962 {
1963 unsigned i;
1964 uint32_t tmp;
1965
1966 for (i = 0; i < rdev->usec_timeout; i++) {
1967 /* read MC_STATUS */
1968 tmp = RREG32(RADEON_MC_STATUS);
1969 if (tmp & RADEON_MC_IDLE) {
1970 return 0;
1971 }
1972 DRM_UDELAY(1);
1973 }
1974 return -1;
1975 }
1976
1977 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
1978 {
1979 lockup->last_cp_rptr = cp->rptr;
1980 lockup->last_jiffies = jiffies;
1981 }
1982
1983 /**
1984 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
1985 * @rdev: radeon device structure
1986 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
1987 * @cp: radeon_cp structure holding CP information
1988 *
1989 * We don't need to initialize the lockup tracking information as we will either
1990 * have CP rptr to a different value of jiffies wrap around which will force
1991 * initialization of the lockup tracking informations.
1992 *
1993 * A possible false positivie is if we get call after while and last_cp_rptr ==
1994 * the current CP rptr, even if it's unlikely it might happen. To avoid this
1995 * if the elapsed time since last call is bigger than 2 second than we return
1996 * false and update the tracking information. Due to this the caller must call
1997 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
1998 * the fencing code should be cautious about that.
1999 *
2000 * Caller should write to the ring to force CP to do something so we don't get
2001 * false positive when CP is just gived nothing to do.
2002 *
2003 **/
2004 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2005 {
2006 unsigned long cjiffies, elapsed;
2007
2008 cjiffies = jiffies;
2009 if (!time_after(cjiffies, lockup->last_jiffies)) {
2010 /* likely a wrap around */
2011 lockup->last_cp_rptr = cp->rptr;
2012 lockup->last_jiffies = jiffies;
2013 return false;
2014 }
2015 if (cp->rptr != lockup->last_cp_rptr) {
2016 /* CP is still working no lockup */
2017 lockup->last_cp_rptr = cp->rptr;
2018 lockup->last_jiffies = jiffies;
2019 return false;
2020 }
2021 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2022 if (elapsed >= 10000) {
2023 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2024 return true;
2025 }
2026 /* give a chance to the GPU ... */
2027 return false;
2028 }
2029
2030 bool r100_gpu_is_lockup(struct radeon_device *rdev)
2031 {
2032 u32 rbbm_status;
2033 int r;
2034
2035 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2036 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2037 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2038 return false;
2039 }
2040 /* force CP activities */
2041 r = radeon_ring_lock(rdev, 2);
2042 if (!r) {
2043 /* PACKET2 NOP */
2044 radeon_ring_write(rdev, 0x80000000);
2045 radeon_ring_write(rdev, 0x80000000);
2046 radeon_ring_unlock_commit(rdev);
2047 }
2048 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2049 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2050 }
2051
2052 void r100_bm_disable(struct radeon_device *rdev)
2053 {
2054 u32 tmp;
2055
2056 /* disable bus mastering */
2057 tmp = RREG32(R_000030_BUS_CNTL);
2058 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2059 mdelay(1);
2060 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2061 mdelay(1);
2062 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2063 tmp = RREG32(RADEON_BUS_CNTL);
2064 mdelay(1);
2065 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2066 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
2067 mdelay(1);
2068 }
2069
2070 int r100_asic_reset(struct radeon_device *rdev)
2071 {
2072 struct r100_mc_save save;
2073 u32 status, tmp;
2074
2075 r100_mc_stop(rdev, &save);
2076 status = RREG32(R_000E40_RBBM_STATUS);
2077 if (!G_000E40_GUI_ACTIVE(status)) {
2078 return 0;
2079 }
2080 status = RREG32(R_000E40_RBBM_STATUS);
2081 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2082 /* stop CP */
2083 WREG32(RADEON_CP_CSQ_CNTL, 0);
2084 tmp = RREG32(RADEON_CP_RB_CNTL);
2085 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2086 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2087 WREG32(RADEON_CP_RB_WPTR, 0);
2088 WREG32(RADEON_CP_RB_CNTL, tmp);
2089 /* save PCI state */
2090 pci_save_state(rdev->pdev);
2091 /* disable bus mastering */
2092 r100_bm_disable(rdev);
2093 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2094 S_0000F0_SOFT_RESET_RE(1) |
2095 S_0000F0_SOFT_RESET_PP(1) |
2096 S_0000F0_SOFT_RESET_RB(1));
2097 RREG32(R_0000F0_RBBM_SOFT_RESET);
2098 mdelay(500);
2099 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2100 mdelay(1);
2101 status = RREG32(R_000E40_RBBM_STATUS);
2102 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2103 /* reset CP */
2104 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2105 RREG32(R_0000F0_RBBM_SOFT_RESET);
2106 mdelay(500);
2107 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2108 mdelay(1);
2109 status = RREG32(R_000E40_RBBM_STATUS);
2110 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2111 /* restore PCI & busmastering */
2112 pci_restore_state(rdev->pdev);
2113 r100_enable_bm(rdev);
2114 /* Check if GPU is idle */
2115 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2116 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2117 dev_err(rdev->dev, "failed to reset GPU\n");
2118 rdev->gpu_lockup = true;
2119 return -1;
2120 }
2121 r100_mc_resume(rdev, &save);
2122 dev_info(rdev->dev, "GPU reset succeed\n");
2123 return 0;
2124 }
2125
2126 void r100_set_common_regs(struct radeon_device *rdev)
2127 {
2128 struct drm_device *dev = rdev->ddev;
2129 bool force_dac2 = false;
2130 u32 tmp;
2131
2132 /* set these so they don't interfere with anything */
2133 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2134 WREG32(RADEON_SUBPIC_CNTL, 0);
2135 WREG32(RADEON_VIPH_CONTROL, 0);
2136 WREG32(RADEON_I2C_CNTL_1, 0);
2137 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2138 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2139 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2140
2141 /* always set up dac2 on rn50 and some rv100 as lots
2142 * of servers seem to wire it up to a VGA port but
2143 * don't report it in the bios connector
2144 * table.
2145 */
2146 switch (dev->pdev->device) {
2147 /* RN50 */
2148 case 0x515e:
2149 case 0x5969:
2150 force_dac2 = true;
2151 break;
2152 /* RV100*/
2153 case 0x5159:
2154 case 0x515a:
2155 /* DELL triple head servers */
2156 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2157 ((dev->pdev->subsystem_device == 0x016c) ||
2158 (dev->pdev->subsystem_device == 0x016d) ||
2159 (dev->pdev->subsystem_device == 0x016e) ||
2160 (dev->pdev->subsystem_device == 0x016f) ||
2161 (dev->pdev->subsystem_device == 0x0170) ||
2162 (dev->pdev->subsystem_device == 0x017d) ||
2163 (dev->pdev->subsystem_device == 0x017e) ||
2164 (dev->pdev->subsystem_device == 0x0183) ||
2165 (dev->pdev->subsystem_device == 0x018a) ||
2166 (dev->pdev->subsystem_device == 0x019a)))
2167 force_dac2 = true;
2168 break;
2169 }
2170
2171 if (force_dac2) {
2172 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2173 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2174 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2175
2176 /* For CRT on DAC2, don't turn it on if BIOS didn't
2177 enable it, even it's detected.
2178 */
2179
2180 /* force it to crtc0 */
2181 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2182 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2183 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2184
2185 /* set up the TV DAC */
2186 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2187 RADEON_TV_DAC_STD_MASK |
2188 RADEON_TV_DAC_RDACPD |
2189 RADEON_TV_DAC_GDACPD |
2190 RADEON_TV_DAC_BDACPD |
2191 RADEON_TV_DAC_BGADJ_MASK |
2192 RADEON_TV_DAC_DACADJ_MASK);
2193 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2194 RADEON_TV_DAC_NHOLD |
2195 RADEON_TV_DAC_STD_PS2 |
2196 (0x58 << 16));
2197
2198 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2199 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2200 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2201 }
2202
2203 /* switch PM block to ACPI mode */
2204 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2205 tmp &= ~RADEON_PM_MODE_SEL;
2206 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2207
2208 }
2209
2210 /*
2211 * VRAM info
2212 */
2213 static void r100_vram_get_type(struct radeon_device *rdev)
2214 {
2215 uint32_t tmp;
2216
2217 rdev->mc.vram_is_ddr = false;
2218 if (rdev->flags & RADEON_IS_IGP)
2219 rdev->mc.vram_is_ddr = true;
2220 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2221 rdev->mc.vram_is_ddr = true;
2222 if ((rdev->family == CHIP_RV100) ||
2223 (rdev->family == CHIP_RS100) ||
2224 (rdev->family == CHIP_RS200)) {
2225 tmp = RREG32(RADEON_MEM_CNTL);
2226 if (tmp & RV100_HALF_MODE) {
2227 rdev->mc.vram_width = 32;
2228 } else {
2229 rdev->mc.vram_width = 64;
2230 }
2231 if (rdev->flags & RADEON_SINGLE_CRTC) {
2232 rdev->mc.vram_width /= 4;
2233 rdev->mc.vram_is_ddr = true;
2234 }
2235 } else if (rdev->family <= CHIP_RV280) {
2236 tmp = RREG32(RADEON_MEM_CNTL);
2237 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2238 rdev->mc.vram_width = 128;
2239 } else {
2240 rdev->mc.vram_width = 64;
2241 }
2242 } else {
2243 /* newer IGPs */
2244 rdev->mc.vram_width = 128;
2245 }
2246 }
2247
2248 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2249 {
2250 u32 aper_size;
2251 u8 byte;
2252
2253 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2254
2255 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2256 * that is has the 2nd generation multifunction PCI interface
2257 */
2258 if (rdev->family == CHIP_RV280 ||
2259 rdev->family >= CHIP_RV350) {
2260 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2261 ~RADEON_HDP_APER_CNTL);
2262 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2263 return aper_size * 2;
2264 }
2265
2266 /* Older cards have all sorts of funny issues to deal with. First
2267 * check if it's a multifunction card by reading the PCI config
2268 * header type... Limit those to one aperture size
2269 */
2270 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2271 if (byte & 0x80) {
2272 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2273 DRM_INFO("Limiting VRAM to one aperture\n");
2274 return aper_size;
2275 }
2276
2277 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2278 * have set it up. We don't write this as it's broken on some ASICs but
2279 * we expect the BIOS to have done the right thing (might be too optimistic...)
2280 */
2281 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2282 return aper_size * 2;
2283 return aper_size;
2284 }
2285
2286 void r100_vram_init_sizes(struct radeon_device *rdev)
2287 {
2288 u64 config_aper_size;
2289
2290 /* work out accessible VRAM */
2291 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2292 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2293 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2294 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2295 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2296 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
2297 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2298 if (rdev->flags & RADEON_IS_IGP) {
2299 uint32_t tom;
2300 /* read NB_TOM to get the amount of ram stolen for the GPU */
2301 tom = RREG32(RADEON_NB_TOM);
2302 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2303 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2304 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2305 } else {
2306 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2307 /* Some production boards of m6 will report 0
2308 * if it's 8 MB
2309 */
2310 if (rdev->mc.real_vram_size == 0) {
2311 rdev->mc.real_vram_size = 8192 * 1024;
2312 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2313 }
2314 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2315 * Novell bug 204882 + along with lots of ubuntu ones
2316 */
2317 if (rdev->mc.aper_size > config_aper_size)
2318 config_aper_size = rdev->mc.aper_size;
2319
2320 if (config_aper_size > rdev->mc.real_vram_size)
2321 rdev->mc.mc_vram_size = config_aper_size;
2322 else
2323 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2324 }
2325 }
2326
2327 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2328 {
2329 uint32_t temp;
2330
2331 temp = RREG32(RADEON_CONFIG_CNTL);
2332 if (state == false) {
2333 temp &= ~(1<<8);
2334 temp |= (1<<9);
2335 } else {
2336 temp &= ~(1<<9);
2337 }
2338 WREG32(RADEON_CONFIG_CNTL, temp);
2339 }
2340
2341 void r100_mc_init(struct radeon_device *rdev)
2342 {
2343 u64 base;
2344
2345 r100_vram_get_type(rdev);
2346 r100_vram_init_sizes(rdev);
2347 base = rdev->mc.aper_base;
2348 if (rdev->flags & RADEON_IS_IGP)
2349 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2350 radeon_vram_location(rdev, &rdev->mc, base);
2351 rdev->mc.gtt_base_align = 0;
2352 if (!(rdev->flags & RADEON_IS_AGP))
2353 radeon_gtt_location(rdev, &rdev->mc);
2354 radeon_update_bandwidth_info(rdev);
2355 }
2356
2357
2358 /*
2359 * Indirect registers accessor
2360 */
2361 void r100_pll_errata_after_index(struct radeon_device *rdev)
2362 {
2363 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2364 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2365 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2366 }
2367 }
2368
2369 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2370 {
2371 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2372 * or the chip could hang on a subsequent access
2373 */
2374 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2375 udelay(5000);
2376 }
2377
2378 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2379 uint32_t save, tmp;
2380
2381 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2382 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2383 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2384 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2385 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2386 }
2387 }
2388
2389 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2390 {
2391 uint32_t data;
2392
2393 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2394 r100_pll_errata_after_index(rdev);
2395 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2396 r100_pll_errata_after_data(rdev);
2397 return data;
2398 }
2399
2400 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2401 {
2402 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2403 r100_pll_errata_after_index(rdev);
2404 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2405 r100_pll_errata_after_data(rdev);
2406 }
2407
2408 void r100_set_safe_registers(struct radeon_device *rdev)
2409 {
2410 if (ASIC_IS_RN50(rdev)) {
2411 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2412 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2413 } else if (rdev->family < CHIP_R200) {
2414 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2415 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2416 } else {
2417 r200_set_safe_registers(rdev);
2418 }
2419 }
2420
2421 /*
2422 * Debugfs info
2423 */
2424 #if defined(CONFIG_DEBUG_FS)
2425 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2426 {
2427 struct drm_info_node *node = (struct drm_info_node *) m->private;
2428 struct drm_device *dev = node->minor->dev;
2429 struct radeon_device *rdev = dev->dev_private;
2430 uint32_t reg, value;
2431 unsigned i;
2432
2433 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2434 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2435 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2436 for (i = 0; i < 64; i++) {
2437 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2438 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2439 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2440 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2441 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2442 }
2443 return 0;
2444 }
2445
2446 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2447 {
2448 struct drm_info_node *node = (struct drm_info_node *) m->private;
2449 struct drm_device *dev = node->minor->dev;
2450 struct radeon_device *rdev = dev->dev_private;
2451 uint32_t rdp, wdp;
2452 unsigned count, i, j;
2453
2454 radeon_ring_free_size(rdev);
2455 rdp = RREG32(RADEON_CP_RB_RPTR);
2456 wdp = RREG32(RADEON_CP_RB_WPTR);
2457 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2458 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2459 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2460 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2461 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2462 seq_printf(m, "%u dwords in ring\n", count);
2463 for (j = 0; j <= count; j++) {
2464 i = (rdp + j) & rdev->cp.ptr_mask;
2465 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2466 }
2467 return 0;
2468 }
2469
2470
2471 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2472 {
2473 struct drm_info_node *node = (struct drm_info_node *) m->private;
2474 struct drm_device *dev = node->minor->dev;
2475 struct radeon_device *rdev = dev->dev_private;
2476 uint32_t csq_stat, csq2_stat, tmp;
2477 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2478 unsigned i;
2479
2480 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2481 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2482 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2483 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2484 r_rptr = (csq_stat >> 0) & 0x3ff;
2485 r_wptr = (csq_stat >> 10) & 0x3ff;
2486 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2487 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2488 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2489 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2490 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2491 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2492 seq_printf(m, "Ring rptr %u\n", r_rptr);
2493 seq_printf(m, "Ring wptr %u\n", r_wptr);
2494 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2495 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2496 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2497 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2498 seq_printf(m, "Ring fifo:\n");
2499 for (i = 0; i < 256; i++) {
2500 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2501 tmp = RREG32(RADEON_CP_CSQ_DATA);
2502 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2503 }
2504 seq_printf(m, "Indirect1 fifo:\n");
2505 for (i = 256; i <= 512; i++) {
2506 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2507 tmp = RREG32(RADEON_CP_CSQ_DATA);
2508 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2509 }
2510 seq_printf(m, "Indirect2 fifo:\n");
2511 for (i = 640; i < ib1_wptr; i++) {
2512 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2513 tmp = RREG32(RADEON_CP_CSQ_DATA);
2514 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2515 }
2516 return 0;
2517 }
2518
2519 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2520 {
2521 struct drm_info_node *node = (struct drm_info_node *) m->private;
2522 struct drm_device *dev = node->minor->dev;
2523 struct radeon_device *rdev = dev->dev_private;
2524 uint32_t tmp;
2525
2526 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2527 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2528 tmp = RREG32(RADEON_MC_FB_LOCATION);
2529 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2530 tmp = RREG32(RADEON_BUS_CNTL);
2531 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2532 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2533 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2534 tmp = RREG32(RADEON_AGP_BASE);
2535 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2536 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2537 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2538 tmp = RREG32(0x01D0);
2539 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2540 tmp = RREG32(RADEON_AIC_LO_ADDR);
2541 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2542 tmp = RREG32(RADEON_AIC_HI_ADDR);
2543 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2544 tmp = RREG32(0x01E4);
2545 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2546 return 0;
2547 }
2548
2549 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2550 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2551 };
2552
2553 static struct drm_info_list r100_debugfs_cp_list[] = {
2554 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2555 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2556 };
2557
2558 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2559 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2560 };
2561 #endif
2562
2563 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2564 {
2565 #if defined(CONFIG_DEBUG_FS)
2566 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2567 #else
2568 return 0;
2569 #endif
2570 }
2571
2572 int r100_debugfs_cp_init(struct radeon_device *rdev)
2573 {
2574 #if defined(CONFIG_DEBUG_FS)
2575 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2576 #else
2577 return 0;
2578 #endif
2579 }
2580
2581 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2582 {
2583 #if defined(CONFIG_DEBUG_FS)
2584 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2585 #else
2586 return 0;
2587 #endif
2588 }
2589
2590 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2591 uint32_t tiling_flags, uint32_t pitch,
2592 uint32_t offset, uint32_t obj_size)
2593 {
2594 int surf_index = reg * 16;
2595 int flags = 0;
2596
2597 if (rdev->family <= CHIP_RS200) {
2598 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2599 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2600 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2601 if (tiling_flags & RADEON_TILING_MACRO)
2602 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2603 } else if (rdev->family <= CHIP_RV280) {
2604 if (tiling_flags & (RADEON_TILING_MACRO))
2605 flags |= R200_SURF_TILE_COLOR_MACRO;
2606 if (tiling_flags & RADEON_TILING_MICRO)
2607 flags |= R200_SURF_TILE_COLOR_MICRO;
2608 } else {
2609 if (tiling_flags & RADEON_TILING_MACRO)
2610 flags |= R300_SURF_TILE_MACRO;
2611 if (tiling_flags & RADEON_TILING_MICRO)
2612 flags |= R300_SURF_TILE_MICRO;
2613 }
2614
2615 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2616 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2617 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2618 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2619
2620 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2621 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2622 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2623 if (ASIC_IS_RN50(rdev))
2624 pitch /= 16;
2625 }
2626
2627 /* r100/r200 divide by 16 */
2628 if (rdev->family < CHIP_R300)
2629 flags |= pitch / 16;
2630 else
2631 flags |= pitch / 8;
2632
2633
2634 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2635 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2636 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2637 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2638 return 0;
2639 }
2640
2641 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2642 {
2643 int surf_index = reg * 16;
2644 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2645 }
2646
2647 void r100_bandwidth_update(struct radeon_device *rdev)
2648 {
2649 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2650 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2651 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2652 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2653 fixed20_12 memtcas_ff[8] = {
2654 dfixed_init(1),
2655 dfixed_init(2),
2656 dfixed_init(3),
2657 dfixed_init(0),
2658 dfixed_init_half(1),
2659 dfixed_init_half(2),
2660 dfixed_init(0),
2661 };
2662 fixed20_12 memtcas_rs480_ff[8] = {
2663 dfixed_init(0),
2664 dfixed_init(1),
2665 dfixed_init(2),
2666 dfixed_init(3),
2667 dfixed_init(0),
2668 dfixed_init_half(1),
2669 dfixed_init_half(2),
2670 dfixed_init_half(3),
2671 };
2672 fixed20_12 memtcas2_ff[8] = {
2673 dfixed_init(0),
2674 dfixed_init(1),
2675 dfixed_init(2),
2676 dfixed_init(3),
2677 dfixed_init(4),
2678 dfixed_init(5),
2679 dfixed_init(6),
2680 dfixed_init(7),
2681 };
2682 fixed20_12 memtrbs[8] = {
2683 dfixed_init(1),
2684 dfixed_init_half(1),
2685 dfixed_init(2),
2686 dfixed_init_half(2),
2687 dfixed_init(3),
2688 dfixed_init_half(3),
2689 dfixed_init(4),
2690 dfixed_init_half(4)
2691 };
2692 fixed20_12 memtrbs_r4xx[8] = {
2693 dfixed_init(4),
2694 dfixed_init(5),
2695 dfixed_init(6),
2696 dfixed_init(7),
2697 dfixed_init(8),
2698 dfixed_init(9),
2699 dfixed_init(10),
2700 dfixed_init(11)
2701 };
2702 fixed20_12 min_mem_eff;
2703 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2704 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2705 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2706 disp_drain_rate2, read_return_rate;
2707 fixed20_12 time_disp1_drop_priority;
2708 int c;
2709 int cur_size = 16; /* in octawords */
2710 int critical_point = 0, critical_point2;
2711 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2712 int stop_req, max_stop_req;
2713 struct drm_display_mode *mode1 = NULL;
2714 struct drm_display_mode *mode2 = NULL;
2715 uint32_t pixel_bytes1 = 0;
2716 uint32_t pixel_bytes2 = 0;
2717
2718 radeon_update_display_priority(rdev);
2719
2720 if (rdev->mode_info.crtcs[0]->base.enabled) {
2721 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2722 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2723 }
2724 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2725 if (rdev->mode_info.crtcs[1]->base.enabled) {
2726 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2727 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2728 }
2729 }
2730
2731 min_mem_eff.full = dfixed_const_8(0);
2732 /* get modes */
2733 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2734 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2735 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2736 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2737 /* check crtc enables */
2738 if (mode2)
2739 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2740 if (mode1)
2741 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2742 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2743 }
2744
2745 /*
2746 * determine is there is enough bw for current mode
2747 */
2748 sclk_ff = rdev->pm.sclk;
2749 mclk_ff = rdev->pm.mclk;
2750
2751 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2752 temp_ff.full = dfixed_const(temp);
2753 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2754
2755 pix_clk.full = 0;
2756 pix_clk2.full = 0;
2757 peak_disp_bw.full = 0;
2758 if (mode1) {
2759 temp_ff.full = dfixed_const(1000);
2760 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2761 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2762 temp_ff.full = dfixed_const(pixel_bytes1);
2763 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2764 }
2765 if (mode2) {
2766 temp_ff.full = dfixed_const(1000);
2767 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2768 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2769 temp_ff.full = dfixed_const(pixel_bytes2);
2770 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2771 }
2772
2773 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2774 if (peak_disp_bw.full >= mem_bw.full) {
2775 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2776 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2777 }
2778
2779 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2780 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2781 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2782 mem_trcd = ((temp >> 2) & 0x3) + 1;
2783 mem_trp = ((temp & 0x3)) + 1;
2784 mem_tras = ((temp & 0x70) >> 4) + 1;
2785 } else if (rdev->family == CHIP_R300 ||
2786 rdev->family == CHIP_R350) { /* r300, r350 */
2787 mem_trcd = (temp & 0x7) + 1;
2788 mem_trp = ((temp >> 8) & 0x7) + 1;
2789 mem_tras = ((temp >> 11) & 0xf) + 4;
2790 } else if (rdev->family == CHIP_RV350 ||
2791 rdev->family <= CHIP_RV380) {
2792 /* rv3x0 */
2793 mem_trcd = (temp & 0x7) + 3;
2794 mem_trp = ((temp >> 8) & 0x7) + 3;
2795 mem_tras = ((temp >> 11) & 0xf) + 6;
2796 } else if (rdev->family == CHIP_R420 ||
2797 rdev->family == CHIP_R423 ||
2798 rdev->family == CHIP_RV410) {
2799 /* r4xx */
2800 mem_trcd = (temp & 0xf) + 3;
2801 if (mem_trcd > 15)
2802 mem_trcd = 15;
2803 mem_trp = ((temp >> 8) & 0xf) + 3;
2804 if (mem_trp > 15)
2805 mem_trp = 15;
2806 mem_tras = ((temp >> 12) & 0x1f) + 6;
2807 if (mem_tras > 31)
2808 mem_tras = 31;
2809 } else { /* RV200, R200 */
2810 mem_trcd = (temp & 0x7) + 1;
2811 mem_trp = ((temp >> 8) & 0x7) + 1;
2812 mem_tras = ((temp >> 12) & 0xf) + 4;
2813 }
2814 /* convert to FF */
2815 trcd_ff.full = dfixed_const(mem_trcd);
2816 trp_ff.full = dfixed_const(mem_trp);
2817 tras_ff.full = dfixed_const(mem_tras);
2818
2819 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2820 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2821 data = (temp & (7 << 20)) >> 20;
2822 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2823 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2824 tcas_ff = memtcas_rs480_ff[data];
2825 else
2826 tcas_ff = memtcas_ff[data];
2827 } else
2828 tcas_ff = memtcas2_ff[data];
2829
2830 if (rdev->family == CHIP_RS400 ||
2831 rdev->family == CHIP_RS480) {
2832 /* extra cas latency stored in bits 23-25 0-4 clocks */
2833 data = (temp >> 23) & 0x7;
2834 if (data < 5)
2835 tcas_ff.full += dfixed_const(data);
2836 }
2837
2838 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2839 /* on the R300, Tcas is included in Trbs.
2840 */
2841 temp = RREG32(RADEON_MEM_CNTL);
2842 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2843 if (data == 1) {
2844 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2845 temp = RREG32(R300_MC_IND_INDEX);
2846 temp &= ~R300_MC_IND_ADDR_MASK;
2847 temp |= R300_MC_READ_CNTL_CD_mcind;
2848 WREG32(R300_MC_IND_INDEX, temp);
2849 temp = RREG32(R300_MC_IND_DATA);
2850 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2851 } else {
2852 temp = RREG32(R300_MC_READ_CNTL_AB);
2853 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2854 }
2855 } else {
2856 temp = RREG32(R300_MC_READ_CNTL_AB);
2857 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2858 }
2859 if (rdev->family == CHIP_RV410 ||
2860 rdev->family == CHIP_R420 ||
2861 rdev->family == CHIP_R423)
2862 trbs_ff = memtrbs_r4xx[data];
2863 else
2864 trbs_ff = memtrbs[data];
2865 tcas_ff.full += trbs_ff.full;
2866 }
2867
2868 sclk_eff_ff.full = sclk_ff.full;
2869
2870 if (rdev->flags & RADEON_IS_AGP) {
2871 fixed20_12 agpmode_ff;
2872 agpmode_ff.full = dfixed_const(radeon_agpmode);
2873 temp_ff.full = dfixed_const_666(16);
2874 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
2875 }
2876 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2877
2878 if (ASIC_IS_R300(rdev)) {
2879 sclk_delay_ff.full = dfixed_const(250);
2880 } else {
2881 if ((rdev->family == CHIP_RV100) ||
2882 rdev->flags & RADEON_IS_IGP) {
2883 if (rdev->mc.vram_is_ddr)
2884 sclk_delay_ff.full = dfixed_const(41);
2885 else
2886 sclk_delay_ff.full = dfixed_const(33);
2887 } else {
2888 if (rdev->mc.vram_width == 128)
2889 sclk_delay_ff.full = dfixed_const(57);
2890 else
2891 sclk_delay_ff.full = dfixed_const(41);
2892 }
2893 }
2894
2895 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
2896
2897 if (rdev->mc.vram_is_ddr) {
2898 if (rdev->mc.vram_width == 32) {
2899 k1.full = dfixed_const(40);
2900 c = 3;
2901 } else {
2902 k1.full = dfixed_const(20);
2903 c = 1;
2904 }
2905 } else {
2906 k1.full = dfixed_const(40);
2907 c = 3;
2908 }
2909
2910 temp_ff.full = dfixed_const(2);
2911 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
2912 temp_ff.full = dfixed_const(c);
2913 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
2914 temp_ff.full = dfixed_const(4);
2915 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
2916 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
2917 mc_latency_mclk.full += k1.full;
2918
2919 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
2920 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
2921
2922 /*
2923 HW cursor time assuming worst case of full size colour cursor.
2924 */
2925 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2926 temp_ff.full += trcd_ff.full;
2927 if (temp_ff.full < tras_ff.full)
2928 temp_ff.full = tras_ff.full;
2929 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
2930
2931 temp_ff.full = dfixed_const(cur_size);
2932 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
2933 /*
2934 Find the total latency for the display data.
2935 */
2936 disp_latency_overhead.full = dfixed_const(8);
2937 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
2938 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2939 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2940
2941 if (mc_latency_mclk.full > mc_latency_sclk.full)
2942 disp_latency.full = mc_latency_mclk.full;
2943 else
2944 disp_latency.full = mc_latency_sclk.full;
2945
2946 /* setup Max GRPH_STOP_REQ default value */
2947 if (ASIC_IS_RV100(rdev))
2948 max_stop_req = 0x5c;
2949 else
2950 max_stop_req = 0x7c;
2951
2952 if (mode1) {
2953 /* CRTC1
2954 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2955 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2956 */
2957 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2958
2959 if (stop_req > max_stop_req)
2960 stop_req = max_stop_req;
2961
2962 /*
2963 Find the drain rate of the display buffer.
2964 */
2965 temp_ff.full = dfixed_const((16/pixel_bytes1));
2966 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
2967
2968 /*
2969 Find the critical point of the display buffer.
2970 */
2971 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
2972 crit_point_ff.full += dfixed_const_half(0);
2973
2974 critical_point = dfixed_trunc(crit_point_ff);
2975
2976 if (rdev->disp_priority == 2) {
2977 critical_point = 0;
2978 }
2979
2980 /*
2981 The critical point should never be above max_stop_req-4. Setting
2982 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2983 */
2984 if (max_stop_req - critical_point < 4)
2985 critical_point = 0;
2986
2987 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2988 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2989 critical_point = 0x10;
2990 }
2991
2992 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2993 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2994 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2995 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2996 if ((rdev->family == CHIP_R350) &&
2997 (stop_req > 0x15)) {
2998 stop_req -= 0x10;
2999 }
3000 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3001 temp |= RADEON_GRPH_BUFFER_SIZE;
3002 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3003 RADEON_GRPH_CRITICAL_AT_SOF |
3004 RADEON_GRPH_STOP_CNTL);
3005 /*
3006 Write the result into the register.
3007 */
3008 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3009 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3010
3011
3012 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3013 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3014 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3015 }
3016
3017 if (mode2) {
3018 u32 grph2_cntl;
3019 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3020
3021 if (stop_req > max_stop_req)
3022 stop_req = max_stop_req;
3023
3024 /*
3025 Find the drain rate of the display buffer.
3026 */
3027 temp_ff.full = dfixed_const((16/pixel_bytes2));
3028 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3029
3030 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3031 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3032 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3033 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3034 if ((rdev->family == CHIP_R350) &&
3035 (stop_req > 0x15)) {
3036 stop_req -= 0x10;
3037 }
3038 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3039 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3040 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3041 RADEON_GRPH_CRITICAL_AT_SOF |
3042 RADEON_GRPH_STOP_CNTL);
3043
3044 if ((rdev->family == CHIP_RS100) ||
3045 (rdev->family == CHIP_RS200))
3046 critical_point2 = 0;
3047 else {
3048 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3049 temp_ff.full = dfixed_const(temp);
3050 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3051 if (sclk_ff.full < temp_ff.full)
3052 temp_ff.full = sclk_ff.full;
3053
3054 read_return_rate.full = temp_ff.full;
3055
3056 if (mode1) {
3057 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3058 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3059 } else {
3060 time_disp1_drop_priority.full = 0;
3061 }
3062 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3063 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3064 crit_point_ff.full += dfixed_const_half(0);
3065
3066 critical_point2 = dfixed_trunc(crit_point_ff);
3067
3068 if (rdev->disp_priority == 2) {
3069 critical_point2 = 0;
3070 }
3071
3072 if (max_stop_req - critical_point2 < 4)
3073 critical_point2 = 0;
3074
3075 }
3076
3077 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3078 /* some R300 cards have problem with this set to 0 */
3079 critical_point2 = 0x10;
3080 }
3081
3082 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3083 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3084
3085 if ((rdev->family == CHIP_RS400) ||
3086 (rdev->family == CHIP_RS480)) {
3087 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3088 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3089 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3090 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3091 }
3092
3093 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3094 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3095 }
3096 }
3097
3098 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3099 {
3100 DRM_ERROR("pitch %d\n", t->pitch);
3101 DRM_ERROR("use_pitch %d\n", t->use_pitch);
3102 DRM_ERROR("width %d\n", t->width);
3103 DRM_ERROR("width_11 %d\n", t->width_11);
3104 DRM_ERROR("height %d\n", t->height);
3105 DRM_ERROR("height_11 %d\n", t->height_11);
3106 DRM_ERROR("num levels %d\n", t->num_levels);
3107 DRM_ERROR("depth %d\n", t->txdepth);
3108 DRM_ERROR("bpp %d\n", t->cpp);
3109 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
3110 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
3111 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3112 DRM_ERROR("compress format %d\n", t->compress_format);
3113 }
3114
3115 static int r100_track_compress_size(int compress_format, int w, int h)
3116 {
3117 int block_width, block_height, block_bytes;
3118 int wblocks, hblocks;
3119 int min_wblocks;
3120 int sz;
3121
3122 block_width = 4;
3123 block_height = 4;
3124
3125 switch (compress_format) {
3126 case R100_TRACK_COMP_DXT1:
3127 block_bytes = 8;
3128 min_wblocks = 4;
3129 break;
3130 default:
3131 case R100_TRACK_COMP_DXT35:
3132 block_bytes = 16;
3133 min_wblocks = 2;
3134 break;
3135 }
3136
3137 hblocks = (h + block_height - 1) / block_height;
3138 wblocks = (w + block_width - 1) / block_width;
3139 if (wblocks < min_wblocks)
3140 wblocks = min_wblocks;
3141 sz = wblocks * hblocks * block_bytes;
3142 return sz;
3143 }
3144
3145 static int r100_cs_track_cube(struct radeon_device *rdev,
3146 struct r100_cs_track *track, unsigned idx)
3147 {
3148 unsigned face, w, h;
3149 struct radeon_bo *cube_robj;
3150 unsigned long size;
3151 unsigned compress_format = track->textures[idx].compress_format;
3152
3153 for (face = 0; face < 5; face++) {
3154 cube_robj = track->textures[idx].cube_info[face].robj;
3155 w = track->textures[idx].cube_info[face].width;
3156 h = track->textures[idx].cube_info[face].height;
3157
3158 if (compress_format) {
3159 size = r100_track_compress_size(compress_format, w, h);
3160 } else
3161 size = w * h;
3162 size *= track->textures[idx].cpp;
3163
3164 size += track->textures[idx].cube_info[face].offset;
3165
3166 if (size > radeon_bo_size(cube_robj)) {
3167 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3168 size, radeon_bo_size(cube_robj));
3169 r100_cs_track_texture_print(&track->textures[idx]);
3170 return -1;
3171 }
3172 }
3173 return 0;
3174 }
3175
3176 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3177 struct r100_cs_track *track)
3178 {
3179 struct radeon_bo *robj;
3180 unsigned long size;
3181 unsigned u, i, w, h, d;
3182 int ret;
3183
3184 for (u = 0; u < track->num_texture; u++) {
3185 if (!track->textures[u].enabled)
3186 continue;
3187 if (track->textures[u].lookup_disable)
3188 continue;
3189 robj = track->textures[u].robj;
3190 if (robj == NULL) {
3191 DRM_ERROR("No texture bound to unit %u\n", u);
3192 return -EINVAL;
3193 }
3194 size = 0;
3195 for (i = 0; i <= track->textures[u].num_levels; i++) {
3196 if (track->textures[u].use_pitch) {
3197 if (rdev->family < CHIP_R300)
3198 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3199 else
3200 w = track->textures[u].pitch / (1 << i);
3201 } else {
3202 w = track->textures[u].width;
3203 if (rdev->family >= CHIP_RV515)
3204 w |= track->textures[u].width_11;
3205 w = w / (1 << i);
3206 if (track->textures[u].roundup_w)
3207 w = roundup_pow_of_two(w);
3208 }
3209 h = track->textures[u].height;
3210 if (rdev->family >= CHIP_RV515)
3211 h |= track->textures[u].height_11;
3212 h = h / (1 << i);
3213 if (track->textures[u].roundup_h)
3214 h = roundup_pow_of_two(h);
3215 if (track->textures[u].tex_coord_type == 1) {
3216 d = (1 << track->textures[u].txdepth) / (1 << i);
3217 if (!d)
3218 d = 1;
3219 } else {
3220 d = 1;
3221 }
3222 if (track->textures[u].compress_format) {
3223
3224 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3225 /* compressed textures are block based */
3226 } else
3227 size += w * h * d;
3228 }
3229 size *= track->textures[u].cpp;
3230
3231 switch (track->textures[u].tex_coord_type) {
3232 case 0:
3233 case 1:
3234 break;
3235 case 2:
3236 if (track->separate_cube) {
3237 ret = r100_cs_track_cube(rdev, track, u);
3238 if (ret)
3239 return ret;
3240 } else
3241 size *= 6;
3242 break;
3243 default:
3244 DRM_ERROR("Invalid texture coordinate type %u for unit "
3245 "%u\n", track->textures[u].tex_coord_type, u);
3246 return -EINVAL;
3247 }
3248 if (size > radeon_bo_size(robj)) {
3249 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3250 "%lu\n", u, size, radeon_bo_size(robj));
3251 r100_cs_track_texture_print(&track->textures[u]);
3252 return -EINVAL;
3253 }
3254 }
3255 return 0;
3256 }
3257
3258 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3259 {
3260 unsigned i;
3261 unsigned long size;
3262 unsigned prim_walk;
3263 unsigned nverts;
3264 unsigned num_cb = track->num_cb;
3265
3266 if (!track->zb_cb_clear && !track->color_channel_mask &&
3267 !track->blend_read_enable)
3268 num_cb = 0;
3269
3270 for (i = 0; i < num_cb; i++) {
3271 if (track->cb[i].robj == NULL) {
3272 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3273 return -EINVAL;
3274 }
3275 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3276 size += track->cb[i].offset;
3277 if (size > radeon_bo_size(track->cb[i].robj)) {
3278 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3279 "(need %lu have %lu) !\n", i, size,
3280 radeon_bo_size(track->cb[i].robj));
3281 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3282 i, track->cb[i].pitch, track->cb[i].cpp,
3283 track->cb[i].offset, track->maxy);
3284 return -EINVAL;
3285 }
3286 }
3287 if (track->z_enabled) {
3288 if (track->zb.robj == NULL) {
3289 DRM_ERROR("[drm] No buffer for z buffer !\n");
3290 return -EINVAL;
3291 }
3292 size = track->zb.pitch * track->zb.cpp * track->maxy;
3293 size += track->zb.offset;
3294 if (size > radeon_bo_size(track->zb.robj)) {
3295 DRM_ERROR("[drm] Buffer too small for z buffer "
3296 "(need %lu have %lu) !\n", size,
3297 radeon_bo_size(track->zb.robj));
3298 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3299 track->zb.pitch, track->zb.cpp,
3300 track->zb.offset, track->maxy);
3301 return -EINVAL;
3302 }
3303 }
3304 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3305 if (track->vap_vf_cntl & (1 << 14)) {
3306 nverts = track->vap_alt_nverts;
3307 } else {
3308 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3309 }
3310 switch (prim_walk) {
3311 case 1:
3312 for (i = 0; i < track->num_arrays; i++) {
3313 size = track->arrays[i].esize * track->max_indx * 4;
3314 if (track->arrays[i].robj == NULL) {
3315 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3316 "bound\n", prim_walk, i);
3317 return -EINVAL;
3318 }
3319 if (size > radeon_bo_size(track->arrays[i].robj)) {
3320 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3321 "need %lu dwords have %lu dwords\n",
3322 prim_walk, i, size >> 2,
3323 radeon_bo_size(track->arrays[i].robj)
3324 >> 2);
3325 DRM_ERROR("Max indices %u\n", track->max_indx);
3326 return -EINVAL;
3327 }
3328 }
3329 break;
3330 case 2:
3331 for (i = 0; i < track->num_arrays; i++) {
3332 size = track->arrays[i].esize * (nverts - 1) * 4;
3333 if (track->arrays[i].robj == NULL) {
3334 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3335 "bound\n", prim_walk, i);
3336 return -EINVAL;
3337 }
3338 if (size > radeon_bo_size(track->arrays[i].robj)) {
3339 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3340 "need %lu dwords have %lu dwords\n",
3341 prim_walk, i, size >> 2,
3342 radeon_bo_size(track->arrays[i].robj)
3343 >> 2);
3344 return -EINVAL;
3345 }
3346 }
3347 break;
3348 case 3:
3349 size = track->vtx_size * nverts;
3350 if (size != track->immd_dwords) {
3351 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3352 track->immd_dwords, size);
3353 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3354 nverts, track->vtx_size);
3355 return -EINVAL;
3356 }
3357 break;
3358 default:
3359 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3360 prim_walk);
3361 return -EINVAL;
3362 }
3363 return r100_cs_track_texture_check(rdev, track);
3364 }
3365
3366 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3367 {
3368 unsigned i, face;
3369
3370 if (rdev->family < CHIP_R300) {
3371 track->num_cb = 1;
3372 if (rdev->family <= CHIP_RS200)
3373 track->num_texture = 3;
3374 else
3375 track->num_texture = 6;
3376 track->maxy = 2048;
3377 track->separate_cube = 1;
3378 } else {
3379 track->num_cb = 4;
3380 track->num_texture = 16;
3381 track->maxy = 4096;
3382 track->separate_cube = 0;
3383 }
3384
3385 for (i = 0; i < track->num_cb; i++) {
3386 track->cb[i].robj = NULL;
3387 track->cb[i].pitch = 8192;
3388 track->cb[i].cpp = 16;
3389 track->cb[i].offset = 0;
3390 }
3391 track->z_enabled = true;
3392 track->zb.robj = NULL;
3393 track->zb.pitch = 8192;
3394 track->zb.cpp = 4;
3395 track->zb.offset = 0;
3396 track->vtx_size = 0x7F;
3397 track->immd_dwords = 0xFFFFFFFFUL;
3398 track->num_arrays = 11;
3399 track->max_indx = 0x00FFFFFFUL;
3400 for (i = 0; i < track->num_arrays; i++) {
3401 track->arrays[i].robj = NULL;
3402 track->arrays[i].esize = 0x7F;
3403 }
3404 for (i = 0; i < track->num_texture; i++) {
3405 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3406 track->textures[i].pitch = 16536;
3407 track->textures[i].width = 16536;
3408 track->textures[i].height = 16536;
3409 track->textures[i].width_11 = 1 << 11;
3410 track->textures[i].height_11 = 1 << 11;
3411 track->textures[i].num_levels = 12;
3412 if (rdev->family <= CHIP_RS200) {
3413 track->textures[i].tex_coord_type = 0;
3414 track->textures[i].txdepth = 0;
3415 } else {
3416 track->textures[i].txdepth = 16;
3417 track->textures[i].tex_coord_type = 1;
3418 }
3419 track->textures[i].cpp = 64;
3420 track->textures[i].robj = NULL;
3421 /* CS IB emission code makes sure texture unit are disabled */
3422 track->textures[i].enabled = false;
3423 track->textures[i].lookup_disable = false;
3424 track->textures[i].roundup_w = true;
3425 track->textures[i].roundup_h = true;
3426 if (track->separate_cube)
3427 for (face = 0; face < 5; face++) {
3428 track->textures[i].cube_info[face].robj = NULL;
3429 track->textures[i].cube_info[face].width = 16536;
3430 track->textures[i].cube_info[face].height = 16536;
3431 track->textures[i].cube_info[face].offset = 0;
3432 }
3433 }
3434 }
3435
3436 int r100_ring_test(struct radeon_device *rdev)
3437 {
3438 uint32_t scratch;
3439 uint32_t tmp = 0;
3440 unsigned i;
3441 int r;
3442
3443 r = radeon_scratch_get(rdev, &scratch);
3444 if (r) {
3445 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3446 return r;
3447 }
3448 WREG32(scratch, 0xCAFEDEAD);
3449 r = radeon_ring_lock(rdev, 2);
3450 if (r) {
3451 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3452 radeon_scratch_free(rdev, scratch);
3453 return r;
3454 }
3455 radeon_ring_write(rdev, PACKET0(scratch, 0));
3456 radeon_ring_write(rdev, 0xDEADBEEF);
3457 radeon_ring_unlock_commit(rdev);
3458 for (i = 0; i < rdev->usec_timeout; i++) {
3459 tmp = RREG32(scratch);
3460 if (tmp == 0xDEADBEEF) {
3461 break;
3462 }
3463 DRM_UDELAY(1);
3464 }
3465 if (i < rdev->usec_timeout) {
3466 DRM_INFO("ring test succeeded in %d usecs\n", i);
3467 } else {
3468 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3469 scratch, tmp);
3470 r = -EINVAL;
3471 }
3472 radeon_scratch_free(rdev, scratch);
3473 return r;
3474 }
3475
3476 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3477 {
3478 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3479 radeon_ring_write(rdev, ib->gpu_addr);
3480 radeon_ring_write(rdev, ib->length_dw);
3481 }
3482
3483 int r100_ib_test(struct radeon_device *rdev)
3484 {
3485 struct radeon_ib *ib;
3486 uint32_t scratch;
3487 uint32_t tmp = 0;
3488 unsigned i;
3489 int r;
3490
3491 r = radeon_scratch_get(rdev, &scratch);
3492 if (r) {
3493 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3494 return r;
3495 }
3496 WREG32(scratch, 0xCAFEDEAD);
3497 r = radeon_ib_get(rdev, &ib);
3498 if (r) {
3499 return r;
3500 }
3501 ib->ptr[0] = PACKET0(scratch, 0);
3502 ib->ptr[1] = 0xDEADBEEF;
3503 ib->ptr[2] = PACKET2(0);
3504 ib->ptr[3] = PACKET2(0);
3505 ib->ptr[4] = PACKET2(0);
3506 ib->ptr[5] = PACKET2(0);
3507 ib->ptr[6] = PACKET2(0);
3508 ib->ptr[7] = PACKET2(0);
3509 ib->length_dw = 8;
3510 r = radeon_ib_schedule(rdev, ib);
3511 if (r) {
3512 radeon_scratch_free(rdev, scratch);
3513 radeon_ib_free(rdev, &ib);
3514 return r;
3515 }
3516 r = radeon_fence_wait(ib->fence, false);
3517 if (r) {
3518 return r;
3519 }
3520 for (i = 0; i < rdev->usec_timeout; i++) {
3521 tmp = RREG32(scratch);
3522 if (tmp == 0xDEADBEEF) {
3523 break;
3524 }
3525 DRM_UDELAY(1);
3526 }
3527 if (i < rdev->usec_timeout) {
3528 DRM_INFO("ib test succeeded in %u usecs\n", i);
3529 } else {
3530 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3531 scratch, tmp);
3532 r = -EINVAL;
3533 }
3534 radeon_scratch_free(rdev, scratch);
3535 radeon_ib_free(rdev, &ib);
3536 return r;
3537 }
3538
3539 void r100_ib_fini(struct radeon_device *rdev)
3540 {
3541 radeon_ib_pool_fini(rdev);
3542 }
3543
3544 int r100_ib_init(struct radeon_device *rdev)
3545 {
3546 int r;
3547
3548 r = radeon_ib_pool_init(rdev);
3549 if (r) {
3550 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3551 r100_ib_fini(rdev);
3552 return r;
3553 }
3554 r = r100_ib_test(rdev);
3555 if (r) {
3556 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3557 r100_ib_fini(rdev);
3558 return r;
3559 }
3560 return 0;
3561 }
3562
3563 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3564 {
3565 /* Shutdown CP we shouldn't need to do that but better be safe than
3566 * sorry
3567 */
3568 rdev->cp.ready = false;
3569 WREG32(R_000740_CP_CSQ_CNTL, 0);
3570
3571 /* Save few CRTC registers */
3572 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3573 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3574 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3575 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3576 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3577 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3578 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3579 }
3580
3581 /* Disable VGA aperture access */
3582 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3583 /* Disable cursor, overlay, crtc */
3584 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3585 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3586 S_000054_CRTC_DISPLAY_DIS(1));
3587 WREG32(R_000050_CRTC_GEN_CNTL,
3588 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3589 S_000050_CRTC_DISP_REQ_EN_B(1));
3590 WREG32(R_000420_OV0_SCALE_CNTL,
3591 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3592 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3593 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3594 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3595 S_000360_CUR2_LOCK(1));
3596 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3597 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3598 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3599 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3600 WREG32(R_000360_CUR2_OFFSET,
3601 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3602 }
3603 }
3604
3605 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3606 {
3607 /* Update base address for crtc */
3608 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3609 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3610 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3611 }
3612 /* Restore CRTC registers */
3613 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3614 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3615 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3616 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3617 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3618 }
3619 }
3620
3621 void r100_vga_render_disable(struct radeon_device *rdev)
3622 {
3623 u32 tmp;
3624
3625 tmp = RREG8(R_0003C2_GENMO_WT);
3626 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3627 }
3628
3629 static void r100_debugfs(struct radeon_device *rdev)
3630 {
3631 int r;
3632
3633 r = r100_debugfs_mc_info_init(rdev);
3634 if (r)
3635 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3636 }
3637
3638 static void r100_mc_program(struct radeon_device *rdev)
3639 {
3640 struct r100_mc_save save;
3641
3642 /* Stops all mc clients */
3643 r100_mc_stop(rdev, &save);
3644 if (rdev->flags & RADEON_IS_AGP) {
3645 WREG32(R_00014C_MC_AGP_LOCATION,
3646 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3647 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3648 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3649 if (rdev->family > CHIP_RV200)
3650 WREG32(R_00015C_AGP_BASE_2,
3651 upper_32_bits(rdev->mc.agp_base) & 0xff);
3652 } else {
3653 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3654 WREG32(R_000170_AGP_BASE, 0);
3655 if (rdev->family > CHIP_RV200)
3656 WREG32(R_00015C_AGP_BASE_2, 0);
3657 }
3658 /* Wait for mc idle */
3659 if (r100_mc_wait_for_idle(rdev))
3660 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3661 /* Program MC, should be a 32bits limited address space */
3662 WREG32(R_000148_MC_FB_LOCATION,
3663 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3664 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3665 r100_mc_resume(rdev, &save);
3666 }
3667
3668 void r100_clock_startup(struct radeon_device *rdev)
3669 {
3670 u32 tmp;
3671
3672 if (radeon_dynclks != -1 && radeon_dynclks)
3673 radeon_legacy_set_clock_gating(rdev, 1);
3674 /* We need to force on some of the block */
3675 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3676 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3677 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3678 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3679 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3680 }
3681
3682 static int r100_startup(struct radeon_device *rdev)
3683 {
3684 int r;
3685
3686 /* set common regs */
3687 r100_set_common_regs(rdev);
3688 /* program mc */
3689 r100_mc_program(rdev);
3690 /* Resume clock */
3691 r100_clock_startup(rdev);
3692 /* Initialize GPU configuration (# pipes, ...) */
3693 // r100_gpu_init(rdev);
3694 /* Initialize GART (initialize after TTM so we can allocate
3695 * memory through TTM but finalize after TTM) */
3696 r100_enable_bm(rdev);
3697 if (rdev->flags & RADEON_IS_PCI) {
3698 r = r100_pci_gart_enable(rdev);
3699 if (r)
3700 return r;
3701 }
3702 /* Enable IRQ */
3703 r100_irq_set(rdev);
3704 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3705 /* 1M ring buffer */
3706 r = r100_cp_init(rdev, 1024 * 1024);
3707 if (r) {
3708 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3709 return r;
3710 }
3711 r = r100_wb_init(rdev);
3712 if (r)
3713 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3714 r = r100_ib_init(rdev);
3715 if (r) {
3716 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3717 return r;
3718 }
3719 return 0;
3720 }
3721
3722 int r100_resume(struct radeon_device *rdev)
3723 {
3724 /* Make sur GART are not working */
3725 if (rdev->flags & RADEON_IS_PCI)
3726 r100_pci_gart_disable(rdev);
3727 /* Resume clock before doing reset */
3728 r100_clock_startup(rdev);
3729 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3730 if (radeon_asic_reset(rdev)) {
3731 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3732 RREG32(R_000E40_RBBM_STATUS),
3733 RREG32(R_0007C0_CP_STAT));
3734 }
3735 /* post */
3736 radeon_combios_asic_init(rdev->ddev);
3737 /* Resume clock after posting */
3738 r100_clock_startup(rdev);
3739 /* Initialize surface registers */
3740 radeon_surface_init(rdev);
3741 return r100_startup(rdev);
3742 }
3743
3744 int r100_suspend(struct radeon_device *rdev)
3745 {
3746 r100_cp_disable(rdev);
3747 r100_wb_disable(rdev);
3748 r100_irq_disable(rdev);
3749 if (rdev->flags & RADEON_IS_PCI)
3750 r100_pci_gart_disable(rdev);
3751 return 0;
3752 }
3753
3754 void r100_fini(struct radeon_device *rdev)
3755 {
3756 r100_cp_fini(rdev);
3757 r100_wb_fini(rdev);
3758 r100_ib_fini(rdev);
3759 radeon_gem_fini(rdev);
3760 if (rdev->flags & RADEON_IS_PCI)
3761 r100_pci_gart_fini(rdev);
3762 radeon_agp_fini(rdev);
3763 radeon_irq_kms_fini(rdev);
3764 radeon_fence_driver_fini(rdev);
3765 radeon_bo_fini(rdev);
3766 radeon_atombios_fini(rdev);
3767 kfree(rdev->bios);
3768 rdev->bios = NULL;
3769 }
3770
3771 /*
3772 * Due to how kexec works, it can leave the hw fully initialised when it
3773 * boots the new kernel. However doing our init sequence with the CP and
3774 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3775 * do some quick sanity checks and restore sane values to avoid this
3776 * problem.
3777 */
3778 void r100_restore_sanity(struct radeon_device *rdev)
3779 {
3780 u32 tmp;
3781
3782 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3783 if (tmp) {
3784 WREG32(RADEON_CP_CSQ_CNTL, 0);
3785 }
3786 tmp = RREG32(RADEON_CP_RB_CNTL);
3787 if (tmp) {
3788 WREG32(RADEON_CP_RB_CNTL, 0);
3789 }
3790 tmp = RREG32(RADEON_SCRATCH_UMSK);
3791 if (tmp) {
3792 WREG32(RADEON_SCRATCH_UMSK, 0);
3793 }
3794 }
3795
3796 int r100_init(struct radeon_device *rdev)
3797 {
3798 int r;
3799
3800 /* Register debugfs file specific to this group of asics */
3801 r100_debugfs(rdev);
3802 /* Disable VGA */
3803 r100_vga_render_disable(rdev);
3804 /* Initialize scratch registers */
3805 radeon_scratch_init(rdev);
3806 /* Initialize surface registers */
3807 radeon_surface_init(rdev);
3808 /* sanity check some register to avoid hangs like after kexec */
3809 r100_restore_sanity(rdev);
3810 /* TODO: disable VGA need to use VGA request */
3811 /* BIOS*/
3812 if (!radeon_get_bios(rdev)) {
3813 if (ASIC_IS_AVIVO(rdev))
3814 return -EINVAL;
3815 }
3816 if (rdev->is_atom_bios) {
3817 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3818 return -EINVAL;
3819 } else {
3820 r = radeon_combios_init(rdev);
3821 if (r)
3822 return r;
3823 }
3824 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3825 if (radeon_asic_reset(rdev)) {
3826 dev_warn(rdev->dev,
3827 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3828 RREG32(R_000E40_RBBM_STATUS),
3829 RREG32(R_0007C0_CP_STAT));
3830 }
3831 /* check if cards are posted or not */
3832 if (radeon_boot_test_post_card(rdev) == false)
3833 return -EINVAL;
3834 /* Set asic errata */
3835 r100_errata(rdev);
3836 /* Initialize clocks */
3837 radeon_get_clock_info(rdev->ddev);
3838 /* initialize AGP */
3839 if (rdev->flags & RADEON_IS_AGP) {
3840 r = radeon_agp_init(rdev);
3841 if (r) {
3842 radeon_agp_disable(rdev);
3843 }
3844 }
3845 /* initialize VRAM */
3846 r100_mc_init(rdev);
3847 /* Fence driver */
3848 r = radeon_fence_driver_init(rdev);
3849 if (r)
3850 return r;
3851 r = radeon_irq_kms_init(rdev);
3852 if (r)
3853 return r;
3854 /* Memory manager */
3855 r = radeon_bo_init(rdev);
3856 if (r)
3857 return r;
3858 if (rdev->flags & RADEON_IS_PCI) {
3859 r = r100_pci_gart_init(rdev);
3860 if (r)
3861 return r;
3862 }
3863 r100_set_safe_registers(rdev);
3864 rdev->accel_working = true;
3865 r = r100_startup(rdev);
3866 if (r) {
3867 /* Somethings want wront with the accel init stop accel */
3868 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3869 r100_cp_fini(rdev);
3870 r100_wb_fini(rdev);
3871 r100_ib_fini(rdev);
3872 radeon_irq_kms_fini(rdev);
3873 if (rdev->flags & RADEON_IS_PCI)
3874 r100_pci_gart_fini(rdev);
3875 rdev->accel_working = false;
3876 }
3877 return 0;
3878 }
Tomato firmware and modifications.