release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/dma/ioat/dma_v2.h

   1 /*
   2  * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59
  16  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called COPYING.
  20  */
  21 #ifndef IOATDMA_V2_H
  22 #define IOATDMA_V2_H
  23
  24 #include <linux/dmaengine.h>
  25 #include <linux/circ_buf.h>
  26 #include "dma.h"
  27 #include "hw.h"
  28
  29
  30 extern int ioat_pending_level;
  31 extern int ioat_ring_alloc_order;
  32
  33 #define NULL_DESC_BUFFER_SIZE 1
  34
  35 #define IOAT_MAX_ORDER 16
  36 #define ioat_get_alloc_order() \
  37         (min(ioat_ring_alloc_order, IOAT_MAX_ORDER))
  38 #define ioat_get_max_alloc_order() \
  39         (min(ioat_ring_max_alloc_order, IOAT_MAX_ORDER))
  40
  41 /* struct ioat2_dma_chan - ioat v2 / v3 channel attributes
  42  * @base: common ioat channel parameters
  43  * @xfercap_log; log2 of channel max transfer length (for fast division)
  44  * @head: allocated index
  45  * @issued: hardware notification point
  46  * @tail: cleanup index
  47  * @dmacount: identical to 'head' except for occasionally resetting to zero
  48  * @alloc_order: log2 of the number of allocated descriptors
  49  * @produce: number of descriptors to produce at submit time
  50  * @ring: software ring buffer implementation of hardware ring
  51  * @prep_lock: serializes descriptor preparation (producers)
  52  */
  53 struct ioat2_dma_chan {
  54         struct ioat_chan_common base;
  55         size_t xfercap_log;
  56         u16 head;
  57         u16 issued;
  58         u16 tail;
  59         u16 dmacount;
  60         u16 alloc_order;
  61         u16 produce;
  62         struct ioat_ring_ent **ring;
  63         spinlock_t prep_lock;
  64 };
  65
  66 static inline struct ioat2_dma_chan *to_ioat2_chan(struct dma_chan *c)
  67 {
  68         struct ioat_chan_common *chan = to_chan_common(c);
  69
  70         return container_of(chan, struct ioat2_dma_chan, base);
  71 }
  72
  73 static inline u16 ioat2_ring_size(struct ioat2_dma_chan *ioat)
  74 {
  75         return 1 << ioat->alloc_order;
  76 }
  77
  78 /* count of descriptors in flight with the engine */
  79 static inline u16 ioat2_ring_active(struct ioat2_dma_chan *ioat)
  80 {
  81         return CIRC_CNT(ioat->head, ioat->tail, ioat2_ring_size(ioat));
  82 }
  83
  84 /* count of descriptors pending submission to hardware */
  85 static inline u16 ioat2_ring_pending(struct ioat2_dma_chan *ioat)
  86 {
  87         return CIRC_CNT(ioat->head, ioat->issued, ioat2_ring_size(ioat));
  88 }
  89
  90 static inline u16 ioat2_ring_space(struct ioat2_dma_chan *ioat)
  91 {
  92         return ioat2_ring_size(ioat) - ioat2_ring_active(ioat);
  93 }
  94
  95 static inline u16 ioat2_xferlen_to_descs(struct ioat2_dma_chan *ioat, size_t len)
  96 {
  97         u16 num_descs = len >> ioat->xfercap_log;
  98
  99         num_descs += !!(len & ((1 << ioat->xfercap_log) - 1));
 100         return num_descs;
 101 }
 102
 103 /**
 104  * struct ioat_ring_ent - wrapper around hardware descriptor
 105  * @hw: hardware DMA descriptor (for memcpy)
 106  * @fill: hardware fill descriptor
 107  * @xor: hardware xor descriptor
 108  * @xor_ex: hardware xor extension descriptor
 109  * @pq: hardware pq descriptor
 110  * @pq_ex: hardware pq extension descriptor
 111  * @pqu: hardware pq update descriptor
 112  * @raw: hardware raw (un-typed) descriptor
 113  * @txd: the generic software descriptor for all engines
 114  * @len: total transaction length for unmap
 115  * @result: asynchronous result of validate operations
 116  * @id: identifier for debug
 117  */
 118
 119 struct ioat_ring_ent {
 120         union {
 121                 struct ioat_dma_descriptor *hw;
 122                 struct ioat_fill_descriptor *fill;
 123                 struct ioat_xor_descriptor *xor;
 124                 struct ioat_xor_ext_descriptor *xor_ex;
 125                 struct ioat_pq_descriptor *pq;
 126                 struct ioat_pq_ext_descriptor *pq_ex;
 127                 struct ioat_pq_update_descriptor *pqu;
 128                 struct ioat_raw_descriptor *raw;
 129         };
 130         size_t len;
 131         struct dma_async_tx_descriptor txd;
 132         enum sum_check_flags *result;
 133         #ifdef DEBUG
 134         int id;
 135         #endif
 136 };
 137
 138 static inline struct ioat_ring_ent *
 139 ioat2_get_ring_ent(struct ioat2_dma_chan *ioat, u16 idx)
 140 {
 141         return ioat->ring[idx & (ioat2_ring_size(ioat) - 1)];
 142 }
 143
 144 static inline void ioat2_set_chainaddr(struct ioat2_dma_chan *ioat, u64 addr)
 145 {
 146         struct ioat_chan_common *chan = &ioat->base;
 147
 148         writel(addr & 0x00000000FFFFFFFF,
 149                chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
 150         writel(addr >> 32,
 151                chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
 152 }
 153
 154 int __devinit ioat2_dma_probe(struct ioatdma_device *dev, int dca);
 155 int __devinit ioat3_dma_probe(struct ioatdma_device *dev, int dca);
 156 struct dca_provider * __devinit ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase);
 157 struct dca_provider * __devinit ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase);
 158 int ioat2_check_space_lock(struct ioat2_dma_chan *ioat, int num_descs);
 159 int ioat2_enumerate_channels(struct ioatdma_device *device);
 160 struct dma_async_tx_descriptor *
 161 ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
 162                            dma_addr_t dma_src, size_t len, unsigned long flags);
 163 void ioat2_issue_pending(struct dma_chan *chan);
 164 int ioat2_alloc_chan_resources(struct dma_chan *c);
 165 void ioat2_free_chan_resources(struct dma_chan *c);
 166 void __ioat2_restart_chan(struct ioat2_dma_chan *ioat);
 167 bool reshape_ring(struct ioat2_dma_chan *ioat, int order);
 168 void __ioat2_issue_pending(struct ioat2_dma_chan *ioat);
 169 void ioat2_cleanup_event(unsigned long data);
 170 void ioat2_timer_event(unsigned long data);
 171 int ioat2_quiesce(struct ioat_chan_common *chan, unsigned long tmo);
 172 int ioat2_reset_sync(struct ioat_chan_common *chan, unsigned long tmo);
 173 extern struct kobj_type ioat2_ktype;
 174 extern struct kmem_cache *ioat2_cache;
 175 #endif /* IOATDMA_V2_H */