release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/dma/ioat/dma.h

   1 /*
   2  * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59
  16  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called COPYING.
  20  */
  21 #ifndef IOATDMA_H
  22 #define IOATDMA_H
  23
  24 #include <linux/dmaengine.h>
  25 #include "hw.h"
  26 #include "registers.h"
  27 #include <linux/init.h>
  28 #include <linux/dmapool.h>
  29 #include <linux/cache.h>
  30 #include <linux/pci_ids.h>
  31 #include <net/tcp.h>
  32
  33 #define IOAT_DMA_VERSION  "4.00"
  34
  35 #define IOAT_LOW_COMPLETION_MASK        0xffffffc0
  36 #define IOAT_DMA_DCA_ANY_CPU            ~0
  37
  38 #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
  39 #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
  40 #define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
  41 #define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
  42
  43 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
  44
  45 #define NULL_DESC_BUFFER_SIZE 1
  46
  47 /**
  48  * struct ioatdma_device - internal representation of a IOAT device
  49  * @pdev: PCI-Express device
  50  * @reg_base: MMIO register space base address
  51  * @dma_pool: for allocating DMA descriptors
  52  * @common: embedded struct dma_device
  53  * @version: version of ioatdma device
  54  * @msix_entries: irq handlers
  55  * @idx: per channel data
  56  * @dca: direct cache access context
  57  * @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
  58  * @enumerate_channels: hw version specific channel enumeration
  59  * @reset_hw: hw version specific channel (re)initialization
  60  * @cleanup_fn: select between the v2 and v3 cleanup routines
  61  * @timer_fn: select between the v2 and v3 timer watchdog routines
  62  * @self_test: hardware version specific self test for each supported op type
  63  *
  64  * Note: the v3 cleanup routine supports raid operations
  65  */
  66 struct ioatdma_device {
  67         struct pci_dev *pdev;
  68         void __iomem *reg_base;
  69         struct pci_pool *dma_pool;
  70         struct pci_pool *completion_pool;
  71         struct dma_device common;
  72         u8 version;
  73         struct msix_entry msix_entries[4];
  74         struct ioat_chan_common *idx[4];
  75         struct dca_provider *dca;
  76         void (*intr_quirk)(struct ioatdma_device *device);
  77         int (*enumerate_channels)(struct ioatdma_device *device);
  78         int (*reset_hw)(struct ioat_chan_common *chan);
  79         void (*cleanup_fn)(unsigned long data);
  80         void (*timer_fn)(unsigned long data);
  81         int (*self_test)(struct ioatdma_device *device);
  82 };
  83
  84 struct ioat_chan_common {
  85         struct dma_chan common;
  86         void __iomem *reg_base;
  87         unsigned long last_completion;
  88         spinlock_t cleanup_lock;
  89         dma_cookie_t completed_cookie;
  90         unsigned long state;
  91         #define IOAT_COMPLETION_PENDING 0
  92         #define IOAT_COMPLETION_ACK 1
  93         #define IOAT_RESET_PENDING 2
  94         #define IOAT_KOBJ_INIT_FAIL 3
  95         #define IOAT_RESHAPE_PENDING 4
  96         #define IOAT_RUN 5
  97         struct timer_list timer;
  98         #define COMPLETION_TIMEOUT msecs_to_jiffies(100)
  99         #define IDLE_TIMEOUT msecs_to_jiffies(2000)
 100         #define RESET_DELAY msecs_to_jiffies(100)
 101         struct ioatdma_device *device;
 102         dma_addr_t completion_dma;
 103         u64 *completion;
 104         struct tasklet_struct cleanup_task;
 105         struct kobject kobj;
 106 };
 107
 108 struct ioat_sysfs_entry {
 109         struct attribute attr;
 110         ssize_t (*show)(struct dma_chan *, char *);
 111 };
 112
 113 /**
 114  * struct ioat_dma_chan - internal representation of a DMA channel
 115  */
 116 struct ioat_dma_chan {
 117         struct ioat_chan_common base;
 118
 119         size_t xfercap; /* XFERCAP register value expanded out */
 120
 121         spinlock_t desc_lock;
 122         struct list_head free_desc;
 123         struct list_head used_desc;
 124
 125         int pending;
 126         u16 desccount;
 127         u16 active;
 128 };
 129
 130 static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c)
 131 {
 132         return container_of(c, struct ioat_chan_common, common);
 133 }
 134
 135 static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c)
 136 {
 137         struct ioat_chan_common *chan = to_chan_common(c);
 138
 139         return container_of(chan, struct ioat_dma_chan, base);
 140 }
 141
 142 /**
 143  * ioat_tx_status - poll the status of an ioat transaction
 144  * @c: channel handle
 145  * @cookie: transaction identifier
 146  * @txstate: if set, updated with the transaction state
 147  */
 148 static inline enum dma_status
 149 ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie,
 150                  struct dma_tx_state *txstate)
 151 {
 152         struct ioat_chan_common *chan = to_chan_common(c);
 153         dma_cookie_t last_used;
 154         dma_cookie_t last_complete;
 155
 156         last_used = c->cookie;
 157         last_complete = chan->completed_cookie;
 158
 159         dma_set_tx_state(txstate, last_complete, last_used, 0);
 160
 161         return dma_async_is_complete(cookie, last_complete, last_used);
 162 }
 163
 164 /* wrapper around hardware descriptor format + additional software fields */
 165
 166 /**
 167  * struct ioat_desc_sw - wrapper around hardware descriptor
 168  * @hw: hardware DMA descriptor (for memcpy)
 169  * @node: this descriptor will either be on the free list,
 170  *     or attached to a transaction list (tx_list)
 171  * @txd: the generic software descriptor for all engines
 172  * @id: identifier for debug
 173  */
 174 struct ioat_desc_sw {
 175         struct ioat_dma_descriptor *hw;
 176         struct list_head node;
 177         size_t len;
 178         struct list_head tx_list;
 179         struct dma_async_tx_descriptor txd;
 180         #ifdef DEBUG
 181         int id;
 182         #endif
 183 };
 184
 185 #ifdef DEBUG
 186 #define set_desc_id(desc, i) ((desc)->id = (i))
 187 #define desc_id(desc) ((desc)->id)
 188 #else
 189 #define set_desc_id(desc, i)
 190 #define desc_id(desc) (0)
 191 #endif
 192
 193 static inline void
 194 __dump_desc_dbg(struct ioat_chan_common *chan, struct ioat_dma_descriptor *hw,
 195                 struct dma_async_tx_descriptor *tx, int id)
 196 {
 197         struct device *dev = to_dev(chan);
 198
 199         dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
 200                 " ctl: %#x (op: %d int_en: %d compl: %d)\n", id,
 201                 (unsigned long long) tx->phys,
 202                 (unsigned long long) hw->next, tx->cookie, tx->flags,
 203                 hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
 204 }
 205
 206 #define dump_desc_dbg(c, d) \
 207         ({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; })
 208
 209 static inline void ioat_set_tcp_copy_break(unsigned long copybreak)
 210 {
 211         #ifdef CONFIG_NET_DMA
 212         sysctl_tcp_dma_copybreak = copybreak;
 213         #endif
 214 }
 215
 216 static inline struct ioat_chan_common *
 217 ioat_chan_by_index(struct ioatdma_device *device, int index)
 218 {
 219         return device->idx[index];
 220 }
 221
 222 static inline u64 ioat_chansts(struct ioat_chan_common *chan)
 223 {
 224         u8 ver = chan->device->version;
 225         u64 status;
 226         u32 status_lo;
 227
 228         /* We need to read the low address first as this causes the
 229          * chipset to latch the upper bits for the subsequent read
 230          */
 231         status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver));
 232         status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver));
 233         status <<= 32;
 234         status |= status_lo;
 235
 236         return status;
 237 }
 238
 239 static inline void ioat_start(struct ioat_chan_common *chan)
 240 {
 241         u8 ver = chan->device->version;
 242
 243         writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
 244 }
 245
 246 static inline u64 ioat_chansts_to_addr(u64 status)
 247 {
 248         return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
 249 }
 250
 251 static inline u32 ioat_chanerr(struct ioat_chan_common *chan)
 252 {
 253         return readl(chan->reg_base + IOAT_CHANERR_OFFSET);
 254 }
 255
 256 static inline void ioat_suspend(struct ioat_chan_common *chan)
 257 {
 258         u8 ver = chan->device->version;
 259
 260         writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
 261 }
 262
 263 static inline void ioat_reset(struct ioat_chan_common *chan)
 264 {
 265         u8 ver = chan->device->version;
 266
 267         writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
 268 }
 269
 270 static inline bool ioat_reset_pending(struct ioat_chan_common *chan)
 271 {
 272         u8 ver = chan->device->version;
 273         u8 cmd;
 274
 275         cmd = readb(chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
 276         return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET;
 277 }
 278
 279 static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr)
 280 {
 281         struct ioat_chan_common *chan = &ioat->base;
 282
 283         writel(addr & 0x00000000FFFFFFFF,
 284                chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
 285         writel(addr >> 32,
 286                chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
 287 }
 288
 289 static inline bool is_ioat_active(unsigned long status)
 290 {
 291         return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
 292 }
 293
 294 static inline bool is_ioat_idle(unsigned long status)
 295 {
 296         return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
 297 }
 298
 299 static inline bool is_ioat_halted(unsigned long status)
 300 {
 301         return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
 302 }
 303
 304 static inline bool is_ioat_suspended(unsigned long status)
 305 {
 306         return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
 307 }
 308
 309 /* channel was fatally programmed */
 310 static inline bool is_ioat_bug(unsigned long err)
 311 {
 312         return !!err;
 313 }
 314
 315 static inline void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len,
 316                               int direction, enum dma_ctrl_flags flags, bool dst)
 317 {
 318         if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) ||
 319             (!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE)))
 320                 pci_unmap_single(pdev, addr, len, direction);
 321         else
 322                 pci_unmap_page(pdev, addr, len, direction);
 323 }
 324
 325 int __devinit ioat_probe(struct ioatdma_device *device);
 326 int __devinit ioat_register(struct ioatdma_device *device);
 327 int __devinit ioat1_dma_probe(struct ioatdma_device *dev, int dca);
 328 int __devinit ioat_dma_self_test(struct ioatdma_device *device);
 329 void __devexit ioat_dma_remove(struct ioatdma_device *device);
 330 struct dca_provider * __devinit ioat_dca_init(struct pci_dev *pdev,
 331                                               void __iomem *iobase);
 332 unsigned long ioat_get_current_completion(struct ioat_chan_common *chan);
 333 void ioat_init_channel(struct ioatdma_device *device,
 334                        struct ioat_chan_common *chan, int idx);
 335 enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
 336                                    struct dma_tx_state *txstate);
 337 void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
 338                     size_t len, struct ioat_dma_descriptor *hw);
 339 bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
 340                            unsigned long *phys_complete);
 341 void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type);
 342 void ioat_kobject_del(struct ioatdma_device *device);
 343 extern const struct sysfs_ops ioat_sysfs_ops;
 344 extern struct ioat_sysfs_entry ioat_version_attr;
 345 extern struct ioat_sysfs_entry ioat_cap_attr;
 346 #endif /* IOATDMA_H */