2 * linux/drivers/char/synclink.c
4 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 Exp $
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
12 * Microgate and SyncLink are trademarks of Microgate Corporation
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
16 * Original release 01/11/99
18 * This code is released under the GNU General Public License (GPL)
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
57 # define BREAKPOINT() asm(" int $3");
59 # define BREAKPOINT() { }
62 #define MAX_ISA_DEVICES 10
63 #define MAX_PCI_DEVICES 10
64 #define MAX_TOTAL_DEVICES 20
66 #include <linux/module.h>
67 #include <linux/errno.h>
68 #include <linux/signal.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/pci.h>
73 #include <linux/tty.h>
74 #include <linux/tty_flip.h>
75 #include <linux/serial.h>
76 #include <linux/major.h>
77 #include <linux/string.h>
78 #include <linux/fcntl.h>
79 #include <linux/ptrace.h>
80 #include <linux/ioport.h>
82 #include <linux/seq_file.h>
83 #include <linux/slab.h>
84 #include <linux/delay.h>
85 #include <linux/netdevice.h>
86 #include <linux/vmalloc.h>
87 #include <linux/init.h>
88 #include <linux/ioctl.h>
89 #include <linux/synclink.h>
91 #include <asm/system.h>
95 #include <linux/bitops.h>
96 #include <asm/types.h>
97 #include <linux/termios.h>
98 #include <linux/workqueue.h>
99 #include <linux/hdlc.h>
100 #include <linux/dma-mapping.h>
102 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && \
103 defined(CONFIG_SYNCLINK_MODULE))
104 #define SYNCLINK_GENERIC_HDLC 1
106 #define SYNCLINK_GENERIC_HDLC 0
109 #define GET_USER(error,value,addr) error = get_user(value,addr)
110 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
111 #define PUT_USER(error,value,addr) error = put_user(value,addr)
112 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
114 #include <asm/uaccess.h>
116 #define RCLRVALUE 0xffff
118 static MGSL_PARAMS default_params
= {
119 MGSL_MODE_HDLC
, /* unsigned long mode */
120 0, /* unsigned char loopback; */
121 HDLC_FLAG_UNDERRUN_ABORT15
, /* unsigned short flags; */
122 HDLC_ENCODING_NRZI_SPACE
, /* unsigned char encoding; */
123 0, /* unsigned long clock_speed; */
124 0xff, /* unsigned char addr_filter; */
125 HDLC_CRC_16_CCITT
, /* unsigned short crc_type; */
126 HDLC_PREAMBLE_LENGTH_8BITS
, /* unsigned char preamble_length; */
127 HDLC_PREAMBLE_PATTERN_NONE
, /* unsigned char preamble; */
128 9600, /* unsigned long data_rate; */
129 8, /* unsigned char data_bits; */
130 1, /* unsigned char stop_bits; */
131 ASYNC_PARITY_NONE
/* unsigned char parity; */
134 #define SHARED_MEM_ADDRESS_SIZE 0x40000
135 #define BUFFERLISTSIZE 4096
136 #define DMABUFFERSIZE 4096
137 #define MAXRXFRAMES 7
139 typedef struct _DMABUFFERENTRY
141 u32 phys_addr
; /* 32-bit flat physical address of data buffer */
142 volatile u16 count
; /* buffer size/data count */
143 volatile u16 status
; /* Control/status field */
144 volatile u16 rcc
; /* character count field */
145 u16 reserved
; /* padding required by 16C32 */
146 u32 link
; /* 32-bit flat link to next buffer entry */
147 char *virt_addr
; /* virtual address of data buffer */
148 u32 phys_entry
; /* physical address of this buffer entry */
150 } DMABUFFERENTRY
, *DMAPBUFFERENTRY
;
152 /* The queue of BH actions to be performed */
155 #define BH_TRANSMIT 2
158 #define IO_PIN_SHUTDOWN_LIMIT 100
160 struct _input_signal_events
{
171 /* transmit holding buffer definitions*/
172 #define MAX_TX_HOLDING_BUFFERS 5
173 struct tx_holding_buffer
{
175 unsigned char * buffer
;
180 * Device instance data structure
185 struct tty_port port
;
189 struct mgsl_icount icount
;
192 int x_char
; /* xon/xoff character */
193 u16 read_status_mask
;
194 u16 ignore_status_mask
;
195 unsigned char *xmit_buf
;
200 wait_queue_head_t status_event_wait_q
;
201 wait_queue_head_t event_wait_q
;
202 struct timer_list tx_timer
; /* HDLC transmit timeout timer */
203 struct mgsl_struct
*next_device
; /* device list link */
205 spinlock_t irq_spinlock
; /* spinlock for synchronizing with ISR */
206 struct work_struct task
; /* task structure for scheduling bh */
208 u32 EventMask
; /* event trigger mask */
209 u32 RecordedEvents
; /* pending events */
211 u32 max_frame_size
; /* as set by device config */
215 bool bh_running
; /* Protection from multiple */
219 int dcd_chkcount
; /* check counts to prevent */
220 int cts_chkcount
; /* too many IRQs if a signal */
221 int dsr_chkcount
; /* is floating */
224 char *buffer_list
; /* virtual address of Rx & Tx buffer lists */
225 u32 buffer_list_phys
;
226 dma_addr_t buffer_list_dma_addr
;
228 unsigned int rx_buffer_count
; /* count of total allocated Rx buffers */
229 DMABUFFERENTRY
*rx_buffer_list
; /* list of receive buffer entries */
230 unsigned int current_rx_buffer
;
232 int num_tx_dma_buffers
; /* number of tx dma frames required */
233 int tx_dma_buffers_used
;
234 unsigned int tx_buffer_count
; /* count of total allocated Tx buffers */
235 DMABUFFERENTRY
*tx_buffer_list
; /* list of transmit buffer entries */
236 int start_tx_dma_buffer
; /* tx dma buffer to start tx dma operation */
237 int current_tx_buffer
; /* next tx dma buffer to be loaded */
239 unsigned char *intermediate_rxbuffer
;
241 int num_tx_holding_buffers
; /* number of tx holding buffer allocated */
242 int get_tx_holding_index
; /* next tx holding buffer for adapter to load */
243 int put_tx_holding_index
; /* next tx holding buffer to store user request */
244 int tx_holding_count
; /* number of tx holding buffers waiting */
245 struct tx_holding_buffer tx_holding_buffers
[MAX_TX_HOLDING_BUFFERS
];
249 bool rx_rcc_underrun
;
258 char device_name
[25]; /* device instance name */
260 unsigned int bus_type
; /* expansion bus type (ISA,EISA,PCI) */
261 unsigned char bus
; /* expansion bus number (zero based) */
262 unsigned char function
; /* PCI device number */
264 unsigned int io_base
; /* base I/O address of adapter */
265 unsigned int io_addr_size
; /* size of the I/O address range */
266 bool io_addr_requested
; /* true if I/O address requested */
268 unsigned int irq_level
; /* interrupt level */
269 unsigned long irq_flags
;
270 bool irq_requested
; /* true if IRQ requested */
272 unsigned int dma_level
; /* DMA channel */
273 bool dma_requested
; /* true if dma channel requested */
279 MGSL_PARAMS params
; /* communications parameters */
281 unsigned char serial_signals
; /* current serial signal states */
283 bool irq_occurred
; /* for diagnostics use */
284 unsigned int init_error
; /* Initialization startup error (DIAGS) */
285 int fDiagnosticsmode
; /* Driver in Diagnostic mode? (DIAGS) */
288 unsigned char* memory_base
; /* shared memory address (PCI only) */
289 u32 phys_memory_base
;
290 bool shared_mem_requested
;
292 unsigned char* lcr_base
; /* local config registers (PCI only) */
295 bool lcr_mem_requested
;
298 char flag_buf
[MAX_ASYNC_BUFFER_SIZE
];
299 char char_buf
[MAX_ASYNC_BUFFER_SIZE
];
300 bool drop_rts_on_tx_done
;
302 bool loopmode_insert_requested
;
303 bool loopmode_send_done_requested
;
305 struct _input_signal_events input_signal_events
;
307 /* generic HDLC device parts */
311 #if SYNCLINK_GENERIC_HDLC
312 struct net_device
*netdev
;
316 #define MGSL_MAGIC 0x5401
319 * The size of the serial xmit buffer is 1 page, or 4096 bytes
321 #ifndef SERIAL_XMIT_SIZE
322 #define SERIAL_XMIT_SIZE 4096
326 * These macros define the offsets used in calculating the
327 * I/O address of the specified USC registers.
331 #define DCPIN 2 /* Bit 1 of I/O address */
332 #define SDPIN 4 /* Bit 2 of I/O address */
334 #define DCAR 0 /* DMA command/address register */
335 #define CCAR SDPIN /* channel command/address register */
336 #define DATAREG DCPIN + SDPIN /* serial data register */
341 * These macros define the register address (ordinal number)
342 * used for writing address/value pairs to the USC.
345 #define CMR 0x02 /* Channel mode Register */
346 #define CCSR 0x04 /* Channel Command/status Register */
347 #define CCR 0x06 /* Channel Control Register */
348 #define PSR 0x08 /* Port status Register */
349 #define PCR 0x0a /* Port Control Register */
350 #define TMDR 0x0c /* Test mode Data Register */
351 #define TMCR 0x0e /* Test mode Control Register */
352 #define CMCR 0x10 /* Clock mode Control Register */
353 #define HCR 0x12 /* Hardware Configuration Register */
354 #define IVR 0x14 /* Interrupt Vector Register */
355 #define IOCR 0x16 /* Input/Output Control Register */
356 #define ICR 0x18 /* Interrupt Control Register */
357 #define DCCR 0x1a /* Daisy Chain Control Register */
358 #define MISR 0x1c /* Misc Interrupt status Register */
359 #define SICR 0x1e /* status Interrupt Control Register */
360 #define RDR 0x20 /* Receive Data Register */
361 #define RMR 0x22 /* Receive mode Register */
362 #define RCSR 0x24 /* Receive Command/status Register */
363 #define RICR 0x26 /* Receive Interrupt Control Register */
364 #define RSR 0x28 /* Receive Sync Register */
365 #define RCLR 0x2a /* Receive count Limit Register */
366 #define RCCR 0x2c /* Receive Character count Register */
367 #define TC0R 0x2e /* Time Constant 0 Register */
368 #define TDR 0x30 /* Transmit Data Register */
369 #define TMR 0x32 /* Transmit mode Register */
370 #define TCSR 0x34 /* Transmit Command/status Register */
371 #define TICR 0x36 /* Transmit Interrupt Control Register */
372 #define TSR 0x38 /* Transmit Sync Register */
373 #define TCLR 0x3a /* Transmit count Limit Register */
374 #define TCCR 0x3c /* Transmit Character count Register */
375 #define TC1R 0x3e /* Time Constant 1 Register */
379 * MACRO DEFINITIONS FOR DMA REGISTERS
382 #define DCR 0x06 /* DMA Control Register (shared) */
383 #define DACR 0x08 /* DMA Array count Register (shared) */
384 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
385 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
386 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
387 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
388 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
390 #define TDMR 0x02 /* Transmit DMA mode Register */
391 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
392 #define TBCR 0x2a /* Transmit Byte count Register */
393 #define TARL 0x2c /* Transmit Address Register (low) */
394 #define TARU 0x2e /* Transmit Address Register (high) */
395 #define NTBCR 0x3a /* Next Transmit Byte count Register */
396 #define NTARL 0x3c /* Next Transmit Address Register (low) */
397 #define NTARU 0x3e /* Next Transmit Address Register (high) */
399 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
400 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
401 #define RBCR 0xaa /* Receive Byte count Register */
402 #define RARL 0xac /* Receive Address Register (low) */
403 #define RARU 0xae /* Receive Address Register (high) */
404 #define NRBCR 0xba /* Next Receive Byte count Register */
405 #define NRARL 0xbc /* Next Receive Address Register (low) */
406 #define NRARU 0xbe /* Next Receive Address Register (high) */
410 * MACRO DEFINITIONS FOR MODEM STATUS BITS
413 #define MODEMSTATUS_DTR 0x80
414 #define MODEMSTATUS_DSR 0x40
415 #define MODEMSTATUS_RTS 0x20
416 #define MODEMSTATUS_CTS 0x10
417 #define MODEMSTATUS_RI 0x04
418 #define MODEMSTATUS_DCD 0x01
422 * Channel Command/Address Register (CCAR) Command Codes
425 #define RTCmd_Null 0x0000
426 #define RTCmd_ResetHighestIus 0x1000
427 #define RTCmd_TriggerChannelLoadDma 0x2000
428 #define RTCmd_TriggerRxDma 0x2800
429 #define RTCmd_TriggerTxDma 0x3000
430 #define RTCmd_TriggerRxAndTxDma 0x3800
431 #define RTCmd_PurgeRxFifo 0x4800
432 #define RTCmd_PurgeTxFifo 0x5000
433 #define RTCmd_PurgeRxAndTxFifo 0x5800
434 #define RTCmd_LoadRcc 0x6800
435 #define RTCmd_LoadTcc 0x7000
436 #define RTCmd_LoadRccAndTcc 0x7800
437 #define RTCmd_LoadTC0 0x8800
438 #define RTCmd_LoadTC1 0x9000
439 #define RTCmd_LoadTC0AndTC1 0x9800
440 #define RTCmd_SerialDataLSBFirst 0xa000
441 #define RTCmd_SerialDataMSBFirst 0xa800
442 #define RTCmd_SelectBigEndian 0xb000
443 #define RTCmd_SelectLittleEndian 0xb800
447 * DMA Command/Address Register (DCAR) Command Codes
450 #define DmaCmd_Null 0x0000
451 #define DmaCmd_ResetTxChannel 0x1000
452 #define DmaCmd_ResetRxChannel 0x1200
453 #define DmaCmd_StartTxChannel 0x2000
454 #define DmaCmd_StartRxChannel 0x2200
455 #define DmaCmd_ContinueTxChannel 0x3000
456 #define DmaCmd_ContinueRxChannel 0x3200
457 #define DmaCmd_PauseTxChannel 0x4000
458 #define DmaCmd_PauseRxChannel 0x4200
459 #define DmaCmd_AbortTxChannel 0x5000
460 #define DmaCmd_AbortRxChannel 0x5200
461 #define DmaCmd_InitTxChannel 0x7000
462 #define DmaCmd_InitRxChannel 0x7200
463 #define DmaCmd_ResetHighestDmaIus 0x8000
464 #define DmaCmd_ResetAllChannels 0x9000
465 #define DmaCmd_StartAllChannels 0xa000
466 #define DmaCmd_ContinueAllChannels 0xb000
467 #define DmaCmd_PauseAllChannels 0xc000
468 #define DmaCmd_AbortAllChannels 0xd000
469 #define DmaCmd_InitAllChannels 0xf000
471 #define TCmd_Null 0x0000
472 #define TCmd_ClearTxCRC 0x2000
473 #define TCmd_SelectTicrTtsaData 0x4000
474 #define TCmd_SelectTicrTxFifostatus 0x5000
475 #define TCmd_SelectTicrIntLevel 0x6000
476 #define TCmd_SelectTicrdma_level 0x7000
477 #define TCmd_SendFrame 0x8000
478 #define TCmd_SendAbort 0x9000
479 #define TCmd_EnableDleInsertion 0xc000
480 #define TCmd_DisableDleInsertion 0xd000
481 #define TCmd_ClearEofEom 0xe000
482 #define TCmd_SetEofEom 0xf000
484 #define RCmd_Null 0x0000
485 #define RCmd_ClearRxCRC 0x2000
486 #define RCmd_EnterHuntmode 0x3000
487 #define RCmd_SelectRicrRtsaData 0x4000
488 #define RCmd_SelectRicrRxFifostatus 0x5000
489 #define RCmd_SelectRicrIntLevel 0x6000
490 #define RCmd_SelectRicrdma_level 0x7000
493 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
496 #define RECEIVE_STATUS BIT5
497 #define RECEIVE_DATA BIT4
498 #define TRANSMIT_STATUS BIT3
499 #define TRANSMIT_DATA BIT2
505 * Receive status Bits in Receive Command/status Register RCSR
508 #define RXSTATUS_SHORT_FRAME BIT8
509 #define RXSTATUS_CODE_VIOLATION BIT8
510 #define RXSTATUS_EXITED_HUNT BIT7
511 #define RXSTATUS_IDLE_RECEIVED BIT6
512 #define RXSTATUS_BREAK_RECEIVED BIT5
513 #define RXSTATUS_ABORT_RECEIVED BIT5
514 #define RXSTATUS_RXBOUND BIT4
515 #define RXSTATUS_CRC_ERROR BIT3
516 #define RXSTATUS_FRAMING_ERROR BIT3
517 #define RXSTATUS_ABORT BIT2
518 #define RXSTATUS_PARITY_ERROR BIT2
519 #define RXSTATUS_OVERRUN BIT1
520 #define RXSTATUS_DATA_AVAILABLE BIT0
521 #define RXSTATUS_ALL 0x01f6
522 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
525 * Values for setting transmit idle mode in
526 * Transmit Control/status Register (TCSR)
528 #define IDLEMODE_FLAGS 0x0000
529 #define IDLEMODE_ALT_ONE_ZERO 0x0100
530 #define IDLEMODE_ZERO 0x0200
531 #define IDLEMODE_ONE 0x0300
532 #define IDLEMODE_ALT_MARK_SPACE 0x0500
533 #define IDLEMODE_SPACE 0x0600
534 #define IDLEMODE_MARK 0x0700
535 #define IDLEMODE_MASK 0x0700
538 * IUSC revision identifiers
540 #define IUSC_SL1660 0x4d44
541 #define IUSC_PRE_SL1660 0x4553
544 * Transmit status Bits in Transmit Command/status Register (TCSR)
547 #define TCSR_PRESERVE 0x0F00
549 #define TCSR_UNDERWAIT BIT11
550 #define TXSTATUS_PREAMBLE_SENT BIT7
551 #define TXSTATUS_IDLE_SENT BIT6
552 #define TXSTATUS_ABORT_SENT BIT5
553 #define TXSTATUS_EOF_SENT BIT4
554 #define TXSTATUS_EOM_SENT BIT4
555 #define TXSTATUS_CRC_SENT BIT3
556 #define TXSTATUS_ALL_SENT BIT2
557 #define TXSTATUS_UNDERRUN BIT1
558 #define TXSTATUS_FIFO_EMPTY BIT0
559 #define TXSTATUS_ALL 0x00fa
560 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
563 #define MISCSTATUS_RXC_LATCHED BIT15
564 #define MISCSTATUS_RXC BIT14
565 #define MISCSTATUS_TXC_LATCHED BIT13
566 #define MISCSTATUS_TXC BIT12
567 #define MISCSTATUS_RI_LATCHED BIT11
568 #define MISCSTATUS_RI BIT10
569 #define MISCSTATUS_DSR_LATCHED BIT9
570 #define MISCSTATUS_DSR BIT8
571 #define MISCSTATUS_DCD_LATCHED BIT7
572 #define MISCSTATUS_DCD BIT6
573 #define MISCSTATUS_CTS_LATCHED BIT5
574 #define MISCSTATUS_CTS BIT4
575 #define MISCSTATUS_RCC_UNDERRUN BIT3
576 #define MISCSTATUS_DPLL_NO_SYNC BIT2
577 #define MISCSTATUS_BRG1_ZERO BIT1
578 #define MISCSTATUS_BRG0_ZERO BIT0
580 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
581 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
583 #define SICR_RXC_ACTIVE BIT15
584 #define SICR_RXC_INACTIVE BIT14
585 #define SICR_RXC (BIT15+BIT14)
586 #define SICR_TXC_ACTIVE BIT13
587 #define SICR_TXC_INACTIVE BIT12
588 #define SICR_TXC (BIT13+BIT12)
589 #define SICR_RI_ACTIVE BIT11
590 #define SICR_RI_INACTIVE BIT10
591 #define SICR_RI (BIT11+BIT10)
592 #define SICR_DSR_ACTIVE BIT9
593 #define SICR_DSR_INACTIVE BIT8
594 #define SICR_DSR (BIT9+BIT8)
595 #define SICR_DCD_ACTIVE BIT7
596 #define SICR_DCD_INACTIVE BIT6
597 #define SICR_DCD (BIT7+BIT6)
598 #define SICR_CTS_ACTIVE BIT5
599 #define SICR_CTS_INACTIVE BIT4
600 #define SICR_CTS (BIT5+BIT4)
601 #define SICR_RCC_UNDERFLOW BIT3
602 #define SICR_DPLL_NO_SYNC BIT2
603 #define SICR_BRG1_ZERO BIT1
604 #define SICR_BRG0_ZERO BIT0
606 void usc_DisableMasterIrqBit( struct mgsl_struct
*info
);
607 void usc_EnableMasterIrqBit( struct mgsl_struct
*info
);
608 void usc_EnableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
609 void usc_DisableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
610 void usc_ClearIrqPendingBits( struct mgsl_struct
*info
, u16 IrqMask
);
612 #define usc_EnableInterrupts( a, b ) \
613 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
615 #define usc_DisableInterrupts( a, b ) \
616 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
618 #define usc_EnableMasterIrqBit(a) \
619 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
621 #define usc_DisableMasterIrqBit(a) \
622 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
624 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
627 * Transmit status Bits in Transmit Control status Register (TCSR)
628 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
631 #define TXSTATUS_PREAMBLE_SENT BIT7
632 #define TXSTATUS_IDLE_SENT BIT6
633 #define TXSTATUS_ABORT_SENT BIT5
634 #define TXSTATUS_EOF BIT4
635 #define TXSTATUS_CRC_SENT BIT3
636 #define TXSTATUS_ALL_SENT BIT2
637 #define TXSTATUS_UNDERRUN BIT1
638 #define TXSTATUS_FIFO_EMPTY BIT0
640 #define DICR_MASTER BIT15
641 #define DICR_TRANSMIT BIT0
642 #define DICR_RECEIVE BIT1
644 #define usc_EnableDmaInterrupts(a,b) \
645 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
647 #define usc_DisableDmaInterrupts(a,b) \
648 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
650 #define usc_EnableStatusIrqs(a,b) \
651 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
653 #define usc_DisablestatusIrqs(a,b) \
654 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
656 /* Transmit status Bits in Transmit Control status Register (TCSR) */
657 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
660 #define DISABLE_UNCONDITIONAL 0
661 #define DISABLE_END_OF_FRAME 1
662 #define ENABLE_UNCONDITIONAL 2
663 #define ENABLE_AUTO_CTS 3
664 #define ENABLE_AUTO_DCD 3
665 #define usc_EnableTransmitter(a,b) \
666 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
667 #define usc_EnableReceiver(a,b) \
668 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
670 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 Port
);
671 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
672 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
);
674 static u16
usc_InReg( struct mgsl_struct
*info
, u16 Port
);
675 static void usc_OutReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
676 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
);
677 void usc_RCmd( struct mgsl_struct
*info
, u16 Cmd
);
678 void usc_TCmd( struct mgsl_struct
*info
, u16 Cmd
);
680 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
681 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
683 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
685 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
);
686 static void usc_start_receiver( struct mgsl_struct
*info
);
687 static void usc_stop_receiver( struct mgsl_struct
*info
);
689 static void usc_start_transmitter( struct mgsl_struct
*info
);
690 static void usc_stop_transmitter( struct mgsl_struct
*info
);
691 static void usc_set_txidle( struct mgsl_struct
*info
);
692 static void usc_load_txfifo( struct mgsl_struct
*info
);
694 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 DataRate
);
695 static void usc_enable_loopback( struct mgsl_struct
*info
, int enable
);
697 static void usc_get_serial_signals( struct mgsl_struct
*info
);
698 static void usc_set_serial_signals( struct mgsl_struct
*info
);
700 static void usc_reset( struct mgsl_struct
*info
);
702 static void usc_set_sync_mode( struct mgsl_struct
*info
);
703 static void usc_set_sdlc_mode( struct mgsl_struct
*info
);
704 static void usc_set_async_mode( struct mgsl_struct
*info
);
705 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 DataRate
);
707 static void usc_loopback_frame( struct mgsl_struct
*info
);
709 static void mgsl_tx_timeout(unsigned long context
);
712 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
);
713 static void usc_loopmode_insert_request( struct mgsl_struct
* info
);
714 static int usc_loopmode_active( struct mgsl_struct
* info
);
715 static void usc_loopmode_send_done( struct mgsl_struct
* info
);
717 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
);
719 #if SYNCLINK_GENERIC_HDLC
720 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
721 static void hdlcdev_tx_done(struct mgsl_struct
*info
);
722 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
);
723 static int hdlcdev_init(struct mgsl_struct
*info
);
724 static void hdlcdev_exit(struct mgsl_struct
*info
);
728 * Defines a BUS descriptor value for the PCI adapter
729 * local bus address ranges.
732 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
743 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
);
746 * Adapter diagnostic routines
748 static bool mgsl_register_test( struct mgsl_struct
*info
);
749 static bool mgsl_irq_test( struct mgsl_struct
*info
);
750 static bool mgsl_dma_test( struct mgsl_struct
*info
);
751 static bool mgsl_memory_test( struct mgsl_struct
*info
);
752 static int mgsl_adapter_test( struct mgsl_struct
*info
);
755 * device and resource management routines
757 static int mgsl_claim_resources(struct mgsl_struct
*info
);
758 static void mgsl_release_resources(struct mgsl_struct
*info
);
759 static void mgsl_add_device(struct mgsl_struct
*info
);
760 static struct mgsl_struct
* mgsl_allocate_device(void);
763 * DMA buffer manupulation functions.
765 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
);
766 static bool mgsl_get_rx_frame( struct mgsl_struct
*info
);
767 static bool mgsl_get_raw_rx_frame( struct mgsl_struct
*info
);
768 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
);
769 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
);
770 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
);
771 static void mgsl_load_tx_dma_buffer( struct mgsl_struct
*info
, const char *Buffer
, unsigned int BufferSize
);
772 static void mgsl_load_pci_memory(char* TargetPtr
, const char* SourcePtr
, unsigned short count
);
775 * DMA and Shared Memory buffer allocation and formatting
777 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
);
778 static void mgsl_free_dma_buffers(struct mgsl_struct
*info
);
779 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
780 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
781 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct
*info
);
782 static void mgsl_free_buffer_list_memory(struct mgsl_struct
*info
);
783 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
784 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
785 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
786 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
787 static bool load_next_tx_holding_buffer(struct mgsl_struct
*info
);
788 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
);
791 * Bottom half interrupt handlers
793 static void mgsl_bh_handler(struct work_struct
*work
);
794 static void mgsl_bh_receive(struct mgsl_struct
*info
);
795 static void mgsl_bh_transmit(struct mgsl_struct
*info
);
796 static void mgsl_bh_status(struct mgsl_struct
*info
);
799 * Interrupt handler routines and dispatch table.
801 static void mgsl_isr_null( struct mgsl_struct
*info
);
802 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
);
803 static void mgsl_isr_receive_data( struct mgsl_struct
*info
);
804 static void mgsl_isr_receive_status( struct mgsl_struct
*info
);
805 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
);
806 static void mgsl_isr_io_pin( struct mgsl_struct
*info
);
807 static void mgsl_isr_misc( struct mgsl_struct
*info
);
808 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
);
809 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
);
811 typedef void (*isr_dispatch_func
)(struct mgsl_struct
*);
813 static isr_dispatch_func UscIsrTable
[7] =
818 mgsl_isr_transmit_data
,
819 mgsl_isr_transmit_status
,
820 mgsl_isr_receive_data
,
821 mgsl_isr_receive_status
825 * ioctl call handlers
827 static int tiocmget(struct tty_struct
*tty
, struct file
*file
);
828 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
829 unsigned int set
, unsigned int clear
);
830 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount
831 __user
*user_icount
);
832 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
);
833 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
);
834 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
);
835 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
);
836 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
);
837 static int mgsl_txabort(struct mgsl_struct
* info
);
838 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
);
839 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
*mask
);
840 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
);
842 /* set non-zero on successful registration with PCI subsystem */
843 static bool pci_registered
;
846 * Global linked list of SyncLink devices
848 static struct mgsl_struct
*mgsl_device_list
;
849 static int mgsl_device_count
;
852 * Set this param to non-zero to load eax with the
853 * .text section address and breakpoint on module load.
854 * This is useful for use with gdb and add-symbol-file command.
856 static int break_on_load
;
859 * Driver major number, defaults to zero to get auto
860 * assigned major number. May be forced as module parameter.
865 * Array of user specified options for ISA adapters.
867 static int io
[MAX_ISA_DEVICES
];
868 static int irq
[MAX_ISA_DEVICES
];
869 static int dma
[MAX_ISA_DEVICES
];
870 static int debug_level
;
871 static int maxframe
[MAX_TOTAL_DEVICES
];
872 static int txdmabufs
[MAX_TOTAL_DEVICES
];
873 static int txholdbufs
[MAX_TOTAL_DEVICES
];
875 module_param(break_on_load
, bool, 0);
876 module_param(ttymajor
, int, 0);
877 module_param_array(io
, int, NULL
, 0);
878 module_param_array(irq
, int, NULL
, 0);
879 module_param_array(dma
, int, NULL
, 0);
880 module_param(debug_level
, int, 0);
881 module_param_array(maxframe
, int, NULL
, 0);
882 module_param_array(txdmabufs
, int, NULL
, 0);
883 module_param_array(txholdbufs
, int, NULL
, 0);
885 static char *driver_name
= "SyncLink serial driver";
886 static char *driver_version
= "$Revision: 4.38 $";
888 static int synclink_init_one (struct pci_dev
*dev
,
889 const struct pci_device_id
*ent
);
890 static void synclink_remove_one (struct pci_dev
*dev
);
892 static struct pci_device_id synclink_pci_tbl
[] = {
893 { PCI_VENDOR_ID_MICROGATE
, PCI_DEVICE_ID_MICROGATE_USC
, PCI_ANY_ID
, PCI_ANY_ID
, },
894 { PCI_VENDOR_ID_MICROGATE
, 0x0210, PCI_ANY_ID
, PCI_ANY_ID
, },
895 { 0, }, /* terminate list */
897 MODULE_DEVICE_TABLE(pci
, synclink_pci_tbl
);
899 MODULE_LICENSE("GPL");
901 static struct pci_driver synclink_pci_driver
= {
903 .id_table
= synclink_pci_tbl
,
904 .probe
= synclink_init_one
,
905 .remove
= __devexit_p(synclink_remove_one
),
908 static struct tty_driver
*serial_driver
;
910 /* number of characters left in xmit buffer before we ask for more */
911 #define WAKEUP_CHARS 256
914 static void mgsl_change_params(struct mgsl_struct
*info
);
915 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
);
918 * 1st function defined in .text section. Calling this function in
919 * init_module() followed by a breakpoint allows a remote debugger
920 * (gdb) to get the .text address for the add-symbol-file command.
921 * This allows remote debugging of dynamically loadable modules.
923 static void* mgsl_get_text_ptr(void)
925 return mgsl_get_text_ptr
;
928 static inline int mgsl_paranoia_check(struct mgsl_struct
*info
,
929 char *name
, const char *routine
)
931 #ifdef MGSL_PARANOIA_CHECK
932 static const char *badmagic
=
933 "Warning: bad magic number for mgsl struct (%s) in %s\n";
934 static const char *badinfo
=
935 "Warning: null mgsl_struct for (%s) in %s\n";
938 printk(badinfo
, name
, routine
);
941 if (info
->magic
!= MGSL_MAGIC
) {
942 printk(badmagic
, name
, routine
);
953 * line discipline callback wrappers
955 * The wrappers maintain line discipline references
956 * while calling into the line discipline.
958 * ldisc_receive_buf - pass receive data to line discipline
961 static void ldisc_receive_buf(struct tty_struct
*tty
,
962 const __u8
*data
, char *flags
, int count
)
964 struct tty_ldisc
*ld
;
967 ld
= tty_ldisc_ref(tty
);
969 if (ld
->ops
->receive_buf
)
970 ld
->ops
->receive_buf(tty
, data
, flags
, count
);
975 /* mgsl_stop() throttle (stop) transmitter
977 * Arguments: tty pointer to tty info structure
980 static void mgsl_stop(struct tty_struct
*tty
)
982 struct mgsl_struct
*info
= tty
->driver_data
;
985 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_stop"))
988 if ( debug_level
>= DEBUG_LEVEL_INFO
)
989 printk("mgsl_stop(%s)\n",info
->device_name
);
991 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
992 if (info
->tx_enabled
)
993 usc_stop_transmitter(info
);
994 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
996 } /* end of mgsl_stop() */
998 /* mgsl_start() release (start) transmitter
1000 * Arguments: tty pointer to tty info structure
1001 * Return Value: None
1003 static void mgsl_start(struct tty_struct
*tty
)
1005 struct mgsl_struct
*info
= tty
->driver_data
;
1006 unsigned long flags
;
1008 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_start"))
1011 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1012 printk("mgsl_start(%s)\n",info
->device_name
);
1014 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1015 if (!info
->tx_enabled
)
1016 usc_start_transmitter(info
);
1017 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1019 } /* end of mgsl_start() */
1022 * Bottom half work queue access functions
1025 /* mgsl_bh_action() Return next bottom half action to perform.
1026 * Return Value: BH action code or 0 if nothing to do.
1028 static int mgsl_bh_action(struct mgsl_struct
*info
)
1030 unsigned long flags
;
1033 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1035 if (info
->pending_bh
& BH_RECEIVE
) {
1036 info
->pending_bh
&= ~BH_RECEIVE
;
1038 } else if (info
->pending_bh
& BH_TRANSMIT
) {
1039 info
->pending_bh
&= ~BH_TRANSMIT
;
1041 } else if (info
->pending_bh
& BH_STATUS
) {
1042 info
->pending_bh
&= ~BH_STATUS
;
1047 /* Mark BH routine as complete */
1048 info
->bh_running
= false;
1049 info
->bh_requested
= false;
1052 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1058 * Perform bottom half processing of work items queued by ISR.
1060 static void mgsl_bh_handler(struct work_struct
*work
)
1062 struct mgsl_struct
*info
=
1063 container_of(work
, struct mgsl_struct
, task
);
1069 if ( debug_level
>= DEBUG_LEVEL_BH
)
1070 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1071 __FILE__
,__LINE__
,info
->device_name
);
1073 info
->bh_running
= true;
1075 while((action
= mgsl_bh_action(info
)) != 0) {
1077 /* Process work item */
1078 if ( debug_level
>= DEBUG_LEVEL_BH
)
1079 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1080 __FILE__
,__LINE__
,action
);
1085 mgsl_bh_receive(info
);
1088 mgsl_bh_transmit(info
);
1091 mgsl_bh_status(info
);
1094 /* unknown work item ID */
1095 printk("Unknown work item ID=%08X!\n", action
);
1100 if ( debug_level
>= DEBUG_LEVEL_BH
)
1101 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1102 __FILE__
,__LINE__
,info
->device_name
);
1105 static void mgsl_bh_receive(struct mgsl_struct
*info
)
1107 bool (*get_rx_frame
)(struct mgsl_struct
*info
) =
1108 (info
->params
.mode
== MGSL_MODE_HDLC
? mgsl_get_rx_frame
: mgsl_get_raw_rx_frame
);
1110 if ( debug_level
>= DEBUG_LEVEL_BH
)
1111 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1112 __FILE__
,__LINE__
,info
->device_name
);
1116 if (info
->rx_rcc_underrun
) {
1117 unsigned long flags
;
1118 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1119 usc_start_receiver(info
);
1120 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1123 } while(get_rx_frame(info
));
1126 static void mgsl_bh_transmit(struct mgsl_struct
*info
)
1128 struct tty_struct
*tty
= info
->port
.tty
;
1129 unsigned long flags
;
1131 if ( debug_level
>= DEBUG_LEVEL_BH
)
1132 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1133 __FILE__
,__LINE__
,info
->device_name
);
1138 /* if transmitter idle and loopmode_send_done_requested
1139 * then start echoing RxD to TxD
1141 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1142 if ( !info
->tx_active
&& info
->loopmode_send_done_requested
)
1143 usc_loopmode_send_done( info
);
1144 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1147 static void mgsl_bh_status(struct mgsl_struct
*info
)
1149 if ( debug_level
>= DEBUG_LEVEL_BH
)
1150 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1151 __FILE__
,__LINE__
,info
->device_name
);
1153 info
->ri_chkcount
= 0;
1154 info
->dsr_chkcount
= 0;
1155 info
->dcd_chkcount
= 0;
1156 info
->cts_chkcount
= 0;
1159 /* mgsl_isr_receive_status()
1161 * Service a receive status interrupt. The type of status
1162 * interrupt is indicated by the state of the RCSR.
1163 * This is only used for HDLC mode.
1165 * Arguments: info pointer to device instance data
1166 * Return Value: None
1168 static void mgsl_isr_receive_status( struct mgsl_struct
*info
)
1170 u16 status
= usc_InReg( info
, RCSR
);
1172 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1173 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1174 __FILE__
,__LINE__
,status
);
1176 if ( (status
& RXSTATUS_ABORT_RECEIVED
) &&
1177 info
->loopmode_insert_requested
&&
1178 usc_loopmode_active(info
) )
1180 ++info
->icount
.rxabort
;
1181 info
->loopmode_insert_requested
= false;
1183 /* clear CMR:13 to start echoing RxD to TxD */
1184 info
->cmr_value
&= ~BIT13
;
1185 usc_OutReg(info
, CMR
, info
->cmr_value
);
1187 /* disable received abort irq (no longer required) */
1188 usc_OutReg(info
, RICR
,
1189 (usc_InReg(info
, RICR
) & ~RXSTATUS_ABORT_RECEIVED
));
1192 if (status
& (RXSTATUS_EXITED_HUNT
+ RXSTATUS_IDLE_RECEIVED
)) {
1193 if (status
& RXSTATUS_EXITED_HUNT
)
1194 info
->icount
.exithunt
++;
1195 if (status
& RXSTATUS_IDLE_RECEIVED
)
1196 info
->icount
.rxidle
++;
1197 wake_up_interruptible(&info
->event_wait_q
);
1200 if (status
& RXSTATUS_OVERRUN
){
1201 info
->icount
.rxover
++;
1202 usc_process_rxoverrun_sync( info
);
1205 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
1206 usc_UnlatchRxstatusBits( info
, status
);
1208 } /* end of mgsl_isr_receive_status() */
1210 /* mgsl_isr_transmit_status()
1212 * Service a transmit status interrupt
1213 * HDLC mode :end of transmit frame
1214 * Async mode:all data is sent
1215 * transmit status is indicated by bits in the TCSR.
1217 * Arguments: info pointer to device instance data
1218 * Return Value: None
1220 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
)
1222 u16 status
= usc_InReg( info
, TCSR
);
1224 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1225 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1226 __FILE__
,__LINE__
,status
);
1228 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
1229 usc_UnlatchTxstatusBits( info
, status
);
1231 if ( status
& (TXSTATUS_UNDERRUN
| TXSTATUS_ABORT_SENT
) )
1233 /* finished sending HDLC abort. This may leave */
1234 /* the TxFifo with data from the aborted frame */
1235 /* so purge the TxFifo. Also shutdown the DMA */
1236 /* channel in case there is data remaining in */
1237 /* the DMA buffer */
1238 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
1239 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
1242 if ( status
& TXSTATUS_EOF_SENT
)
1243 info
->icount
.txok
++;
1244 else if ( status
& TXSTATUS_UNDERRUN
)
1245 info
->icount
.txunder
++;
1246 else if ( status
& TXSTATUS_ABORT_SENT
)
1247 info
->icount
.txabort
++;
1249 info
->icount
.txunder
++;
1251 info
->tx_active
= false;
1252 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1253 del_timer(&info
->tx_timer
);
1255 if ( info
->drop_rts_on_tx_done
) {
1256 usc_get_serial_signals( info
);
1257 if ( info
->serial_signals
& SerialSignal_RTS
) {
1258 info
->serial_signals
&= ~SerialSignal_RTS
;
1259 usc_set_serial_signals( info
);
1261 info
->drop_rts_on_tx_done
= false;
1264 #if SYNCLINK_GENERIC_HDLC
1266 hdlcdev_tx_done(info
);
1270 if (info
->port
.tty
->stopped
|| info
->port
.tty
->hw_stopped
) {
1271 usc_stop_transmitter(info
);
1274 info
->pending_bh
|= BH_TRANSMIT
;
1277 } /* end of mgsl_isr_transmit_status() */
1279 /* mgsl_isr_io_pin()
1281 * Service an Input/Output pin interrupt. The type of
1282 * interrupt is indicated by bits in the MISR
1284 * Arguments: info pointer to device instance data
1285 * Return Value: None
1287 static void mgsl_isr_io_pin( struct mgsl_struct
*info
)
1289 struct mgsl_icount
*icount
;
1290 u16 status
= usc_InReg( info
, MISR
);
1292 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1293 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1294 __FILE__
,__LINE__
,status
);
1296 usc_ClearIrqPendingBits( info
, IO_PIN
);
1297 usc_UnlatchIostatusBits( info
, status
);
1299 if (status
& (MISCSTATUS_CTS_LATCHED
| MISCSTATUS_DCD_LATCHED
|
1300 MISCSTATUS_DSR_LATCHED
| MISCSTATUS_RI_LATCHED
) ) {
1301 icount
= &info
->icount
;
1302 /* update input line counters */
1303 if (status
& MISCSTATUS_RI_LATCHED
) {
1304 if ((info
->ri_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1305 usc_DisablestatusIrqs(info
,SICR_RI
);
1307 if ( status
& MISCSTATUS_RI
)
1308 info
->input_signal_events
.ri_up
++;
1310 info
->input_signal_events
.ri_down
++;
1312 if (status
& MISCSTATUS_DSR_LATCHED
) {
1313 if ((info
->dsr_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1314 usc_DisablestatusIrqs(info
,SICR_DSR
);
1316 if ( status
& MISCSTATUS_DSR
)
1317 info
->input_signal_events
.dsr_up
++;
1319 info
->input_signal_events
.dsr_down
++;
1321 if (status
& MISCSTATUS_DCD_LATCHED
) {
1322 if ((info
->dcd_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1323 usc_DisablestatusIrqs(info
,SICR_DCD
);
1325 if (status
& MISCSTATUS_DCD
) {
1326 info
->input_signal_events
.dcd_up
++;
1328 info
->input_signal_events
.dcd_down
++;
1329 #if SYNCLINK_GENERIC_HDLC
1330 if (info
->netcount
) {
1331 if (status
& MISCSTATUS_DCD
)
1332 netif_carrier_on(info
->netdev
);
1334 netif_carrier_off(info
->netdev
);
1338 if (status
& MISCSTATUS_CTS_LATCHED
)
1340 if ((info
->cts_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1341 usc_DisablestatusIrqs(info
,SICR_CTS
);
1343 if ( status
& MISCSTATUS_CTS
)
1344 info
->input_signal_events
.cts_up
++;
1346 info
->input_signal_events
.cts_down
++;
1348 wake_up_interruptible(&info
->status_event_wait_q
);
1349 wake_up_interruptible(&info
->event_wait_q
);
1351 if ( (info
->port
.flags
& ASYNC_CHECK_CD
) &&
1352 (status
& MISCSTATUS_DCD_LATCHED
) ) {
1353 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1354 printk("%s CD now %s...", info
->device_name
,
1355 (status
& MISCSTATUS_DCD
) ? "on" : "off");
1356 if (status
& MISCSTATUS_DCD
)
1357 wake_up_interruptible(&info
->port
.open_wait
);
1359 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1360 printk("doing serial hangup...");
1362 tty_hangup(info
->port
.tty
);
1366 if ( (info
->port
.flags
& ASYNC_CTS_FLOW
) &&
1367 (status
& MISCSTATUS_CTS_LATCHED
) ) {
1368 if (info
->port
.tty
->hw_stopped
) {
1369 if (status
& MISCSTATUS_CTS
) {
1370 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1371 printk("CTS tx start...");
1373 info
->port
.tty
->hw_stopped
= 0;
1374 usc_start_transmitter(info
);
1375 info
->pending_bh
|= BH_TRANSMIT
;
1379 if (!(status
& MISCSTATUS_CTS
)) {
1380 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1381 printk("CTS tx stop...");
1383 info
->port
.tty
->hw_stopped
= 1;
1384 usc_stop_transmitter(info
);
1390 info
->pending_bh
|= BH_STATUS
;
1392 /* for diagnostics set IRQ flag */
1393 if ( status
& MISCSTATUS_TXC_LATCHED
){
1394 usc_OutReg( info
, SICR
,
1395 (unsigned short)(usc_InReg(info
,SICR
) & ~(SICR_TXC_ACTIVE
+SICR_TXC_INACTIVE
)) );
1396 usc_UnlatchIostatusBits( info
, MISCSTATUS_TXC_LATCHED
);
1397 info
->irq_occurred
= true;
1400 } /* end of mgsl_isr_io_pin() */
1402 /* mgsl_isr_transmit_data()
1404 * Service a transmit data interrupt (async mode only).
1406 * Arguments: info pointer to device instance data
1407 * Return Value: None
1409 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
)
1411 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1412 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1413 __FILE__
,__LINE__
,info
->xmit_cnt
);
1415 usc_ClearIrqPendingBits( info
, TRANSMIT_DATA
);
1417 if (info
->port
.tty
->stopped
|| info
->port
.tty
->hw_stopped
) {
1418 usc_stop_transmitter(info
);
1422 if ( info
->xmit_cnt
)
1423 usc_load_txfifo( info
);
1425 info
->tx_active
= false;
1427 if (info
->xmit_cnt
< WAKEUP_CHARS
)
1428 info
->pending_bh
|= BH_TRANSMIT
;
1430 } /* end of mgsl_isr_transmit_data() */
1432 /* mgsl_isr_receive_data()
1434 * Service a receive data interrupt. This occurs
1435 * when operating in asynchronous interrupt transfer mode.
1436 * The receive data FIFO is flushed to the receive data buffers.
1438 * Arguments: info pointer to device instance data
1439 * Return Value: None
1441 static void mgsl_isr_receive_data( struct mgsl_struct
*info
)
1446 unsigned char DataByte
;
1447 struct tty_struct
*tty
= info
->port
.tty
;
1448 struct mgsl_icount
*icount
= &info
->icount
;
1450 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1451 printk("%s(%d):mgsl_isr_receive_data\n",
1454 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
);
1456 /* select FIFO status for RICR readback */
1457 usc_RCmd( info
, RCmd_SelectRicrRxFifostatus
);
1459 /* clear the Wordstatus bit so that status readback */
1460 /* only reflects the status of this byte */
1461 usc_OutReg( info
, RICR
+LSBONLY
, (u16
)(usc_InReg(info
, RICR
+LSBONLY
) & ~BIT3
));
1463 /* flush the receive FIFO */
1465 while( (Fifocount
= (usc_InReg(info
,RICR
) >> 8)) ) {
1468 /* read one byte from RxFIFO */
1469 outw( (inw(info
->io_base
+ CCAR
) & 0x0780) | (RDR
+LSBONLY
),
1470 info
->io_base
+ CCAR
);
1471 DataByte
= inb( info
->io_base
+ CCAR
);
1473 /* get the status of the received byte */
1474 status
= usc_InReg(info
, RCSR
);
1475 if ( status
& (RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
+
1476 RXSTATUS_OVERRUN
+ RXSTATUS_BREAK_RECEIVED
) )
1477 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
1482 if ( status
& (RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
+
1483 RXSTATUS_OVERRUN
+ RXSTATUS_BREAK_RECEIVED
) ) {
1484 printk("rxerr=%04X\n",status
);
1485 /* update error statistics */
1486 if ( status
& RXSTATUS_BREAK_RECEIVED
) {
1487 status
&= ~(RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
);
1489 } else if (status
& RXSTATUS_PARITY_ERROR
)
1491 else if (status
& RXSTATUS_FRAMING_ERROR
)
1493 else if (status
& RXSTATUS_OVERRUN
) {
1494 /* must issue purge fifo cmd before */
1495 /* 16C32 accepts more receive chars */
1496 usc_RTCmd(info
,RTCmd_PurgeRxFifo
);
1500 /* discard char if tty control flags say so */
1501 if (status
& info
->ignore_status_mask
)
1504 status
&= info
->read_status_mask
;
1506 if (status
& RXSTATUS_BREAK_RECEIVED
) {
1508 if (info
->port
.flags
& ASYNC_SAK
)
1510 } else if (status
& RXSTATUS_PARITY_ERROR
)
1512 else if (status
& RXSTATUS_FRAMING_ERROR
)
1514 } /* end of if (error) */
1515 tty_insert_flip_char(tty
, DataByte
, flag
);
1516 if (status
& RXSTATUS_OVERRUN
) {
1517 /* Overrun is special, since it's
1518 * reported immediately, and doesn't
1519 * affect the current character
1521 work
+= tty_insert_flip_char(tty
, 0, TTY_OVERRUN
);
1525 if ( debug_level
>= DEBUG_LEVEL_ISR
) {
1526 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1527 __FILE__
,__LINE__
,icount
->rx
,icount
->brk
,
1528 icount
->parity
,icount
->frame
,icount
->overrun
);
1532 tty_flip_buffer_push(tty
);
1537 * Service a miscellaneous interrupt source.
1539 * Arguments: info pointer to device extension (instance data)
1540 * Return Value: None
1542 static void mgsl_isr_misc( struct mgsl_struct
*info
)
1544 u16 status
= usc_InReg( info
, MISR
);
1546 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1547 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1548 __FILE__
,__LINE__
,status
);
1550 if ((status
& MISCSTATUS_RCC_UNDERRUN
) &&
1551 (info
->params
.mode
== MGSL_MODE_HDLC
)) {
1553 /* turn off receiver and rx DMA */
1554 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
1555 usc_DmaCmd(info
, DmaCmd_ResetRxChannel
);
1556 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
1557 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
1558 usc_DisableInterrupts(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
1560 /* schedule BH handler to restart receiver */
1561 info
->pending_bh
|= BH_RECEIVE
;
1562 info
->rx_rcc_underrun
= true;
1565 usc_ClearIrqPendingBits( info
, MISC
);
1566 usc_UnlatchMiscstatusBits( info
, status
);
1568 } /* end of mgsl_isr_misc() */
1572 * Services undefined interrupt vectors from the
1573 * USC. (hence this function SHOULD never be called)
1575 * Arguments: info pointer to device extension (instance data)
1576 * Return Value: None
1578 static void mgsl_isr_null( struct mgsl_struct
*info
)
1581 } /* end of mgsl_isr_null() */
1583 /* mgsl_isr_receive_dma()
1585 * Service a receive DMA channel interrupt.
1586 * For this driver there are two sources of receive DMA interrupts
1587 * as identified in the Receive DMA mode Register (RDMR):
1589 * BIT3 EOA/EOL End of List, all receive buffers in receive
1590 * buffer list have been filled (no more free buffers
1591 * available). The DMA controller has shut down.
1593 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1594 * DMA buffer is terminated in response to completion
1595 * of a good frame or a frame with errors. The status
1596 * of the frame is stored in the buffer entry in the
1597 * list of receive buffer entries.
1599 * Arguments: info pointer to device instance data
1600 * Return Value: None
1602 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
)
1606 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1607 usc_OutDmaReg( info
, CDIR
, BIT9
+BIT1
);
1609 /* Read the receive DMA status to identify interrupt type. */
1610 /* This also clears the status bits. */
1611 status
= usc_InDmaReg( info
, RDMR
);
1613 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1614 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1615 __FILE__
,__LINE__
,info
->device_name
,status
);
1617 info
->pending_bh
|= BH_RECEIVE
;
1619 if ( status
& BIT3
) {
1620 info
->rx_overflow
= true;
1621 info
->icount
.buf_overrun
++;
1624 } /* end of mgsl_isr_receive_dma() */
1626 /* mgsl_isr_transmit_dma()
1628 * This function services a transmit DMA channel interrupt.
1630 * For this driver there is one source of transmit DMA interrupts
1631 * as identified in the Transmit DMA Mode Register (TDMR):
1633 * BIT2 EOB End of Buffer. This interrupt occurs when a
1634 * transmit DMA buffer has been emptied.
1636 * The driver maintains enough transmit DMA buffers to hold at least
1637 * one max frame size transmit frame. When operating in a buffered
1638 * transmit mode, there may be enough transmit DMA buffers to hold at
1639 * least two or more max frame size frames. On an EOB condition,
1640 * determine if there are any queued transmit buffers and copy into
1641 * transmit DMA buffers if we have room.
1643 * Arguments: info pointer to device instance data
1644 * Return Value: None
1646 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
)
1650 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1651 usc_OutDmaReg(info
, CDIR
, BIT8
+BIT0
);
1653 /* Read the transmit DMA status to identify interrupt type. */
1654 /* This also clears the status bits. */
1656 status
= usc_InDmaReg( info
, TDMR
);
1658 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1659 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1660 __FILE__
,__LINE__
,info
->device_name
,status
);
1662 if ( status
& BIT2
) {
1663 --info
->tx_dma_buffers_used
;
1665 /* if there are transmit frames queued,
1666 * try to load the next one
1668 if ( load_next_tx_holding_buffer(info
) ) {
1669 /* if call returns non-zero value, we have
1670 * at least one free tx holding buffer
1672 info
->pending_bh
|= BH_TRANSMIT
;
1676 } /* end of mgsl_isr_transmit_dma() */
1680 * Interrupt service routine entry point.
1684 * irq interrupt number that caused interrupt
1685 * dev_id device ID supplied during interrupt registration
1687 * Return Value: None
1689 static irqreturn_t
mgsl_interrupt(int dummy
, void *dev_id
)
1691 struct mgsl_struct
*info
= dev_id
;
1695 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1696 printk(KERN_DEBUG
"%s(%d):mgsl_interrupt(%d)entry.\n",
1697 __FILE__
, __LINE__
, info
->irq_level
);
1699 spin_lock(&info
->irq_spinlock
);
1702 /* Read the interrupt vectors from hardware. */
1703 UscVector
= usc_InReg(info
, IVR
) >> 9;
1704 DmaVector
= usc_InDmaReg(info
, DIVR
);
1706 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1707 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1708 __FILE__
,__LINE__
,info
->device_name
,UscVector
,DmaVector
);
1710 if ( !UscVector
&& !DmaVector
)
1713 /* Dispatch interrupt vector */
1715 (*UscIsrTable
[UscVector
])(info
);
1716 else if ( (DmaVector
&(BIT10
|BIT9
)) == BIT10
)
1717 mgsl_isr_transmit_dma(info
);
1719 mgsl_isr_receive_dma(info
);
1721 if ( info
->isr_overflow
) {
1722 printk(KERN_ERR
"%s(%d):%s isr overflow irq=%d\n",
1723 __FILE__
, __LINE__
, info
->device_name
, info
->irq_level
);
1724 usc_DisableMasterIrqBit(info
);
1725 usc_DisableDmaInterrupts(info
,DICR_MASTER
);
1730 /* Request bottom half processing if there's something
1731 * for it to do and the bh is not already running
1734 if ( info
->pending_bh
&& !info
->bh_running
&& !info
->bh_requested
) {
1735 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1736 printk("%s(%d):%s queueing bh task.\n",
1737 __FILE__
,__LINE__
,info
->device_name
);
1738 schedule_work(&info
->task
);
1739 info
->bh_requested
= true;
1742 spin_unlock(&info
->irq_spinlock
);
1744 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1745 printk(KERN_DEBUG
"%s(%d):mgsl_interrupt(%d)exit.\n",
1746 __FILE__
, __LINE__
, info
->irq_level
);
1749 } /* end of mgsl_interrupt() */
1753 * Initialize and start device.
1755 * Arguments: info pointer to device instance data
1756 * Return Value: 0 if success, otherwise error code
1758 static int startup(struct mgsl_struct
* info
)
1762 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1763 printk("%s(%d):mgsl_startup(%s)\n",__FILE__
,__LINE__
,info
->device_name
);
1765 if (info
->port
.flags
& ASYNC_INITIALIZED
)
1768 if (!info
->xmit_buf
) {
1769 /* allocate a page of memory for a transmit buffer */
1770 info
->xmit_buf
= (unsigned char *)get_zeroed_page(GFP_KERNEL
);
1771 if (!info
->xmit_buf
) {
1772 printk(KERN_ERR
"%s(%d):%s can't allocate transmit buffer\n",
1773 __FILE__
,__LINE__
,info
->device_name
);
1778 info
->pending_bh
= 0;
1780 memset(&info
->icount
, 0, sizeof(info
->icount
));
1782 setup_timer(&info
->tx_timer
, mgsl_tx_timeout
, (unsigned long)info
);
1784 /* Allocate and claim adapter resources */
1785 retval
= mgsl_claim_resources(info
);
1787 /* perform existence check and diagnostics */
1789 retval
= mgsl_adapter_test(info
);
1792 if (capable(CAP_SYS_ADMIN
) && info
->port
.tty
)
1793 set_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
1794 mgsl_release_resources(info
);
1798 /* program hardware for current parameters */
1799 mgsl_change_params(info
);
1802 clear_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
1804 info
->port
.flags
|= ASYNC_INITIALIZED
;
1808 } /* end of startup() */
1812 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1814 * Arguments: info pointer to device instance data
1815 * Return Value: None
1817 static void shutdown(struct mgsl_struct
* info
)
1819 unsigned long flags
;
1821 if (!(info
->port
.flags
& ASYNC_INITIALIZED
))
1824 if (debug_level
>= DEBUG_LEVEL_INFO
)
1825 printk("%s(%d):mgsl_shutdown(%s)\n",
1826 __FILE__
,__LINE__
, info
->device_name
);
1828 /* clear status wait queue because status changes */
1829 /* can't happen after shutting down the hardware */
1830 wake_up_interruptible(&info
->status_event_wait_q
);
1831 wake_up_interruptible(&info
->event_wait_q
);
1833 del_timer_sync(&info
->tx_timer
);
1835 if (info
->xmit_buf
) {
1836 free_page((unsigned long) info
->xmit_buf
);
1837 info
->xmit_buf
= NULL
;
1840 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1841 usc_DisableMasterIrqBit(info
);
1842 usc_stop_receiver(info
);
1843 usc_stop_transmitter(info
);
1844 usc_DisableInterrupts(info
,RECEIVE_DATA
+ RECEIVE_STATUS
+
1845 TRANSMIT_DATA
+ TRANSMIT_STATUS
+ IO_PIN
+ MISC
);
1846 usc_DisableDmaInterrupts(info
,DICR_MASTER
+ DICR_TRANSMIT
+ DICR_RECEIVE
);
1848 /* Disable DMAEN (Port 7, Bit 14) */
1849 /* This disconnects the DMA request signal from the ISA bus */
1850 /* on the ISA adapter. This has no effect for the PCI adapter */
1851 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) | BIT14
));
1853 /* Disable INTEN (Port 6, Bit12) */
1854 /* This disconnects the IRQ request signal to the ISA bus */
1855 /* on the ISA adapter. This has no effect for the PCI adapter */
1856 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) | BIT12
));
1858 if (!info
->port
.tty
|| info
->port
.tty
->termios
->c_cflag
& HUPCL
) {
1859 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
1860 usc_set_serial_signals(info
);
1863 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1865 mgsl_release_resources(info
);
1868 set_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
1870 info
->port
.flags
&= ~ASYNC_INITIALIZED
;
1872 } /* end of shutdown() */
1874 static void mgsl_program_hw(struct mgsl_struct
*info
)
1876 unsigned long flags
;
1878 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1880 usc_stop_receiver(info
);
1881 usc_stop_transmitter(info
);
1882 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1884 if (info
->params
.mode
== MGSL_MODE_HDLC
||
1885 info
->params
.mode
== MGSL_MODE_RAW
||
1887 usc_set_sync_mode(info
);
1889 usc_set_async_mode(info
);
1891 usc_set_serial_signals(info
);
1893 info
->dcd_chkcount
= 0;
1894 info
->cts_chkcount
= 0;
1895 info
->ri_chkcount
= 0;
1896 info
->dsr_chkcount
= 0;
1898 usc_EnableStatusIrqs(info
,SICR_CTS
+SICR_DSR
+SICR_DCD
+SICR_RI
);
1899 usc_EnableInterrupts(info
, IO_PIN
);
1900 usc_get_serial_signals(info
);
1902 if (info
->netcount
|| info
->port
.tty
->termios
->c_cflag
& CREAD
)
1903 usc_start_receiver(info
);
1905 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1908 /* Reconfigure adapter based on new parameters
1910 static void mgsl_change_params(struct mgsl_struct
*info
)
1915 if (!info
->port
.tty
|| !info
->port
.tty
->termios
)
1918 if (debug_level
>= DEBUG_LEVEL_INFO
)
1919 printk("%s(%d):mgsl_change_params(%s)\n",
1920 __FILE__
,__LINE__
, info
->device_name
);
1922 cflag
= info
->port
.tty
->termios
->c_cflag
;
1924 /* if B0 rate (hangup) specified then negate DTR and RTS */
1925 /* otherwise assert DTR and RTS */
1927 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
1929 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
1931 /* byte size and parity */
1933 switch (cflag
& CSIZE
) {
1934 case CS5
: info
->params
.data_bits
= 5; break;
1935 case CS6
: info
->params
.data_bits
= 6; break;
1936 case CS7
: info
->params
.data_bits
= 7; break;
1937 case CS8
: info
->params
.data_bits
= 8; break;
1938 /* Never happens, but GCC is too dumb to figure it out */
1939 default: info
->params
.data_bits
= 7; break;
1943 info
->params
.stop_bits
= 2;
1945 info
->params
.stop_bits
= 1;
1947 info
->params
.parity
= ASYNC_PARITY_NONE
;
1948 if (cflag
& PARENB
) {
1950 info
->params
.parity
= ASYNC_PARITY_ODD
;
1952 info
->params
.parity
= ASYNC_PARITY_EVEN
;
1955 info
->params
.parity
= ASYNC_PARITY_SPACE
;
1959 /* calculate number of jiffies to transmit a full
1960 * FIFO (32 bytes) at specified data rate
1962 bits_per_char
= info
->params
.data_bits
+
1963 info
->params
.stop_bits
+ 1;
1965 /* if port data rate is set to 460800 or less then
1966 * allow tty settings to override, otherwise keep the
1967 * current data rate.
1969 if (info
->params
.data_rate
<= 460800)
1970 info
->params
.data_rate
= tty_get_baud_rate(info
->port
.tty
);
1972 if ( info
->params
.data_rate
) {
1973 info
->timeout
= (32*HZ
*bits_per_char
) /
1974 info
->params
.data_rate
;
1976 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
1978 if (cflag
& CRTSCTS
)
1979 info
->port
.flags
|= ASYNC_CTS_FLOW
;
1981 info
->port
.flags
&= ~ASYNC_CTS_FLOW
;
1984 info
->port
.flags
&= ~ASYNC_CHECK_CD
;
1986 info
->port
.flags
|= ASYNC_CHECK_CD
;
1988 /* process tty input control flags */
1990 info
->read_status_mask
= RXSTATUS_OVERRUN
;
1991 if (I_INPCK(info
->port
.tty
))
1992 info
->read_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
1993 if (I_BRKINT(info
->port
.tty
) || I_PARMRK(info
->port
.tty
))
1994 info
->read_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
1996 if (I_IGNPAR(info
->port
.tty
))
1997 info
->ignore_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
1998 if (I_IGNBRK(info
->port
.tty
)) {
1999 info
->ignore_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
2000 /* If ignoring parity and break indicators, ignore
2001 * overruns too. (For real raw support).
2003 if (I_IGNPAR(info
->port
.tty
))
2004 info
->ignore_status_mask
|= RXSTATUS_OVERRUN
;
2007 mgsl_program_hw(info
);
2009 } /* end of mgsl_change_params() */
2013 * Add a character to the transmit buffer.
2015 * Arguments: tty pointer to tty information structure
2016 * ch character to add to transmit buffer
2018 * Return Value: None
2020 static int mgsl_put_char(struct tty_struct
*tty
, unsigned char ch
)
2022 struct mgsl_struct
*info
= tty
->driver_data
;
2023 unsigned long flags
;
2026 if (debug_level
>= DEBUG_LEVEL_INFO
) {
2027 printk(KERN_DEBUG
"%s(%d):mgsl_put_char(%d) on %s\n",
2028 __FILE__
, __LINE__
, ch
, info
->device_name
);
2031 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_put_char"))
2034 if (!info
->xmit_buf
)
2037 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
2039 if ((info
->params
.mode
== MGSL_MODE_ASYNC
) || !info
->tx_active
) {
2040 if (info
->xmit_cnt
< SERIAL_XMIT_SIZE
- 1) {
2041 info
->xmit_buf
[info
->xmit_head
++] = ch
;
2042 info
->xmit_head
&= SERIAL_XMIT_SIZE
-1;
2047 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
2050 } /* end of mgsl_put_char() */
2052 /* mgsl_flush_chars()
2054 * Enable transmitter so remaining characters in the
2055 * transmit buffer are sent.
2057 * Arguments: tty pointer to tty information structure
2058 * Return Value: None
2060 static void mgsl_flush_chars(struct tty_struct
*tty
)
2062 struct mgsl_struct
*info
= tty
->driver_data
;
2063 unsigned long flags
;
2065 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2066 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2067 __FILE__
,__LINE__
,info
->device_name
,info
->xmit_cnt
);
2069 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_chars"))
2072 if (info
->xmit_cnt
<= 0 || tty
->stopped
|| tty
->hw_stopped
||
2076 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2077 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2078 __FILE__
,__LINE__
,info
->device_name
);
2080 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2082 if (!info
->tx_active
) {
2083 if ( (info
->params
.mode
== MGSL_MODE_HDLC
||
2084 info
->params
.mode
== MGSL_MODE_RAW
) && info
->xmit_cnt
) {
2085 /* operating in synchronous (frame oriented) mode */
2086 /* copy data from circular xmit_buf to */
2087 /* transmit DMA buffer. */
2088 mgsl_load_tx_dma_buffer(info
,
2089 info
->xmit_buf
,info
->xmit_cnt
);
2091 usc_start_transmitter(info
);
2094 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2096 } /* end of mgsl_flush_chars() */
2100 * Send a block of data
2104 * tty pointer to tty information structure
2105 * buf pointer to buffer containing send data
2106 * count size of send data in bytes
2108 * Return Value: number of characters written
2110 static int mgsl_write(struct tty_struct
* tty
,
2111 const unsigned char *buf
, int count
)
2114 struct mgsl_struct
*info
= tty
->driver_data
;
2115 unsigned long flags
;
2117 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2118 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2119 __FILE__
,__LINE__
,info
->device_name
,count
);
2121 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write"))
2124 if (!info
->xmit_buf
)
2127 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2128 info
->params
.mode
== MGSL_MODE_RAW
) {
2129 /* operating in synchronous (frame oriented) mode */
2130 /* operating in synchronous (frame oriented) mode */
2131 if (info
->tx_active
) {
2133 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
2137 /* transmitter is actively sending data -
2138 * if we have multiple transmit dma and
2139 * holding buffers, attempt to queue this
2140 * frame for transmission at a later time.
2142 if (info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
2143 /* no tx holding buffers available */
2148 /* queue transmit frame request */
2150 save_tx_buffer_request(info
,buf
,count
);
2152 /* if we have sufficient tx dma buffers,
2153 * load the next buffered tx request
2155 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2156 load_next_tx_holding_buffer(info
);
2157 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2161 /* if operating in HDLC LoopMode and the adapter */
2162 /* has yet to be inserted into the loop, we can't */
2165 if ( (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) &&
2166 !usc_loopmode_active(info
) )
2172 if ( info
->xmit_cnt
) {
2173 /* Send accumulated from send_char() calls */
2174 /* as frame and wait before accepting more data. */
2177 /* copy data from circular xmit_buf to */
2178 /* transmit DMA buffer. */
2179 mgsl_load_tx_dma_buffer(info
,
2180 info
->xmit_buf
,info
->xmit_cnt
);
2181 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2182 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2183 __FILE__
,__LINE__
,info
->device_name
);
2185 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2186 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2187 __FILE__
,__LINE__
,info
->device_name
);
2189 info
->xmit_cnt
= count
;
2190 mgsl_load_tx_dma_buffer(info
,buf
,count
);
2194 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2195 c
= min_t(int, count
,
2196 min(SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1,
2197 SERIAL_XMIT_SIZE
- info
->xmit_head
));
2199 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2202 memcpy(info
->xmit_buf
+ info
->xmit_head
, buf
, c
);
2203 info
->xmit_head
= ((info
->xmit_head
+ c
) &
2204 (SERIAL_XMIT_SIZE
-1));
2205 info
->xmit_cnt
+= c
;
2206 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2213 if (info
->xmit_cnt
&& !tty
->stopped
&& !tty
->hw_stopped
) {
2214 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2215 if (!info
->tx_active
)
2216 usc_start_transmitter(info
);
2217 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2220 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2221 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2222 __FILE__
,__LINE__
,info
->device_name
,ret
);
2226 } /* end of mgsl_write() */
2228 /* mgsl_write_room()
2230 * Return the count of free bytes in transmit buffer
2232 * Arguments: tty pointer to tty info structure
2233 * Return Value: None
2235 static int mgsl_write_room(struct tty_struct
*tty
)
2237 struct mgsl_struct
*info
= tty
->driver_data
;
2240 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write_room"))
2242 ret
= SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1;
2246 if (debug_level
>= DEBUG_LEVEL_INFO
)
2247 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2248 __FILE__
,__LINE__
, info
->device_name
,ret
);
2250 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2251 info
->params
.mode
== MGSL_MODE_RAW
) {
2252 /* operating in synchronous (frame oriented) mode */
2253 if ( info
->tx_active
)
2256 return HDLC_MAX_FRAME_SIZE
;
2261 } /* end of mgsl_write_room() */
2263 /* mgsl_chars_in_buffer()
2265 * Return the count of bytes in transmit buffer
2267 * Arguments: tty pointer to tty info structure
2268 * Return Value: None
2270 static int mgsl_chars_in_buffer(struct tty_struct
*tty
)
2272 struct mgsl_struct
*info
= tty
->driver_data
;
2274 if (debug_level
>= DEBUG_LEVEL_INFO
)
2275 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2276 __FILE__
,__LINE__
, info
->device_name
);
2278 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_chars_in_buffer"))
2281 if (debug_level
>= DEBUG_LEVEL_INFO
)
2282 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2283 __FILE__
,__LINE__
, info
->device_name
,info
->xmit_cnt
);
2285 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2286 info
->params
.mode
== MGSL_MODE_RAW
) {
2287 /* operating in synchronous (frame oriented) mode */
2288 if ( info
->tx_active
)
2289 return info
->max_frame_size
;
2294 return info
->xmit_cnt
;
2295 } /* end of mgsl_chars_in_buffer() */
2297 /* mgsl_flush_buffer()
2299 * Discard all data in the send buffer
2301 * Arguments: tty pointer to tty info structure
2302 * Return Value: None
2304 static void mgsl_flush_buffer(struct tty_struct
*tty
)
2306 struct mgsl_struct
*info
= tty
->driver_data
;
2307 unsigned long flags
;
2309 if (debug_level
>= DEBUG_LEVEL_INFO
)
2310 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2311 __FILE__
,__LINE__
, info
->device_name
);
2313 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_buffer"))
2316 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2317 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
2318 del_timer(&info
->tx_timer
);
2319 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2324 /* mgsl_send_xchar()
2326 * Send a high-priority XON/XOFF character
2328 * Arguments: tty pointer to tty info structure
2329 * ch character to send
2330 * Return Value: None
2332 static void mgsl_send_xchar(struct tty_struct
*tty
, char ch
)
2334 struct mgsl_struct
*info
= tty
->driver_data
;
2335 unsigned long flags
;
2337 if (debug_level
>= DEBUG_LEVEL_INFO
)
2338 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2339 __FILE__
,__LINE__
, info
->device_name
, ch
);
2341 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_send_xchar"))
2346 /* Make sure transmit interrupts are on */
2347 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2348 if (!info
->tx_enabled
)
2349 usc_start_transmitter(info
);
2350 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2352 } /* end of mgsl_send_xchar() */
2356 * Signal remote device to throttle send data (our receive data)
2358 * Arguments: tty pointer to tty info structure
2359 * Return Value: None
2361 static void mgsl_throttle(struct tty_struct
* tty
)
2363 struct mgsl_struct
*info
= tty
->driver_data
;
2364 unsigned long flags
;
2366 if (debug_level
>= DEBUG_LEVEL_INFO
)
2367 printk("%s(%d):mgsl_throttle(%s) entry\n",
2368 __FILE__
,__LINE__
, info
->device_name
);
2370 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_throttle"))
2374 mgsl_send_xchar(tty
, STOP_CHAR(tty
));
2376 if (tty
->termios
->c_cflag
& CRTSCTS
) {
2377 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2378 info
->serial_signals
&= ~SerialSignal_RTS
;
2379 usc_set_serial_signals(info
);
2380 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2382 } /* end of mgsl_throttle() */
2384 /* mgsl_unthrottle()
2386 * Signal remote device to stop throttling send data (our receive data)
2388 * Arguments: tty pointer to tty info structure
2389 * Return Value: None
2391 static void mgsl_unthrottle(struct tty_struct
* tty
)
2393 struct mgsl_struct
*info
= tty
->driver_data
;
2394 unsigned long flags
;
2396 if (debug_level
>= DEBUG_LEVEL_INFO
)
2397 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2398 __FILE__
,__LINE__
, info
->device_name
);
2400 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_unthrottle"))
2407 mgsl_send_xchar(tty
, START_CHAR(tty
));
2410 if (tty
->termios
->c_cflag
& CRTSCTS
) {
2411 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2412 info
->serial_signals
|= SerialSignal_RTS
;
2413 usc_set_serial_signals(info
);
2414 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2417 } /* end of mgsl_unthrottle() */
2421 * get the current serial parameters information
2423 * Arguments: info pointer to device instance data
2424 * user_icount pointer to buffer to hold returned stats
2426 * Return Value: 0 if success, otherwise error code
2428 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount __user
*user_icount
)
2432 if (debug_level
>= DEBUG_LEVEL_INFO
)
2433 printk("%s(%d):mgsl_get_params(%s)\n",
2434 __FILE__
,__LINE__
, info
->device_name
);
2437 memset(&info
->icount
, 0, sizeof(info
->icount
));
2439 mutex_lock(&info
->port
.mutex
);
2440 COPY_TO_USER(err
, user_icount
, &info
->icount
, sizeof(struct mgsl_icount
));
2441 mutex_unlock(&info
->port
.mutex
);
2448 } /* end of mgsl_get_stats() */
2450 /* mgsl_get_params()
2452 * get the current serial parameters information
2454 * Arguments: info pointer to device instance data
2455 * user_params pointer to buffer to hold returned params
2457 * Return Value: 0 if success, otherwise error code
2459 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
)
2462 if (debug_level
>= DEBUG_LEVEL_INFO
)
2463 printk("%s(%d):mgsl_get_params(%s)\n",
2464 __FILE__
,__LINE__
, info
->device_name
);
2466 mutex_lock(&info
->port
.mutex
);
2467 COPY_TO_USER(err
,user_params
, &info
->params
, sizeof(MGSL_PARAMS
));
2468 mutex_unlock(&info
->port
.mutex
);
2470 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2471 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2472 __FILE__
,__LINE__
,info
->device_name
);
2478 } /* end of mgsl_get_params() */
2480 /* mgsl_set_params()
2482 * set the serial parameters
2486 * info pointer to device instance data
2487 * new_params user buffer containing new serial params
2489 * Return Value: 0 if success, otherwise error code
2491 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
)
2493 unsigned long flags
;
2494 MGSL_PARAMS tmp_params
;
2497 if (debug_level
>= DEBUG_LEVEL_INFO
)
2498 printk("%s(%d):mgsl_set_params %s\n", __FILE__
,__LINE__
,
2499 info
->device_name
);
2500 COPY_FROM_USER(err
,&tmp_params
, new_params
, sizeof(MGSL_PARAMS
));
2502 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2503 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2504 __FILE__
,__LINE__
,info
->device_name
);
2508 mutex_lock(&info
->port
.mutex
);
2509 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2510 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
2511 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2513 mgsl_change_params(info
);
2514 mutex_unlock(&info
->port
.mutex
);
2518 } /* end of mgsl_set_params() */
2520 /* mgsl_get_txidle()
2522 * get the current transmit idle mode
2524 * Arguments: info pointer to device instance data
2525 * idle_mode pointer to buffer to hold returned idle mode
2527 * Return Value: 0 if success, otherwise error code
2529 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
)
2533 if (debug_level
>= DEBUG_LEVEL_INFO
)
2534 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2535 __FILE__
,__LINE__
, info
->device_name
, info
->idle_mode
);
2537 COPY_TO_USER(err
,idle_mode
, &info
->idle_mode
, sizeof(int));
2539 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2540 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2541 __FILE__
,__LINE__
,info
->device_name
);
2547 } /* end of mgsl_get_txidle() */
2549 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2551 * Arguments: info pointer to device instance data
2552 * idle_mode new idle mode
2554 * Return Value: 0 if success, otherwise error code
2556 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
)
2558 unsigned long flags
;
2560 if (debug_level
>= DEBUG_LEVEL_INFO
)
2561 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__
,__LINE__
,
2562 info
->device_name
, idle_mode
);
2564 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2565 info
->idle_mode
= idle_mode
;
2566 usc_set_txidle( info
);
2567 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2570 } /* end of mgsl_set_txidle() */
2574 * enable or disable the transmitter
2578 * info pointer to device instance data
2579 * enable 1 = enable, 0 = disable
2581 * Return Value: 0 if success, otherwise error code
2583 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
)
2585 unsigned long flags
;
2587 if (debug_level
>= DEBUG_LEVEL_INFO
)
2588 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__
,__LINE__
,
2589 info
->device_name
, enable
);
2591 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2593 if ( !info
->tx_enabled
) {
2595 usc_start_transmitter(info
);
2596 /*--------------------------------------------------
2597 * if HDLC/SDLC Loop mode, attempt to insert the
2598 * station in the 'loop' by setting CMR:13. Upon
2599 * receipt of the next GoAhead (RxAbort) sequence,
2600 * the OnLoop indicator (CCSR:7) should go active
2601 * to indicate that we are on the loop
2602 *--------------------------------------------------*/
2603 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2604 usc_loopmode_insert_request( info
);
2607 if ( info
->tx_enabled
)
2608 usc_stop_transmitter(info
);
2610 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2613 } /* end of mgsl_txenable() */
2615 /* mgsl_txabort() abort send HDLC frame
2617 * Arguments: info pointer to device instance data
2618 * Return Value: 0 if success, otherwise error code
2620 static int mgsl_txabort(struct mgsl_struct
* info
)
2622 unsigned long flags
;
2624 if (debug_level
>= DEBUG_LEVEL_INFO
)
2625 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__
,__LINE__
,
2628 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2629 if ( info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
)
2631 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2632 usc_loopmode_cancel_transmit( info
);
2634 usc_TCmd(info
,TCmd_SendAbort
);
2636 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2639 } /* end of mgsl_txabort() */
2641 /* mgsl_rxenable() enable or disable the receiver
2643 * Arguments: info pointer to device instance data
2644 * enable 1 = enable, 0 = disable
2645 * Return Value: 0 if success, otherwise error code
2647 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
)
2649 unsigned long flags
;
2651 if (debug_level
>= DEBUG_LEVEL_INFO
)
2652 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__
,__LINE__
,
2653 info
->device_name
, enable
);
2655 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2657 if ( !info
->rx_enabled
)
2658 usc_start_receiver(info
);
2660 if ( info
->rx_enabled
)
2661 usc_stop_receiver(info
);
2663 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2666 } /* end of mgsl_rxenable() */
2668 /* mgsl_wait_event() wait for specified event to occur
2670 * Arguments: info pointer to device instance data
2671 * mask pointer to bitmask of events to wait for
2672 * Return Value: 0 if successful and bit mask updated with
2673 * of events triggerred,
2674 * otherwise error code
2676 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
* mask_ptr
)
2678 unsigned long flags
;
2681 struct mgsl_icount cprev
, cnow
;
2684 struct _input_signal_events oldsigs
, newsigs
;
2685 DECLARE_WAITQUEUE(wait
, current
);
2687 COPY_FROM_USER(rc
,&mask
, mask_ptr
, sizeof(int));
2692 if (debug_level
>= DEBUG_LEVEL_INFO
)
2693 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__
,__LINE__
,
2694 info
->device_name
, mask
);
2696 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2698 /* return immediately if state matches requested events */
2699 usc_get_serial_signals(info
);
2700 s
= info
->serial_signals
;
2702 ( ((s
& SerialSignal_DSR
) ? MgslEvent_DsrActive
:MgslEvent_DsrInactive
) +
2703 ((s
& SerialSignal_DCD
) ? MgslEvent_DcdActive
:MgslEvent_DcdInactive
) +
2704 ((s
& SerialSignal_CTS
) ? MgslEvent_CtsActive
:MgslEvent_CtsInactive
) +
2705 ((s
& SerialSignal_RI
) ? MgslEvent_RiActive
:MgslEvent_RiInactive
) );
2707 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2711 /* save current irq counts */
2712 cprev
= info
->icount
;
2713 oldsigs
= info
->input_signal_events
;
2715 /* enable hunt and idle irqs if needed */
2716 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2717 u16 oldreg
= usc_InReg(info
,RICR
);
2718 u16 newreg
= oldreg
+
2719 (mask
& MgslEvent_ExitHuntMode
? RXSTATUS_EXITED_HUNT
:0) +
2720 (mask
& MgslEvent_IdleReceived
? RXSTATUS_IDLE_RECEIVED
:0);
2721 if (oldreg
!= newreg
)
2722 usc_OutReg(info
, RICR
, newreg
);
2725 set_current_state(TASK_INTERRUPTIBLE
);
2726 add_wait_queue(&info
->event_wait_q
, &wait
);
2728 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2733 if (signal_pending(current
)) {
2738 /* get current irq counts */
2739 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2740 cnow
= info
->icount
;
2741 newsigs
= info
->input_signal_events
;
2742 set_current_state(TASK_INTERRUPTIBLE
);
2743 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2745 /* if no change, wait aborted for some reason */
2746 if (newsigs
.dsr_up
== oldsigs
.dsr_up
&&
2747 newsigs
.dsr_down
== oldsigs
.dsr_down
&&
2748 newsigs
.dcd_up
== oldsigs
.dcd_up
&&
2749 newsigs
.dcd_down
== oldsigs
.dcd_down
&&
2750 newsigs
.cts_up
== oldsigs
.cts_up
&&
2751 newsigs
.cts_down
== oldsigs
.cts_down
&&
2752 newsigs
.ri_up
== oldsigs
.ri_up
&&
2753 newsigs
.ri_down
== oldsigs
.ri_down
&&
2754 cnow
.exithunt
== cprev
.exithunt
&&
2755 cnow
.rxidle
== cprev
.rxidle
) {
2761 ( (newsigs
.dsr_up
!= oldsigs
.dsr_up
? MgslEvent_DsrActive
:0) +
2762 (newsigs
.dsr_down
!= oldsigs
.dsr_down
? MgslEvent_DsrInactive
:0) +
2763 (newsigs
.dcd_up
!= oldsigs
.dcd_up
? MgslEvent_DcdActive
:0) +
2764 (newsigs
.dcd_down
!= oldsigs
.dcd_down
? MgslEvent_DcdInactive
:0) +
2765 (newsigs
.cts_up
!= oldsigs
.cts_up
? MgslEvent_CtsActive
:0) +
2766 (newsigs
.cts_down
!= oldsigs
.cts_down
? MgslEvent_CtsInactive
:0) +
2767 (newsigs
.ri_up
!= oldsigs
.ri_up
? MgslEvent_RiActive
:0) +
2768 (newsigs
.ri_down
!= oldsigs
.ri_down
? MgslEvent_RiInactive
:0) +
2769 (cnow
.exithunt
!= cprev
.exithunt
? MgslEvent_ExitHuntMode
:0) +
2770 (cnow
.rxidle
!= cprev
.rxidle
? MgslEvent_IdleReceived
:0) );
2778 remove_wait_queue(&info
->event_wait_q
, &wait
);
2779 set_current_state(TASK_RUNNING
);
2781 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2782 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2783 if (!waitqueue_active(&info
->event_wait_q
)) {
2784 /* disable enable exit hunt mode/idle rcvd IRQs */
2785 usc_OutReg(info
, RICR
, usc_InReg(info
,RICR
) &
2786 ~(RXSTATUS_EXITED_HUNT
+ RXSTATUS_IDLE_RECEIVED
));
2788 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2792 PUT_USER(rc
, events
, mask_ptr
);
2796 } /* end of mgsl_wait_event() */
2798 static int modem_input_wait(struct mgsl_struct
*info
,int arg
)
2800 unsigned long flags
;
2802 struct mgsl_icount cprev
, cnow
;
2803 DECLARE_WAITQUEUE(wait
, current
);
2805 /* save current irq counts */
2806 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2807 cprev
= info
->icount
;
2808 add_wait_queue(&info
->status_event_wait_q
, &wait
);
2809 set_current_state(TASK_INTERRUPTIBLE
);
2810 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2814 if (signal_pending(current
)) {
2819 /* get new irq counts */
2820 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2821 cnow
= info
->icount
;
2822 set_current_state(TASK_INTERRUPTIBLE
);
2823 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2825 /* if no change, wait aborted for some reason */
2826 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
2827 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
) {
2832 /* check for change in caller specified modem input */
2833 if ((arg
& TIOCM_RNG
&& cnow
.rng
!= cprev
.rng
) ||
2834 (arg
& TIOCM_DSR
&& cnow
.dsr
!= cprev
.dsr
) ||
2835 (arg
& TIOCM_CD
&& cnow
.dcd
!= cprev
.dcd
) ||
2836 (arg
& TIOCM_CTS
&& cnow
.cts
!= cprev
.cts
)) {
2843 remove_wait_queue(&info
->status_event_wait_q
, &wait
);
2844 set_current_state(TASK_RUNNING
);
2848 /* return the state of the serial control and status signals
2850 static int tiocmget(struct tty_struct
*tty
, struct file
*file
)
2852 struct mgsl_struct
*info
= tty
->driver_data
;
2853 unsigned int result
;
2854 unsigned long flags
;
2856 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2857 usc_get_serial_signals(info
);
2858 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2860 result
= ((info
->serial_signals
& SerialSignal_RTS
) ? TIOCM_RTS
:0) +
2861 ((info
->serial_signals
& SerialSignal_DTR
) ? TIOCM_DTR
:0) +
2862 ((info
->serial_signals
& SerialSignal_DCD
) ? TIOCM_CAR
:0) +
2863 ((info
->serial_signals
& SerialSignal_RI
) ? TIOCM_RNG
:0) +
2864 ((info
->serial_signals
& SerialSignal_DSR
) ? TIOCM_DSR
:0) +
2865 ((info
->serial_signals
& SerialSignal_CTS
) ? TIOCM_CTS
:0);
2867 if (debug_level
>= DEBUG_LEVEL_INFO
)
2868 printk("%s(%d):%s tiocmget() value=%08X\n",
2869 __FILE__
,__LINE__
, info
->device_name
, result
);
2873 /* set modem control signals (DTR/RTS)
2875 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
2876 unsigned int set
, unsigned int clear
)
2878 struct mgsl_struct
*info
= tty
->driver_data
;
2879 unsigned long flags
;
2881 if (debug_level
>= DEBUG_LEVEL_INFO
)
2882 printk("%s(%d):%s tiocmset(%x,%x)\n",
2883 __FILE__
,__LINE__
,info
->device_name
, set
, clear
);
2885 if (set
& TIOCM_RTS
)
2886 info
->serial_signals
|= SerialSignal_RTS
;
2887 if (set
& TIOCM_DTR
)
2888 info
->serial_signals
|= SerialSignal_DTR
;
2889 if (clear
& TIOCM_RTS
)
2890 info
->serial_signals
&= ~SerialSignal_RTS
;
2891 if (clear
& TIOCM_DTR
)
2892 info
->serial_signals
&= ~SerialSignal_DTR
;
2894 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2895 usc_set_serial_signals(info
);
2896 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2901 /* mgsl_break() Set or clear transmit break condition
2903 * Arguments: tty pointer to tty instance data
2904 * break_state -1=set break condition, 0=clear
2905 * Return Value: error code
2907 static int mgsl_break(struct tty_struct
*tty
, int break_state
)
2909 struct mgsl_struct
* info
= tty
->driver_data
;
2910 unsigned long flags
;
2912 if (debug_level
>= DEBUG_LEVEL_INFO
)
2913 printk("%s(%d):mgsl_break(%s,%d)\n",
2914 __FILE__
,__LINE__
, info
->device_name
, break_state
);
2916 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_break"))
2919 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2920 if (break_state
== -1)
2921 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) | BIT7
));
2923 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) & ~BIT7
));
2924 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2927 } /* end of mgsl_break() */
2929 /* mgsl_ioctl() Service an IOCTL request
2933 * tty pointer to tty instance data
2934 * file pointer to associated file object for device
2935 * cmd IOCTL command code
2936 * arg command argument/context
2938 * Return Value: 0 if success, otherwise error code
2940 static int mgsl_ioctl(struct tty_struct
*tty
, struct file
* file
,
2941 unsigned int cmd
, unsigned long arg
)
2943 struct mgsl_struct
* info
= tty
->driver_data
;
2945 if (debug_level
>= DEBUG_LEVEL_INFO
)
2946 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__
,__LINE__
,
2947 info
->device_name
, cmd
);
2949 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_ioctl"))
2952 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
2953 (cmd
!= TIOCMIWAIT
) && (cmd
!= TIOCGICOUNT
)) {
2954 if (tty
->flags
& (1 << TTY_IO_ERROR
))
2958 return mgsl_ioctl_common(info
, cmd
, arg
);
2961 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
)
2964 struct mgsl_icount cnow
; /* kernel counter temps */
2965 void __user
*argp
= (void __user
*)arg
;
2966 struct serial_icounter_struct __user
*p_cuser
; /* user space */
2967 unsigned long flags
;
2970 case MGSL_IOCGPARAMS
:
2971 return mgsl_get_params(info
, argp
);
2972 case MGSL_IOCSPARAMS
:
2973 return mgsl_set_params(info
, argp
);
2974 case MGSL_IOCGTXIDLE
:
2975 return mgsl_get_txidle(info
, argp
);
2976 case MGSL_IOCSTXIDLE
:
2977 return mgsl_set_txidle(info
,(int)arg
);
2978 case MGSL_IOCTXENABLE
:
2979 return mgsl_txenable(info
,(int)arg
);
2980 case MGSL_IOCRXENABLE
:
2981 return mgsl_rxenable(info
,(int)arg
);
2982 case MGSL_IOCTXABORT
:
2983 return mgsl_txabort(info
);
2984 case MGSL_IOCGSTATS
:
2985 return mgsl_get_stats(info
, argp
);
2986 case MGSL_IOCWAITEVENT
:
2987 return mgsl_wait_event(info
, argp
);
2988 case MGSL_IOCLOOPTXDONE
:
2989 return mgsl_loopmode_send_done(info
);
2990 /* Wait for modem input (DCD,RI,DSR,CTS) change
2991 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
2994 return modem_input_wait(info
,(int)arg
);
2997 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2998 * Return: write counters to the user passed counter struct
2999 * NB: both 1->0 and 0->1 transitions are counted except for
3000 * RI where only 0->1 is counted.
3003 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3004 cnow
= info
->icount
;
3005 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3007 PUT_USER(error
,cnow
.cts
, &p_cuser
->cts
);
3008 if (error
) return error
;
3009 PUT_USER(error
,cnow
.dsr
, &p_cuser
->dsr
);
3010 if (error
) return error
;
3011 PUT_USER(error
,cnow
.rng
, &p_cuser
->rng
);
3012 if (error
) return error
;
3013 PUT_USER(error
,cnow
.dcd
, &p_cuser
->dcd
);
3014 if (error
) return error
;
3015 PUT_USER(error
,cnow
.rx
, &p_cuser
->rx
);
3016 if (error
) return error
;
3017 PUT_USER(error
,cnow
.tx
, &p_cuser
->tx
);
3018 if (error
) return error
;
3019 PUT_USER(error
,cnow
.frame
, &p_cuser
->frame
);
3020 if (error
) return error
;
3021 PUT_USER(error
,cnow
.overrun
, &p_cuser
->overrun
);
3022 if (error
) return error
;
3023 PUT_USER(error
,cnow
.parity
, &p_cuser
->parity
);
3024 if (error
) return error
;
3025 PUT_USER(error
,cnow
.brk
, &p_cuser
->brk
);
3026 if (error
) return error
;
3027 PUT_USER(error
,cnow
.buf_overrun
, &p_cuser
->buf_overrun
);
3028 if (error
) return error
;
3031 return -ENOIOCTLCMD
;
3036 /* mgsl_set_termios()
3038 * Set new termios settings
3042 * tty pointer to tty structure
3043 * termios pointer to buffer to hold returned old termios
3045 * Return Value: None
3047 static void mgsl_set_termios(struct tty_struct
*tty
, struct ktermios
*old_termios
)
3049 struct mgsl_struct
*info
= tty
->driver_data
;
3050 unsigned long flags
;
3052 if (debug_level
>= DEBUG_LEVEL_INFO
)
3053 printk("%s(%d):mgsl_set_termios %s\n", __FILE__
,__LINE__
,
3054 tty
->driver
->name
);
3056 mgsl_change_params(info
);
3058 /* Handle transition to B0 status */
3059 if (old_termios
->c_cflag
& CBAUD
&&
3060 !(tty
->termios
->c_cflag
& CBAUD
)) {
3061 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
3062 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3063 usc_set_serial_signals(info
);
3064 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3067 /* Handle transition away from B0 status */
3068 if (!(old_termios
->c_cflag
& CBAUD
) &&
3069 tty
->termios
->c_cflag
& CBAUD
) {
3070 info
->serial_signals
|= SerialSignal_DTR
;
3071 if (!(tty
->termios
->c_cflag
& CRTSCTS
) ||
3072 !test_bit(TTY_THROTTLED
, &tty
->flags
)) {
3073 info
->serial_signals
|= SerialSignal_RTS
;
3075 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3076 usc_set_serial_signals(info
);
3077 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3080 /* Handle turning off CRTSCTS */
3081 if (old_termios
->c_cflag
& CRTSCTS
&&
3082 !(tty
->termios
->c_cflag
& CRTSCTS
)) {
3083 tty
->hw_stopped
= 0;
3087 } /* end of mgsl_set_termios() */
3091 * Called when port is closed. Wait for remaining data to be
3092 * sent. Disable port and free resources.
3096 * tty pointer to open tty structure
3097 * filp pointer to open file object
3099 * Return Value: None
3101 static void mgsl_close(struct tty_struct
*tty
, struct file
* filp
)
3103 struct mgsl_struct
* info
= tty
->driver_data
;
3105 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_close"))
3108 if (debug_level
>= DEBUG_LEVEL_INFO
)
3109 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3110 __FILE__
,__LINE__
, info
->device_name
, info
->port
.count
);
3112 if (tty_port_close_start(&info
->port
, tty
, filp
) == 0)
3115 mutex_lock(&info
->port
.mutex
);
3116 if (info
->port
.flags
& ASYNC_INITIALIZED
)
3117 mgsl_wait_until_sent(tty
, info
->timeout
);
3118 mgsl_flush_buffer(tty
);
3119 tty_ldisc_flush(tty
);
3121 mutex_unlock(&info
->port
.mutex
);
3123 tty_port_close_end(&info
->port
, tty
);
3124 info
->port
.tty
= NULL
;
3126 if (debug_level
>= DEBUG_LEVEL_INFO
)
3127 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__
,__LINE__
,
3128 tty
->driver
->name
, info
->port
.count
);
3130 } /* end of mgsl_close() */
3132 /* mgsl_wait_until_sent()
3134 * Wait until the transmitter is empty.
3138 * tty pointer to tty info structure
3139 * timeout time to wait for send completion
3141 * Return Value: None
3143 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
)
3145 struct mgsl_struct
* info
= tty
->driver_data
;
3146 unsigned long orig_jiffies
, char_time
;
3151 if (debug_level
>= DEBUG_LEVEL_INFO
)
3152 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3153 __FILE__
,__LINE__
, info
->device_name
);
3155 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_wait_until_sent"))
3158 if (!(info
->port
.flags
& ASYNC_INITIALIZED
))
3161 orig_jiffies
= jiffies
;
3163 /* Set check interval to 1/5 of estimated time to
3164 * send a character, and make it at least 1. The check
3165 * interval should also be less than the timeout.
3166 * Note: use tight timings here to satisfy the NIST-PCTS.
3169 if ( info
->params
.data_rate
) {
3170 char_time
= info
->timeout
/(32 * 5);
3177 char_time
= min_t(unsigned long, char_time
, timeout
);
3179 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
3180 info
->params
.mode
== MGSL_MODE_RAW
) {
3181 while (info
->tx_active
) {
3182 msleep_interruptible(jiffies_to_msecs(char_time
));
3183 if (signal_pending(current
))
3185 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3189 while (!(usc_InReg(info
,TCSR
) & TXSTATUS_ALL_SENT
) &&
3191 msleep_interruptible(jiffies_to_msecs(char_time
));
3192 if (signal_pending(current
))
3194 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3200 if (debug_level
>= DEBUG_LEVEL_INFO
)
3201 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3202 __FILE__
,__LINE__
, info
->device_name
);
3204 } /* end of mgsl_wait_until_sent() */
3208 * Called by tty_hangup() when a hangup is signaled.
3209 * This is the same as to closing all open files for the port.
3211 * Arguments: tty pointer to associated tty object
3212 * Return Value: None
3214 static void mgsl_hangup(struct tty_struct
*tty
)
3216 struct mgsl_struct
* info
= tty
->driver_data
;
3218 if (debug_level
>= DEBUG_LEVEL_INFO
)
3219 printk("%s(%d):mgsl_hangup(%s)\n",
3220 __FILE__
,__LINE__
, info
->device_name
);
3222 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_hangup"))
3225 mgsl_flush_buffer(tty
);
3228 info
->port
.count
= 0;
3229 info
->port
.flags
&= ~ASYNC_NORMAL_ACTIVE
;
3230 info
->port
.tty
= NULL
;
3232 wake_up_interruptible(&info
->port
.open_wait
);
3234 } /* end of mgsl_hangup() */
3239 * Return true if carrier is raised
3242 static int carrier_raised(struct tty_port
*port
)
3244 unsigned long flags
;
3245 struct mgsl_struct
*info
= container_of(port
, struct mgsl_struct
, port
);
3247 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
3248 usc_get_serial_signals(info
);
3249 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
3250 return (info
->serial_signals
& SerialSignal_DCD
) ? 1 : 0;
3253 static void dtr_rts(struct tty_port
*port
, int on
)
3255 struct mgsl_struct
*info
= container_of(port
, struct mgsl_struct
, port
);
3256 unsigned long flags
;
3258 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3260 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
3262 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
3263 usc_set_serial_signals(info
);
3264 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3268 /* block_til_ready()
3270 * Block the current process until the specified port
3271 * is ready to be opened.
3275 * tty pointer to tty info structure
3276 * filp pointer to open file object
3277 * info pointer to device instance data
3279 * Return Value: 0 if success, otherwise error code
3281 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,
3282 struct mgsl_struct
*info
)
3284 DECLARE_WAITQUEUE(wait
, current
);
3286 bool do_clocal
= false;
3287 bool extra_count
= false;
3288 unsigned long flags
;
3290 struct tty_port
*port
= &info
->port
;
3292 if (debug_level
>= DEBUG_LEVEL_INFO
)
3293 printk("%s(%d):block_til_ready on %s\n",
3294 __FILE__
,__LINE__
, tty
->driver
->name
);
3296 if (filp
->f_flags
& O_NONBLOCK
|| tty
->flags
& (1 << TTY_IO_ERROR
)){
3297 /* nonblock mode is set or port is not enabled */
3298 port
->flags
|= ASYNC_NORMAL_ACTIVE
;
3302 if (tty
->termios
->c_cflag
& CLOCAL
)
3305 /* Wait for carrier detect and the line to become
3306 * free (i.e., not in use by the callout). While we are in
3307 * this loop, port->count is dropped by one, so that
3308 * mgsl_close() knows when to free things. We restore it upon
3309 * exit, either normal or abnormal.
3313 add_wait_queue(&port
->open_wait
, &wait
);
3315 if (debug_level
>= DEBUG_LEVEL_INFO
)
3316 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3317 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3319 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
3320 if (!tty_hung_up_p(filp
)) {
3324 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
3325 port
->blocked_open
++;
3328 if (tty
->termios
->c_cflag
& CBAUD
)
3329 tty_port_raise_dtr_rts(port
);
3331 set_current_state(TASK_INTERRUPTIBLE
);
3333 if (tty_hung_up_p(filp
) || !(port
->flags
& ASYNC_INITIALIZED
)){
3334 retval
= (port
->flags
& ASYNC_HUP_NOTIFY
) ?
3335 -EAGAIN
: -ERESTARTSYS
;
3339 dcd
= tty_port_carrier_raised(&info
->port
);
3341 if (!(port
->flags
& ASYNC_CLOSING
) && (do_clocal
|| dcd
))
3344 if (signal_pending(current
)) {
3345 retval
= -ERESTARTSYS
;
3349 if (debug_level
>= DEBUG_LEVEL_INFO
)
3350 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3351 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3358 set_current_state(TASK_RUNNING
);
3359 remove_wait_queue(&port
->open_wait
, &wait
);
3363 port
->blocked_open
--;
3365 if (debug_level
>= DEBUG_LEVEL_INFO
)
3366 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3367 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3370 port
->flags
|= ASYNC_NORMAL_ACTIVE
;
3374 } /* end of block_til_ready() */
3378 * Called when a port is opened. Init and enable port.
3379 * Perform serial-specific initialization for the tty structure.
3381 * Arguments: tty pointer to tty info structure
3382 * filp associated file pointer
3384 * Return Value: 0 if success, otherwise error code
3386 static int mgsl_open(struct tty_struct
*tty
, struct file
* filp
)
3388 struct mgsl_struct
*info
;
3390 unsigned long flags
;
3392 /* verify range of specified line number */
3394 if ((line
< 0) || (line
>= mgsl_device_count
)) {
3395 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3396 __FILE__
,__LINE__
,line
);
3400 /* find the info structure for the specified line */
3401 info
= mgsl_device_list
;
3402 while(info
&& info
->line
!= line
)
3403 info
= info
->next_device
;
3404 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_open"))
3407 tty
->driver_data
= info
;
3408 info
->port
.tty
= tty
;
3410 if (debug_level
>= DEBUG_LEVEL_INFO
)
3411 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3412 __FILE__
,__LINE__
,tty
->driver
->name
, info
->port
.count
);
3414 /* If port is closing, signal caller to try again */
3415 if (tty_hung_up_p(filp
) || info
->port
.flags
& ASYNC_CLOSING
){
3416 if (info
->port
.flags
& ASYNC_CLOSING
)
3417 interruptible_sleep_on(&info
->port
.close_wait
);
3418 retval
= ((info
->port
.flags
& ASYNC_HUP_NOTIFY
) ?
3419 -EAGAIN
: -ERESTARTSYS
);
3423 info
->port
.tty
->low_latency
= (info
->port
.flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
3425 spin_lock_irqsave(&info
->netlock
, flags
);
3426 if (info
->netcount
) {
3428 spin_unlock_irqrestore(&info
->netlock
, flags
);
3432 spin_unlock_irqrestore(&info
->netlock
, flags
);
3434 if (info
->port
.count
== 1) {
3435 /* 1st open on this device, init hardware */
3436 retval
= startup(info
);
3441 retval
= block_til_ready(tty
, filp
, info
);
3443 if (debug_level
>= DEBUG_LEVEL_INFO
)
3444 printk("%s(%d):block_til_ready(%s) returned %d\n",
3445 __FILE__
,__LINE__
, info
->device_name
, retval
);
3449 if (debug_level
>= DEBUG_LEVEL_INFO
)
3450 printk("%s(%d):mgsl_open(%s) success\n",
3451 __FILE__
,__LINE__
, info
->device_name
);
3456 if (tty
->count
== 1)
3457 info
->port
.tty
= NULL
; /* tty layer will release tty struct */
3458 if(info
->port
.count
)
3464 } /* end of mgsl_open() */
3467 * /proc fs routines....
3470 static inline void line_info(struct seq_file
*m
, struct mgsl_struct
*info
)
3473 unsigned long flags
;
3475 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3476 seq_printf(m
, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3477 info
->device_name
, info
->io_base
, info
->irq_level
,
3478 info
->phys_memory_base
, info
->phys_lcr_base
);
3480 seq_printf(m
, "%s:(E)ISA io:%04X irq:%d dma:%d",
3481 info
->device_name
, info
->io_base
,
3482 info
->irq_level
, info
->dma_level
);
3485 /* output current serial signal states */
3486 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3487 usc_get_serial_signals(info
);
3488 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3492 if (info
->serial_signals
& SerialSignal_RTS
)
3493 strcat(stat_buf
, "|RTS");
3494 if (info
->serial_signals
& SerialSignal_CTS
)
3495 strcat(stat_buf
, "|CTS");
3496 if (info
->serial_signals
& SerialSignal_DTR
)
3497 strcat(stat_buf
, "|DTR");
3498 if (info
->serial_signals
& SerialSignal_DSR
)
3499 strcat(stat_buf
, "|DSR");
3500 if (info
->serial_signals
& SerialSignal_DCD
)
3501 strcat(stat_buf
, "|CD");
3502 if (info
->serial_signals
& SerialSignal_RI
)
3503 strcat(stat_buf
, "|RI");
3505 if (info
->params
.mode
== MGSL_MODE_HDLC
||
3506 info
->params
.mode
== MGSL_MODE_RAW
) {
3507 seq_printf(m
, " HDLC txok:%d rxok:%d",
3508 info
->icount
.txok
, info
->icount
.rxok
);
3509 if (info
->icount
.txunder
)
3510 seq_printf(m
, " txunder:%d", info
->icount
.txunder
);
3511 if (info
->icount
.txabort
)
3512 seq_printf(m
, " txabort:%d", info
->icount
.txabort
);
3513 if (info
->icount
.rxshort
)
3514 seq_printf(m
, " rxshort:%d", info
->icount
.rxshort
);
3515 if (info
->icount
.rxlong
)
3516 seq_printf(m
, " rxlong:%d", info
->icount
.rxlong
);
3517 if (info
->icount
.rxover
)
3518 seq_printf(m
, " rxover:%d", info
->icount
.rxover
);
3519 if (info
->icount
.rxcrc
)
3520 seq_printf(m
, " rxcrc:%d", info
->icount
.rxcrc
);
3522 seq_printf(m
, " ASYNC tx:%d rx:%d",
3523 info
->icount
.tx
, info
->icount
.rx
);
3524 if (info
->icount
.frame
)
3525 seq_printf(m
, " fe:%d", info
->icount
.frame
);
3526 if (info
->icount
.parity
)
3527 seq_printf(m
, " pe:%d", info
->icount
.parity
);
3528 if (info
->icount
.brk
)
3529 seq_printf(m
, " brk:%d", info
->icount
.brk
);
3530 if (info
->icount
.overrun
)
3531 seq_printf(m
, " oe:%d", info
->icount
.overrun
);
3534 /* Append serial signal status to end */
3535 seq_printf(m
, " %s\n", stat_buf
+1);
3537 seq_printf(m
, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3538 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
3541 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3543 u16 Tcsr
= usc_InReg( info
, TCSR
);
3544 u16 Tdmr
= usc_InDmaReg( info
, TDMR
);
3545 u16 Ticr
= usc_InReg( info
, TICR
);
3546 u16 Rscr
= usc_InReg( info
, RCSR
);
3547 u16 Rdmr
= usc_InDmaReg( info
, RDMR
);
3548 u16 Ricr
= usc_InReg( info
, RICR
);
3549 u16 Icr
= usc_InReg( info
, ICR
);
3550 u16 Dccr
= usc_InReg( info
, DCCR
);
3551 u16 Tmr
= usc_InReg( info
, TMR
);
3552 u16 Tccr
= usc_InReg( info
, TCCR
);
3553 u16 Ccar
= inw( info
->io_base
+ CCAR
);
3554 seq_printf(m
, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3555 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3556 Tcsr
,Tdmr
,Ticr
,Rscr
,Rdmr
,Ricr
,Icr
,Dccr
,Tmr
,Tccr
,Ccar
);
3558 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3561 /* Called to print information about devices */
3562 static int mgsl_proc_show(struct seq_file
*m
, void *v
)
3564 struct mgsl_struct
*info
;
3566 seq_printf(m
, "synclink driver:%s\n", driver_version
);
3568 info
= mgsl_device_list
;
3571 info
= info
->next_device
;
3576 static int mgsl_proc_open(struct inode
*inode
, struct file
*file
)
3578 return single_open(file
, mgsl_proc_show
, NULL
);
3581 static const struct file_operations mgsl_proc_fops
= {
3582 .owner
= THIS_MODULE
,
3583 .open
= mgsl_proc_open
,
3585 .llseek
= seq_lseek
,
3586 .release
= single_release
,
3589 /* mgsl_allocate_dma_buffers()
3591 * Allocate and format DMA buffers (ISA adapter)
3592 * or format shared memory buffers (PCI adapter).
3594 * Arguments: info pointer to device instance data
3595 * Return Value: 0 if success, otherwise error
3597 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
)
3599 unsigned short BuffersPerFrame
;
3601 info
->last_mem_alloc
= 0;
3603 /* Calculate the number of DMA buffers necessary to hold the */
3604 /* largest allowable frame size. Note: If the max frame size is */
3605 /* not an even multiple of the DMA buffer size then we need to */
3606 /* round the buffer count per frame up one. */
3608 BuffersPerFrame
= (unsigned short)(info
->max_frame_size
/DMABUFFERSIZE
);
3609 if ( info
->max_frame_size
% DMABUFFERSIZE
)
3612 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3614 * The PCI adapter has 256KBytes of shared memory to use.
3615 * This is 64 PAGE_SIZE buffers.
3617 * The first page is used for padding at this time so the
3618 * buffer list does not begin at offset 0 of the PCI
3619 * adapter's shared memory.
3621 * The 2nd page is used for the buffer list. A 4K buffer
3622 * list can hold 128 DMA_BUFFER structures at 32 bytes
3625 * This leaves 62 4K pages.
3627 * The next N pages are used for transmit frame(s). We
3628 * reserve enough 4K page blocks to hold the required
3629 * number of transmit dma buffers (num_tx_dma_buffers),
3630 * each of MaxFrameSize size.
3632 * Of the remaining pages (62-N), determine how many can
3633 * be used to receive full MaxFrameSize inbound frames
3635 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3636 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3638 /* Calculate the number of PAGE_SIZE buffers needed for */
3639 /* receive and transmit DMA buffers. */
3642 /* Calculate the number of DMA buffers necessary to */
3643 /* hold 7 max size receive frames and one max size transmit frame. */
3644 /* The receive buffer count is bumped by one so we avoid an */
3645 /* End of List condition if all receive buffers are used when */
3646 /* using linked list DMA buffers. */
3648 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3649 info
->rx_buffer_count
= (BuffersPerFrame
* MAXRXFRAMES
) + 6;
3652 * limit total TxBuffers & RxBuffers to 62 4K total
3653 * (ala PCI Allocation)
3656 if ( (info
->tx_buffer_count
+ info
->rx_buffer_count
) > 62 )
3657 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3661 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3662 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3663 __FILE__
,__LINE__
, info
->tx_buffer_count
,info
->rx_buffer_count
);
3665 if ( mgsl_alloc_buffer_list_memory( info
) < 0 ||
3666 mgsl_alloc_frame_memory(info
, info
->rx_buffer_list
, info
->rx_buffer_count
) < 0 ||
3667 mgsl_alloc_frame_memory(info
, info
->tx_buffer_list
, info
->tx_buffer_count
) < 0 ||
3668 mgsl_alloc_intermediate_rxbuffer_memory(info
) < 0 ||
3669 mgsl_alloc_intermediate_txbuffer_memory(info
) < 0 ) {
3670 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__
,__LINE__
);
3674 mgsl_reset_rx_dma_buffers( info
);
3675 mgsl_reset_tx_dma_buffers( info
);
3679 } /* end of mgsl_allocate_dma_buffers() */
3682 * mgsl_alloc_buffer_list_memory()
3684 * Allocate a common DMA buffer for use as the
3685 * receive and transmit buffer lists.
3687 * A buffer list is a set of buffer entries where each entry contains
3688 * a pointer to an actual buffer and a pointer to the next buffer entry
3689 * (plus some other info about the buffer).
3691 * The buffer entries for a list are built to form a circular list so
3692 * that when the entire list has been traversed you start back at the
3695 * This function allocates memory for just the buffer entries.
3696 * The links (pointer to next entry) are filled in with the physical
3697 * address of the next entry so the adapter can navigate the list
3698 * using bus master DMA. The pointers to the actual buffers are filled
3699 * out later when the actual buffers are allocated.
3701 * Arguments: info pointer to device instance data
3702 * Return Value: 0 if success, otherwise error
3704 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct
*info
)
3708 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3709 /* PCI adapter uses shared memory. */
3710 info
->buffer_list
= info
->memory_base
+ info
->last_mem_alloc
;
3711 info
->buffer_list_phys
= info
->last_mem_alloc
;
3712 info
->last_mem_alloc
+= BUFFERLISTSIZE
;
3714 /* ISA adapter uses system memory. */
3715 /* The buffer lists are allocated as a common buffer that both */
3716 /* the processor and adapter can access. This allows the driver to */
3717 /* inspect portions of the buffer while other portions are being */
3718 /* updated by the adapter using Bus Master DMA. */
3720 info
->buffer_list
= dma_alloc_coherent(NULL
, BUFFERLISTSIZE
, &info
->buffer_list_dma_addr
, GFP_KERNEL
);
3721 if (info
->buffer_list
== NULL
)
3723 info
->buffer_list_phys
= (u32
)(info
->buffer_list_dma_addr
);
3726 /* We got the memory for the buffer entry lists. */
3727 /* Initialize the memory block to all zeros. */
3728 memset( info
->buffer_list
, 0, BUFFERLISTSIZE
);
3730 /* Save virtual address pointers to the receive and */
3731 /* transmit buffer lists. (Receive 1st). These pointers will */
3732 /* be used by the processor to access the lists. */
3733 info
->rx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3734 info
->tx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3735 info
->tx_buffer_list
+= info
->rx_buffer_count
;
3738 * Build the links for the buffer entry lists such that
3739 * two circular lists are built. (Transmit and Receive).
3741 * Note: the links are physical addresses
3742 * which are read by the adapter to determine the next
3743 * buffer entry to use.
3746 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
3747 /* calculate and store physical address of this buffer entry */
3748 info
->rx_buffer_list
[i
].phys_entry
=
3749 info
->buffer_list_phys
+ (i
* sizeof(DMABUFFERENTRY
));
3751 /* calculate and store physical address of */
3752 /* next entry in cirular list of entries */
3754 info
->rx_buffer_list
[i
].link
= info
->buffer_list_phys
;
3756 if ( i
< info
->rx_buffer_count
- 1 )
3757 info
->rx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3760 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
3761 /* calculate and store physical address of this buffer entry */
3762 info
->tx_buffer_list
[i
].phys_entry
= info
->buffer_list_phys
+
3763 ((info
->rx_buffer_count
+ i
) * sizeof(DMABUFFERENTRY
));
3765 /* calculate and store physical address of */
3766 /* next entry in cirular list of entries */
3768 info
->tx_buffer_list
[i
].link
= info
->buffer_list_phys
+
3769 info
->rx_buffer_count
* sizeof(DMABUFFERENTRY
);
3771 if ( i
< info
->tx_buffer_count
- 1 )
3772 info
->tx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3777 } /* end of mgsl_alloc_buffer_list_memory() */
3779 /* Free DMA buffers allocated for use as the
3780 * receive and transmit buffer lists.
3783 * The data transfer buffers associated with the buffer list
3784 * MUST be freed before freeing the buffer list itself because
3785 * the buffer list contains the information necessary to free
3786 * the individual buffers!
3788 static void mgsl_free_buffer_list_memory( struct mgsl_struct
*info
)
3790 if (info
->buffer_list
&& info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3791 dma_free_coherent(NULL
, BUFFERLISTSIZE
, info
->buffer_list
, info
->buffer_list_dma_addr
);
3793 info
->buffer_list
= NULL
;
3794 info
->rx_buffer_list
= NULL
;
3795 info
->tx_buffer_list
= NULL
;
3797 } /* end of mgsl_free_buffer_list_memory() */
3800 * mgsl_alloc_frame_memory()
3802 * Allocate the frame DMA buffers used by the specified buffer list.
3803 * Each DMA buffer will be one memory page in size. This is necessary
3804 * because memory can fragment enough that it may be impossible
3809 * info pointer to device instance data
3810 * BufferList pointer to list of buffer entries
3811 * Buffercount count of buffer entries in buffer list
3813 * Return Value: 0 if success, otherwise -ENOMEM
3815 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
,DMABUFFERENTRY
*BufferList
,int Buffercount
)
3820 /* Allocate page sized buffers for the receive buffer list */
3822 for ( i
= 0; i
< Buffercount
; i
++ ) {
3823 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3824 /* PCI adapter uses shared memory buffers. */
3825 BufferList
[i
].virt_addr
= info
->memory_base
+ info
->last_mem_alloc
;
3826 phys_addr
= info
->last_mem_alloc
;
3827 info
->last_mem_alloc
+= DMABUFFERSIZE
;
3829 /* ISA adapter uses system memory. */
3830 BufferList
[i
].virt_addr
= dma_alloc_coherent(NULL
, DMABUFFERSIZE
, &BufferList
[i
].dma_addr
, GFP_KERNEL
);
3831 if (BufferList
[i
].virt_addr
== NULL
)
3833 phys_addr
= (u32
)(BufferList
[i
].dma_addr
);
3835 BufferList
[i
].phys_addr
= phys_addr
;
3840 } /* end of mgsl_alloc_frame_memory() */
3843 * mgsl_free_frame_memory()
3845 * Free the buffers associated with
3846 * each buffer entry of a buffer list.
3850 * info pointer to device instance data
3851 * BufferList pointer to list of buffer entries
3852 * Buffercount count of buffer entries in buffer list
3854 * Return Value: None
3856 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
, int Buffercount
)
3861 for ( i
= 0 ; i
< Buffercount
; i
++ ) {
3862 if ( BufferList
[i
].virt_addr
) {
3863 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3864 dma_free_coherent(NULL
, DMABUFFERSIZE
, BufferList
[i
].virt_addr
, BufferList
[i
].dma_addr
);
3865 BufferList
[i
].virt_addr
= NULL
;
3870 } /* end of mgsl_free_frame_memory() */
3872 /* mgsl_free_dma_buffers()
3876 * Arguments: info pointer to device instance data
3877 * Return Value: None
3879 static void mgsl_free_dma_buffers( struct mgsl_struct
*info
)
3881 mgsl_free_frame_memory( info
, info
->rx_buffer_list
, info
->rx_buffer_count
);
3882 mgsl_free_frame_memory( info
, info
->tx_buffer_list
, info
->tx_buffer_count
);
3883 mgsl_free_buffer_list_memory( info
);
3885 } /* end of mgsl_free_dma_buffers() */
3889 * mgsl_alloc_intermediate_rxbuffer_memory()
3891 * Allocate a buffer large enough to hold max_frame_size. This buffer
3892 * is used to pass an assembled frame to the line discipline.
3896 * info pointer to device instance data
3898 * Return Value: 0 if success, otherwise -ENOMEM
3900 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
3902 info
->intermediate_rxbuffer
= kmalloc(info
->max_frame_size
, GFP_KERNEL
| GFP_DMA
);
3903 if ( info
->intermediate_rxbuffer
== NULL
)
3908 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3911 * mgsl_free_intermediate_rxbuffer_memory()
3916 * info pointer to device instance data
3918 * Return Value: None
3920 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
3922 kfree(info
->intermediate_rxbuffer
);
3923 info
->intermediate_rxbuffer
= NULL
;
3925 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
3928 * mgsl_alloc_intermediate_txbuffer_memory()
3930 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3931 * This buffer is used to load transmit frames into the adapter's dma transfer
3932 * buffers when there is sufficient space.
3936 * info pointer to device instance data
3938 * Return Value: 0 if success, otherwise -ENOMEM
3940 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
3944 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3945 printk("%s %s(%d) allocating %d tx holding buffers\n",
3946 info
->device_name
, __FILE__
,__LINE__
,info
->num_tx_holding_buffers
);
3948 memset(info
->tx_holding_buffers
,0,sizeof(info
->tx_holding_buffers
));
3950 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
3951 info
->tx_holding_buffers
[i
].buffer
=
3952 kmalloc(info
->max_frame_size
, GFP_KERNEL
);
3953 if (info
->tx_holding_buffers
[i
].buffer
== NULL
) {
3954 for (--i
; i
>= 0; i
--) {
3955 kfree(info
->tx_holding_buffers
[i
].buffer
);
3956 info
->tx_holding_buffers
[i
].buffer
= NULL
;
3964 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
3967 * mgsl_free_intermediate_txbuffer_memory()
3972 * info pointer to device instance data
3974 * Return Value: None
3976 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
3980 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
3981 kfree(info
->tx_holding_buffers
[i
].buffer
);
3982 info
->tx_holding_buffers
[i
].buffer
= NULL
;
3985 info
->get_tx_holding_index
= 0;
3986 info
->put_tx_holding_index
= 0;
3987 info
->tx_holding_count
= 0;
3989 } /* end of mgsl_free_intermediate_txbuffer_memory() */
3993 * load_next_tx_holding_buffer()
3995 * attempts to load the next buffered tx request into the
4000 * info pointer to device instance data
4002 * Return Value: true if next buffered tx request loaded
4003 * into adapter's tx dma buffer,
4006 static bool load_next_tx_holding_buffer(struct mgsl_struct
*info
)
4010 if ( info
->tx_holding_count
) {
4011 /* determine if we have enough tx dma buffers
4012 * to accommodate the next tx frame
4014 struct tx_holding_buffer
*ptx
=
4015 &info
->tx_holding_buffers
[info
->get_tx_holding_index
];
4016 int num_free
= num_free_tx_dma_buffers(info
);
4017 int num_needed
= ptx
->buffer_size
/ DMABUFFERSIZE
;
4018 if ( ptx
->buffer_size
% DMABUFFERSIZE
)
4021 if (num_needed
<= num_free
) {
4022 info
->xmit_cnt
= ptx
->buffer_size
;
4023 mgsl_load_tx_dma_buffer(info
,ptx
->buffer
,ptx
->buffer_size
);
4025 --info
->tx_holding_count
;
4026 if ( ++info
->get_tx_holding_index
>= info
->num_tx_holding_buffers
)
4027 info
->get_tx_holding_index
=0;
4029 /* restart transmit timer */
4030 mod_timer(&info
->tx_timer
, jiffies
+ msecs_to_jiffies(5000));
4040 * save_tx_buffer_request()
4042 * attempt to store transmit frame request for later transmission
4046 * info pointer to device instance data
4047 * Buffer pointer to buffer containing frame to load
4048 * BufferSize size in bytes of frame in Buffer
4050 * Return Value: 1 if able to store, 0 otherwise
4052 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
)
4054 struct tx_holding_buffer
*ptx
;
4056 if ( info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
4057 return 0; /* all buffers in use */
4060 ptx
= &info
->tx_holding_buffers
[info
->put_tx_holding_index
];
4061 ptx
->buffer_size
= BufferSize
;
4062 memcpy( ptx
->buffer
, Buffer
, BufferSize
);
4064 ++info
->tx_holding_count
;
4065 if ( ++info
->put_tx_holding_index
>= info
->num_tx_holding_buffers
)
4066 info
->put_tx_holding_index
=0;
4071 static int mgsl_claim_resources(struct mgsl_struct
*info
)
4073 if (request_region(info
->io_base
,info
->io_addr_size
,"synclink") == NULL
) {
4074 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4075 __FILE__
,__LINE__
,info
->device_name
, info
->io_base
);
4078 info
->io_addr_requested
= true;
4080 if ( request_irq(info
->irq_level
,mgsl_interrupt
,info
->irq_flags
,
4081 info
->device_name
, info
) < 0 ) {
4082 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4083 __FILE__
,__LINE__
,info
->device_name
, info
->irq_level
);
4086 info
->irq_requested
= true;
4088 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4089 if (request_mem_region(info
->phys_memory_base
,0x40000,"synclink") == NULL
) {
4090 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4091 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4094 info
->shared_mem_requested
= true;
4095 if (request_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128,"synclink") == NULL
) {
4096 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4097 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
+ info
->lcr_offset
);
4100 info
->lcr_mem_requested
= true;
4102 info
->memory_base
= ioremap_nocache(info
->phys_memory_base
,
4104 if (!info
->memory_base
) {
4105 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4106 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4110 if ( !mgsl_memory_test(info
) ) {
4111 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4112 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4116 info
->lcr_base
= ioremap_nocache(info
->phys_lcr_base
,
4118 if (!info
->lcr_base
) {
4119 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4120 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
4123 info
->lcr_base
+= info
->lcr_offset
;
4126 /* claim DMA channel */
4128 if (request_dma(info
->dma_level
,info
->device_name
) < 0){
4129 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4130 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4131 mgsl_release_resources( info
);
4134 info
->dma_requested
= true;
4136 /* ISA adapter uses bus master DMA */
4137 set_dma_mode(info
->dma_level
,DMA_MODE_CASCADE
);
4138 enable_dma(info
->dma_level
);
4141 if ( mgsl_allocate_dma_buffers(info
) < 0 ) {
4142 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4143 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4149 mgsl_release_resources(info
);
4152 } /* end of mgsl_claim_resources() */
4154 static void mgsl_release_resources(struct mgsl_struct
*info
)
4156 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4157 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4158 __FILE__
,__LINE__
,info
->device_name
);
4160 if ( info
->irq_requested
) {
4161 free_irq(info
->irq_level
, info
);
4162 info
->irq_requested
= false;
4164 if ( info
->dma_requested
) {
4165 disable_dma(info
->dma_level
);
4166 free_dma(info
->dma_level
);
4167 info
->dma_requested
= false;
4169 mgsl_free_dma_buffers(info
);
4170 mgsl_free_intermediate_rxbuffer_memory(info
);
4171 mgsl_free_intermediate_txbuffer_memory(info
);
4173 if ( info
->io_addr_requested
) {
4174 release_region(info
->io_base
,info
->io_addr_size
);
4175 info
->io_addr_requested
= false;
4177 if ( info
->shared_mem_requested
) {
4178 release_mem_region(info
->phys_memory_base
,0x40000);
4179 info
->shared_mem_requested
= false;
4181 if ( info
->lcr_mem_requested
) {
4182 release_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128);
4183 info
->lcr_mem_requested
= false;
4185 if (info
->memory_base
){
4186 iounmap(info
->memory_base
);
4187 info
->memory_base
= NULL
;
4189 if (info
->lcr_base
){
4190 iounmap(info
->lcr_base
- info
->lcr_offset
);
4191 info
->lcr_base
= NULL
;
4194 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4195 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4196 __FILE__
,__LINE__
,info
->device_name
);
4198 } /* end of mgsl_release_resources() */
4200 /* mgsl_add_device()
4202 * Add the specified device instance data structure to the
4203 * global linked list of devices and increment the device count.
4205 * Arguments: info pointer to device instance data
4206 * Return Value: None
4208 static void mgsl_add_device( struct mgsl_struct
*info
)
4210 info
->next_device
= NULL
;
4211 info
->line
= mgsl_device_count
;
4212 sprintf(info
->device_name
,"ttySL%d",info
->line
);
4214 if (info
->line
< MAX_TOTAL_DEVICES
) {
4215 if (maxframe
[info
->line
])
4216 info
->max_frame_size
= maxframe
[info
->line
];
4218 if (txdmabufs
[info
->line
]) {
4219 info
->num_tx_dma_buffers
= txdmabufs
[info
->line
];
4220 if (info
->num_tx_dma_buffers
< 1)
4221 info
->num_tx_dma_buffers
= 1;
4224 if (txholdbufs
[info
->line
]) {
4225 info
->num_tx_holding_buffers
= txholdbufs
[info
->line
];
4226 if (info
->num_tx_holding_buffers
< 1)
4227 info
->num_tx_holding_buffers
= 1;
4228 else if (info
->num_tx_holding_buffers
> MAX_TX_HOLDING_BUFFERS
)
4229 info
->num_tx_holding_buffers
= MAX_TX_HOLDING_BUFFERS
;
4233 mgsl_device_count
++;
4235 if ( !mgsl_device_list
)
4236 mgsl_device_list
= info
;
4238 struct mgsl_struct
*current_dev
= mgsl_device_list
;
4239 while( current_dev
->next_device
)
4240 current_dev
= current_dev
->next_device
;
4241 current_dev
->next_device
= info
;
4244 if ( info
->max_frame_size
< 4096 )
4245 info
->max_frame_size
= 4096;
4246 else if ( info
->max_frame_size
> 65535 )
4247 info
->max_frame_size
= 65535;
4249 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4250 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4251 info
->hw_version
+ 1, info
->device_name
, info
->io_base
, info
->irq_level
,
4252 info
->phys_memory_base
, info
->phys_lcr_base
,
4253 info
->max_frame_size
);
4255 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4256 info
->device_name
, info
->io_base
, info
->irq_level
, info
->dma_level
,
4257 info
->max_frame_size
);
4260 #if SYNCLINK_GENERIC_HDLC
4264 } /* end of mgsl_add_device() */
4266 static const struct tty_port_operations mgsl_port_ops
= {
4267 .carrier_raised
= carrier_raised
,
4272 /* mgsl_allocate_device()
4274 * Allocate and initialize a device instance structure
4277 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4279 static struct mgsl_struct
* mgsl_allocate_device(void)
4281 struct mgsl_struct
*info
;
4283 info
= kzalloc(sizeof(struct mgsl_struct
),
4287 printk("Error can't allocate device instance data\n");
4289 tty_port_init(&info
->port
);
4290 info
->port
.ops
= &mgsl_port_ops
;
4291 info
->magic
= MGSL_MAGIC
;
4292 INIT_WORK(&info
->task
, mgsl_bh_handler
);
4293 info
->max_frame_size
= 4096;
4294 info
->port
.close_delay
= 5*HZ
/10;
4295 info
->port
.closing_wait
= 30*HZ
;
4296 init_waitqueue_head(&info
->status_event_wait_q
);
4297 init_waitqueue_head(&info
->event_wait_q
);
4298 spin_lock_init(&info
->irq_spinlock
);
4299 spin_lock_init(&info
->netlock
);
4300 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
4301 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
4302 info
->num_tx_dma_buffers
= 1;
4303 info
->num_tx_holding_buffers
= 0;
4308 } /* end of mgsl_allocate_device()*/
4310 static const struct tty_operations mgsl_ops
= {
4312 .close
= mgsl_close
,
4313 .write
= mgsl_write
,
4314 .put_char
= mgsl_put_char
,
4315 .flush_chars
= mgsl_flush_chars
,
4316 .write_room
= mgsl_write_room
,
4317 .chars_in_buffer
= mgsl_chars_in_buffer
,
4318 .flush_buffer
= mgsl_flush_buffer
,
4319 .ioctl
= mgsl_ioctl
,
4320 .throttle
= mgsl_throttle
,
4321 .unthrottle
= mgsl_unthrottle
,
4322 .send_xchar
= mgsl_send_xchar
,
4323 .break_ctl
= mgsl_break
,
4324 .wait_until_sent
= mgsl_wait_until_sent
,
4325 .set_termios
= mgsl_set_termios
,
4327 .start
= mgsl_start
,
4328 .hangup
= mgsl_hangup
,
4329 .tiocmget
= tiocmget
,
4330 .tiocmset
= tiocmset
,
4331 .proc_fops
= &mgsl_proc_fops
,
4335 * perform tty device initialization
4337 static int mgsl_init_tty(void)
4341 serial_driver
= alloc_tty_driver(128);
4345 serial_driver
->owner
= THIS_MODULE
;
4346 serial_driver
->driver_name
= "synclink";
4347 serial_driver
->name
= "ttySL";
4348 serial_driver
->major
= ttymajor
;
4349 serial_driver
->minor_start
= 64;
4350 serial_driver
->type
= TTY_DRIVER_TYPE_SERIAL
;
4351 serial_driver
->subtype
= SERIAL_TYPE_NORMAL
;
4352 serial_driver
->init_termios
= tty_std_termios
;
4353 serial_driver
->init_termios
.c_cflag
=
4354 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
4355 serial_driver
->init_termios
.c_ispeed
= 9600;
4356 serial_driver
->init_termios
.c_ospeed
= 9600;
4357 serial_driver
->flags
= TTY_DRIVER_REAL_RAW
;
4358 tty_set_operations(serial_driver
, &mgsl_ops
);
4359 if ((rc
= tty_register_driver(serial_driver
)) < 0) {
4360 printk("%s(%d):Couldn't register serial driver\n",
4362 put_tty_driver(serial_driver
);
4363 serial_driver
= NULL
;
4367 printk("%s %s, tty major#%d\n",
4368 driver_name
, driver_version
,
4369 serial_driver
->major
);
4373 /* enumerate user specified ISA adapters
4375 static void mgsl_enum_isa_devices(void)
4377 struct mgsl_struct
*info
;
4380 /* Check for user specified ISA devices */
4382 for (i
=0 ;(i
< MAX_ISA_DEVICES
) && io
[i
] && irq
[i
]; i
++){
4383 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4384 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4385 io
[i
], irq
[i
], dma
[i
] );
4387 info
= mgsl_allocate_device();
4389 /* error allocating device instance data */
4390 if ( debug_level
>= DEBUG_LEVEL_ERROR
)
4391 printk( "can't allocate device instance data.\n");
4395 /* Copy user configuration info to device instance data */
4396 info
->io_base
= (unsigned int)io
[i
];
4397 info
->irq_level
= (unsigned int)irq
[i
];
4398 info
->irq_level
= irq_canonicalize(info
->irq_level
);
4399 info
->dma_level
= (unsigned int)dma
[i
];
4400 info
->bus_type
= MGSL_BUS_TYPE_ISA
;
4401 info
->io_addr_size
= 16;
4402 info
->irq_flags
= 0;
4404 mgsl_add_device( info
);
4408 static void synclink_cleanup(void)
4411 struct mgsl_struct
*info
;
4412 struct mgsl_struct
*tmp
;
4414 printk("Unloading %s: %s\n", driver_name
, driver_version
);
4416 if (serial_driver
) {
4417 if ((rc
= tty_unregister_driver(serial_driver
)))
4418 printk("%s(%d) failed to unregister tty driver err=%d\n",
4419 __FILE__
,__LINE__
,rc
);
4420 put_tty_driver(serial_driver
);
4423 info
= mgsl_device_list
;
4425 #if SYNCLINK_GENERIC_HDLC
4428 mgsl_release_resources(info
);
4430 info
= info
->next_device
;
4435 pci_unregister_driver(&synclink_pci_driver
);
4438 static int __init
synclink_init(void)
4442 if (break_on_load
) {
4443 mgsl_get_text_ptr();
4447 printk("%s %s\n", driver_name
, driver_version
);
4449 mgsl_enum_isa_devices();
4450 if ((rc
= pci_register_driver(&synclink_pci_driver
)) < 0)
4451 printk("%s:failed to register PCI driver, error=%d\n",__FILE__
,rc
);
4453 pci_registered
= true;
4455 if ((rc
= mgsl_init_tty()) < 0)
4465 static void __exit
synclink_exit(void)
4470 module_init(synclink_init
);
4471 module_exit(synclink_exit
);
4476 * Issue a USC Receive/Transmit command to the
4477 * Channel Command/Address Register (CCAR).
4481 * The command is encoded in the most significant 5 bits <15..11>
4482 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4483 * and Bits <6..0> must be written as zeros.
4487 * info pointer to device information structure
4488 * Cmd command mask (use symbolic macros)
4494 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
)
4496 /* output command to CCAR in bits <15..11> */
4497 /* preserve bits <10..7>, bits <6..0> must be zero */
4499 outw( Cmd
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4501 /* Read to flush write to CCAR */
4502 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4503 inw( info
->io_base
+ CCAR
);
4505 } /* end of usc_RTCmd() */
4510 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4514 * info pointer to device information structure
4515 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4521 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
)
4523 /* write command mask to DCAR */
4524 outw( Cmd
+ info
->mbre_bit
, info
->io_base
);
4526 /* Read to flush write to DCAR */
4527 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4528 inw( info
->io_base
);
4530 } /* end of usc_DmaCmd() */
4535 * Write a 16-bit value to a USC DMA register
4539 * info pointer to device info structure
4540 * RegAddr register address (number) for write
4541 * RegValue 16-bit value to write to register
4548 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4550 /* Note: The DCAR is located at the adapter base address */
4551 /* Note: must preserve state of BIT8 in DCAR */
4553 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4554 outw( RegValue
, info
->io_base
);
4556 /* Read to flush write to DCAR */
4557 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4558 inw( info
->io_base
);
4560 } /* end of usc_OutDmaReg() */
4565 * Read a 16-bit value from a DMA register
4569 * info pointer to device info structure
4570 * RegAddr register address (number) to read from
4574 * The 16-bit value read from register
4577 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 RegAddr
)
4579 /* Note: The DCAR is located at the adapter base address */
4580 /* Note: must preserve state of BIT8 in DCAR */
4582 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4583 return inw( info
->io_base
);
4585 } /* end of usc_InDmaReg() */
4591 * Write a 16-bit value to a USC serial channel register
4595 * info pointer to device info structure
4596 * RegAddr register address (number) to write to
4597 * RegValue 16-bit value to write to register
4604 static void usc_OutReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4606 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4607 outw( RegValue
, info
->io_base
+ CCAR
);
4609 /* Read to flush write to CCAR */
4610 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4611 inw( info
->io_base
+ CCAR
);
4613 } /* end of usc_OutReg() */
4618 * Reads a 16-bit value from a USC serial channel register
4622 * info pointer to device extension
4623 * RegAddr register address (number) to read from
4627 * 16-bit value read from register
4629 static u16
usc_InReg( struct mgsl_struct
*info
, u16 RegAddr
)
4631 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4632 return inw( info
->io_base
+ CCAR
);
4634 } /* end of usc_InReg() */
4636 /* usc_set_sdlc_mode()
4638 * Set up the adapter for SDLC DMA communications.
4640 * Arguments: info pointer to device instance data
4641 * Return Value: NONE
4643 static void usc_set_sdlc_mode( struct mgsl_struct
*info
)
4649 * determine if the IUSC on the adapter is pre-SL1660. If
4650 * not, take advantage of the UnderWait feature of more
4651 * modern chips. If an underrun occurs and this bit is set,
4652 * the transmitter will idle the programmed idle pattern
4653 * until the driver has time to service the underrun. Otherwise,
4654 * the dma controller may get the cycles previously requested
4655 * and begin transmitting queued tx data.
4657 usc_OutReg(info
,TMCR
,0x1f);
4658 RegValue
=usc_InReg(info
,TMDR
);
4659 PreSL1660
= (RegValue
== IUSC_PRE_SL1660
);
4661 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
4664 ** Channel Mode Register (CMR)
4666 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4667 ** <13> 0 0 = Transmit Disabled (initially)
4668 ** <12> 0 1 = Consecutive Idles share common 0
4669 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4670 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4671 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4673 ** 1000 1110 0000 0110 = 0x8e06
4677 /*--------------------------------------------------
4678 * ignore user options for UnderRun Actions and
4680 *--------------------------------------------------*/
4684 /* Channel mode Register (CMR)
4686 * <15..14> 00 Tx Sub modes, Underrun Action
4687 * <13> 0 1 = Send Preamble before opening flag
4688 * <12> 0 1 = Consecutive Idles share common 0
4689 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4690 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4691 * <3..0> 0110 Receiver mode = HDLC/SDLC
4693 * 0000 0110 0000 0110 = 0x0606
4695 if (info
->params
.mode
== MGSL_MODE_RAW
) {
4696 RegValue
= 0x0001; /* Set Receive mode = external sync */
4698 usc_OutReg( info
, IOCR
, /* Set IOCR DCD is RxSync Detect Input */
4699 (unsigned short)((usc_InReg(info
, IOCR
) & ~(BIT13
|BIT12
)) | BIT12
));
4707 if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_ABORT15
)
4709 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_FLAG
)
4711 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_CRC
)
4712 RegValue
|= BIT15
+ BIT14
;
4715 if ( info
->params
.preamble
!= HDLC_PREAMBLE_PATTERN_NONE
)
4719 if ( info
->params
.mode
== MGSL_MODE_HDLC
&&
4720 (info
->params
.flags
& HDLC_FLAG_SHARE_ZERO
) )
4723 if ( info
->params
.addr_filter
!= 0xff )
4725 /* set up receive address filtering */
4726 usc_OutReg( info
, RSR
, info
->params
.addr_filter
);
4730 usc_OutReg( info
, CMR
, RegValue
);
4731 info
->cmr_value
= RegValue
;
4733 /* Receiver mode Register (RMR)
4735 * <15..13> 000 encoding
4736 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4737 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4738 * <9> 0 1 = Include Receive chars in CRC
4739 * <8> 1 1 = Use Abort/PE bit as abort indicator
4740 * <7..6> 00 Even parity
4741 * <5> 0 parity disabled
4742 * <4..2> 000 Receive Char Length = 8 bits
4743 * <1..0> 00 Disable Receiver
4745 * 0000 0101 0000 0000 = 0x0500
4750 switch ( info
->params
.encoding
) {
4751 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4752 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4753 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
+ BIT13
; break;
4754 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4755 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
+ BIT13
; break;
4756 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
; break;
4757 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
+ BIT13
; break;
4760 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4762 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4763 RegValue
|= ( BIT12
| BIT10
| BIT9
);
4765 usc_OutReg( info
, RMR
, RegValue
);
4767 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4768 /* When an opening flag of an SDLC frame is recognized the */
4769 /* Receive Character count (RCC) is loaded with the value in */
4770 /* RCLR. The RCC is decremented for each received byte. The */
4771 /* value of RCC is stored after the closing flag of the frame */
4772 /* allowing the frame size to be computed. */
4774 usc_OutReg( info
, RCLR
, RCLRVALUE
);
4776 usc_RCmd( info
, RCmd_SelectRicrdma_level
);
4778 /* Receive Interrupt Control Register (RICR)
4780 * <15..8> ? RxFIFO DMA Request Level
4781 * <7> 0 Exited Hunt IA (Interrupt Arm)
4782 * <6> 0 Idle Received IA
4783 * <5> 0 Break/Abort IA
4785 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4787 * <1> 1 Rx Overrun IA
4788 * <0> 0 Select TC0 value for readback
4790 * 0000 0000 0000 1000 = 0x000a
4793 /* Carry over the Exit Hunt and Idle Received bits */
4794 /* in case they have been armed by usc_ArmEvents. */
4796 RegValue
= usc_InReg( info
, RICR
) & 0xc0;
4798 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4799 usc_OutReg( info
, RICR
, (u16
)(0x030a | RegValue
) );
4801 usc_OutReg( info
, RICR
, (u16
)(0x140a | RegValue
) );
4803 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4805 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
4806 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
4808 /* Transmit mode Register (TMR)
4810 * <15..13> 000 encoding
4811 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4812 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4813 * <9> 0 1 = Tx CRC Enabled
4814 * <8> 0 1 = Append CRC to end of transmit frame
4815 * <7..6> 00 Transmit parity Even
4816 * <5> 0 Transmit parity Disabled
4817 * <4..2> 000 Tx Char Length = 8 bits
4818 * <1..0> 00 Disable Transmitter
4820 * 0000 0100 0000 0000 = 0x0400
4825 switch ( info
->params
.encoding
) {
4826 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4827 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4828 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
+ BIT13
; break;
4829 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4830 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
+ BIT13
; break;
4831 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
; break;
4832 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
+ BIT13
; break;
4835 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4836 RegValue
|= BIT9
+ BIT8
;
4837 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4838 RegValue
|= ( BIT12
| BIT10
| BIT9
| BIT8
);
4840 usc_OutReg( info
, TMR
, RegValue
);
4842 usc_set_txidle( info
);
4845 usc_TCmd( info
, TCmd_SelectTicrdma_level
);
4847 /* Transmit Interrupt Control Register (TICR)
4849 * <15..8> ? Transmit FIFO DMA Level
4850 * <7> 0 Present IA (Interrupt Arm)
4851 * <6> 0 Idle Sent IA
4852 * <5> 1 Abort Sent IA
4853 * <4> 1 EOF/EOM Sent IA
4855 * <2> 1 1 = Wait for SW Trigger to Start Frame
4856 * <1> 1 Tx Underrun IA
4857 * <0> 0 TC0 constant on read back
4859 * 0000 0000 0011 0110 = 0x0036
4862 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4863 usc_OutReg( info
, TICR
, 0x0736 );
4865 usc_OutReg( info
, TICR
, 0x1436 );
4867 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
4868 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
4871 ** Transmit Command/Status Register (TCSR)
4873 ** <15..12> 0000 TCmd
4874 ** <11> 0/1 UnderWait
4875 ** <10..08> 000 TxIdle
4879 ** <4> x EOF/EOM Sent
4885 ** 0000 0000 0000 0000 = 0x0000
4887 info
->tcsr_value
= 0;
4890 info
->tcsr_value
|= TCSR_UNDERWAIT
;
4892 usc_OutReg( info
, TCSR
, info
->tcsr_value
);
4897 if ( info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4898 RegValue
|= 0x0003; /* RxCLK from DPLL */
4899 else if ( info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
4900 RegValue
|= 0x0004; /* RxCLK from BRG0 */
4901 else if ( info
->params
.flags
& HDLC_FLAG_RXC_TXCPIN
)
4902 RegValue
|= 0x0006; /* RxCLK from TXC Input */
4904 RegValue
|= 0x0007; /* RxCLK from Port1 */
4906 if ( info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
4907 RegValue
|= 0x0018; /* TxCLK from DPLL */
4908 else if ( info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4909 RegValue
|= 0x0020; /* TxCLK from BRG0 */
4910 else if ( info
->params
.flags
& HDLC_FLAG_TXC_RXCPIN
)
4911 RegValue
|= 0x0038; /* RxCLK from TXC Input */
4913 RegValue
|= 0x0030; /* TxCLK from Port0 */
4915 usc_OutReg( info
, CMCR
, RegValue
);
4918 /* Hardware Configuration Register (HCR)
4920 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4921 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4922 * <12> 0 CVOK:0=report code violation in biphase
4923 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4924 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4925 * <7..6> 00 reserved
4926 * <5> 0 BRG1 mode:0=continuous,1=single cycle
4928 * <3..2> 00 reserved
4929 * <1> 0 BRG0 mode:0=continuous,1=single cycle
4935 if ( info
->params
.flags
& (HDLC_FLAG_RXC_DPLL
+ HDLC_FLAG_TXC_DPLL
) ) {
4940 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
4941 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
4943 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4944 XtalSpeed
= 11059200;
4946 XtalSpeed
= 14745600;
4948 if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV16
) {
4952 else if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV8
) {
4959 /* Tc = (Xtal/Speed) - 1 */
4960 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
4961 /* then rounding up gives a more precise time constant. Instead */
4962 /* of rounding up and then subtracting 1 we just don't subtract */
4963 /* the one in this case. */
4965 /*--------------------------------------------------
4966 * ejz: for DPLL mode, application should use the
4967 * same clock speed as the partner system, even
4968 * though clocking is derived from the input RxData.
4969 * In case the user uses a 0 for the clock speed,
4970 * default to 0xffffffff and don't try to divide by
4972 *--------------------------------------------------*/
4973 if ( info
->params
.clock_speed
)
4975 Tc
= (u16
)((XtalSpeed
/DpllDivisor
)/info
->params
.clock_speed
);
4976 if ( !((((XtalSpeed
/DpllDivisor
) % info
->params
.clock_speed
) * 2)
4977 / info
->params
.clock_speed
) )
4984 /* Write 16-bit Time Constant for BRG1 */
4985 usc_OutReg( info
, TC1R
, Tc
);
4987 RegValue
|= BIT4
; /* enable BRG1 */
4989 switch ( info
->params
.encoding
) {
4990 case HDLC_ENCODING_NRZ
:
4991 case HDLC_ENCODING_NRZB
:
4992 case HDLC_ENCODING_NRZI_MARK
:
4993 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT8
; break;
4994 case HDLC_ENCODING_BIPHASE_MARK
:
4995 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT9
; break;
4996 case HDLC_ENCODING_BIPHASE_LEVEL
:
4997 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT9
+ BIT8
; break;
5001 usc_OutReg( info
, HCR
, RegValue
);
5004 /* Channel Control/status Register (CCSR)
5006 * <15> X RCC FIFO Overflow status (RO)
5007 * <14> X RCC FIFO Not Empty status (RO)
5008 * <13> 0 1 = Clear RCC FIFO (WO)
5009 * <12> X DPLL Sync (RW)
5010 * <11> X DPLL 2 Missed Clocks status (RO)
5011 * <10> X DPLL 1 Missed Clock status (RO)
5012 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5013 * <7> X SDLC Loop On status (RO)
5014 * <6> X SDLC Loop Send status (RO)
5015 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5016 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5017 * <1..0> 00 reserved
5019 * 0000 0000 0010 0000 = 0x0020
5022 usc_OutReg( info
, CCSR
, 0x1020 );
5025 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
) {
5026 usc_OutReg( info
, SICR
,
5027 (u16
)(usc_InReg(info
,SICR
) | SICR_CTS_INACTIVE
) );
5031 /* enable Master Interrupt Enable bit (MIE) */
5032 usc_EnableMasterIrqBit( info
);
5034 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
+ RECEIVE_DATA
+
5035 TRANSMIT_STATUS
+ TRANSMIT_DATA
+ MISC
);
5037 /* arm RCC underflow interrupt */
5038 usc_OutReg(info
, SICR
, (u16
)(usc_InReg(info
,SICR
) | BIT3
));
5039 usc_EnableInterrupts(info
, MISC
);
5042 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5043 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5044 info
->mbre_bit
= BIT8
;
5045 outw( BIT8
, info
->io_base
); /* set Master Bus Enable (DCAR) */
5047 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
5048 /* Enable DMAEN (Port 7, Bit 14) */
5049 /* This connects the DMA request signal to the ISA bus */
5050 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) & ~BIT14
));
5053 /* DMA Control Register (DCR)
5055 * <15..14> 10 Priority mode = Alternating Tx/Rx
5056 * 01 Rx has priority
5057 * 00 Tx has priority
5059 * <13> 1 Enable Priority Preempt per DCR<15..14>
5060 * (WARNING DCR<11..10> must be 00 when this is 1)
5061 * 0 Choose activate channel per DCR<11..10>
5063 * <12> 0 Little Endian for Array/List
5064 * <11..10> 00 Both Channels can use each bus grant
5065 * <9..6> 0000 reserved
5066 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5067 * <4> 0 1 = drive D/C and S/D pins
5068 * <3> 1 1 = Add one wait state to all DMA cycles.
5069 * <2> 0 1 = Strobe /UAS on every transfer.
5070 * <1..0> 11 Addr incrementing only affects LS24 bits
5072 * 0110 0000 0000 1011 = 0x600b
5075 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5076 /* PCI adapter does not need DMA wait state */
5077 usc_OutDmaReg( info
, DCR
, 0xa00b );
5080 usc_OutDmaReg( info
, DCR
, 0x800b );
5083 /* Receive DMA mode Register (RDMR)
5085 * <15..14> 11 DMA mode = Linked List Buffer mode
5086 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5087 * <12> 1 Clear count of List Entry after fetching
5088 * <11..10> 00 Address mode = Increment
5089 * <9> 1 Terminate Buffer on RxBound
5090 * <8> 0 Bus Width = 16bits
5091 * <7..0> ? status Bits (write as 0s)
5093 * 1111 0010 0000 0000 = 0xf200
5096 usc_OutDmaReg( info
, RDMR
, 0xf200 );
5099 /* Transmit DMA mode Register (TDMR)
5101 * <15..14> 11 DMA mode = Linked List Buffer mode
5102 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5103 * <12> 1 Clear count of List Entry after fetching
5104 * <11..10> 00 Address mode = Increment
5105 * <9> 1 Terminate Buffer on end of frame
5106 * <8> 0 Bus Width = 16bits
5107 * <7..0> ? status Bits (Read Only so write as 0)
5109 * 1111 0010 0000 0000 = 0xf200
5112 usc_OutDmaReg( info
, TDMR
, 0xf200 );
5115 /* DMA Interrupt Control Register (DICR)
5117 * <15> 1 DMA Interrupt Enable
5118 * <14> 0 1 = Disable IEO from USC
5119 * <13> 0 1 = Don't provide vector during IntAck
5120 * <12> 1 1 = Include status in Vector
5121 * <10..2> 0 reserved, Must be 0s
5122 * <1> 0 1 = Rx DMA Interrupt Enabled
5123 * <0> 0 1 = Tx DMA Interrupt Enabled
5125 * 1001 0000 0000 0000 = 0x9000
5128 usc_OutDmaReg( info
, DICR
, 0x9000 );
5130 usc_InDmaReg( info
, RDMR
); /* clear pending receive DMA IRQ bits */
5131 usc_InDmaReg( info
, TDMR
); /* clear pending transmit DMA IRQ bits */
5132 usc_OutDmaReg( info
, CDIR
, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5134 /* Channel Control Register (CCR)
5136 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5137 * <13> 0 Trigger Tx on SW Command Disabled
5138 * <12> 0 Flag Preamble Disabled
5139 * <11..10> 00 Preamble Length
5140 * <9..8> 00 Preamble Pattern
5141 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5142 * <5> 0 Trigger Rx on SW Command Disabled
5145 * 1000 0000 1000 0000 = 0x8080
5150 switch ( info
->params
.preamble_length
) {
5151 case HDLC_PREAMBLE_LENGTH_16BITS
: RegValue
|= BIT10
; break;
5152 case HDLC_PREAMBLE_LENGTH_32BITS
: RegValue
|= BIT11
; break;
5153 case HDLC_PREAMBLE_LENGTH_64BITS
: RegValue
|= BIT11
+ BIT10
; break;
5156 switch ( info
->params
.preamble
) {
5157 case HDLC_PREAMBLE_PATTERN_FLAGS
: RegValue
|= BIT8
+ BIT12
; break;
5158 case HDLC_PREAMBLE_PATTERN_ONES
: RegValue
|= BIT8
; break;
5159 case HDLC_PREAMBLE_PATTERN_10
: RegValue
|= BIT9
; break;
5160 case HDLC_PREAMBLE_PATTERN_01
: RegValue
|= BIT9
+ BIT8
; break;
5163 usc_OutReg( info
, CCR
, RegValue
);
5167 * Burst/Dwell Control Register
5169 * <15..8> 0x20 Maximum number of transfers per bus grant
5170 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5173 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5174 /* don't limit bus occupancy on PCI adapter */
5175 usc_OutDmaReg( info
, BDCR
, 0x0000 );
5178 usc_OutDmaReg( info
, BDCR
, 0x2000 );
5180 usc_stop_transmitter(info
);
5181 usc_stop_receiver(info
);
5183 } /* end of usc_set_sdlc_mode() */
5185 /* usc_enable_loopback()
5187 * Set the 16C32 for internal loopback mode.
5188 * The TxCLK and RxCLK signals are generated from the BRG0 and
5189 * the TxD is looped back to the RxD internally.
5191 * Arguments: info pointer to device instance data
5192 * enable 1 = enable loopback, 0 = disable
5193 * Return Value: None
5195 static void usc_enable_loopback(struct mgsl_struct
*info
, int enable
)
5198 /* blank external TXD output */
5199 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) | (BIT7
+BIT6
));
5201 /* Clock mode Control Register (CMCR)
5203 * <15..14> 00 counter 1 Disabled
5204 * <13..12> 00 counter 0 Disabled
5205 * <11..10> 11 BRG1 Input is TxC Pin
5206 * <9..8> 11 BRG0 Input is TxC Pin
5207 * <7..6> 01 DPLL Input is BRG1 Output
5208 * <5..3> 100 TxCLK comes from BRG0
5209 * <2..0> 100 RxCLK comes from BRG0
5211 * 0000 1111 0110 0100 = 0x0f64
5214 usc_OutReg( info
, CMCR
, 0x0f64 );
5216 /* Write 16-bit Time Constant for BRG0 */
5217 /* use clock speed if available, otherwise use 8 for diagnostics */
5218 if (info
->params
.clock_speed
) {
5219 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5220 usc_OutReg(info
, TC0R
, (u16
)((11059200/info
->params
.clock_speed
)-1));
5222 usc_OutReg(info
, TC0R
, (u16
)((14745600/info
->params
.clock_speed
)-1));
5224 usc_OutReg(info
, TC0R
, (u16
)8);
5226 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5227 mode = Continuous Set Bit 0 to enable BRG0. */
5228 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5230 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5231 usc_OutReg(info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004));
5233 /* set Internal Data loopback mode */
5234 info
->loopback_bits
= 0x300;
5235 outw( 0x0300, info
->io_base
+ CCAR
);
5237 /* enable external TXD output */
5238 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) & ~(BIT7
+BIT6
));
5240 /* clear Internal Data loopback mode */
5241 info
->loopback_bits
= 0;
5242 outw( 0,info
->io_base
+ CCAR
);
5245 } /* end of usc_enable_loopback() */
5247 /* usc_enable_aux_clock()
5249 * Enabled the AUX clock output at the specified frequency.
5253 * info pointer to device extension
5254 * data_rate data rate of clock in bits per second
5255 * A data rate of 0 disables the AUX clock.
5257 * Return Value: None
5259 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 data_rate
)
5265 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5266 XtalSpeed
= 11059200;
5268 XtalSpeed
= 14745600;
5271 /* Tc = (Xtal/Speed) - 1 */
5272 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5273 /* then rounding up gives a more precise time constant. Instead */
5274 /* of rounding up and then subtracting 1 we just don't subtract */
5275 /* the one in this case. */
5278 Tc
= (u16
)(XtalSpeed
/data_rate
);
5279 if ( !(((XtalSpeed
% data_rate
) * 2) / data_rate
) )
5282 /* Write 16-bit Time Constant for BRG0 */
5283 usc_OutReg( info
, TC0R
, Tc
);
5286 * Hardware Configuration Register (HCR)
5287 * Clear Bit 1, BRG0 mode = Continuous
5288 * Set Bit 0 to enable BRG0.
5291 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5293 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5294 usc_OutReg( info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
5296 /* data rate == 0 so turn off BRG0 */
5297 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
5300 } /* end of usc_enable_aux_clock() */
5304 * usc_process_rxoverrun_sync()
5306 * This function processes a receive overrun by resetting the
5307 * receive DMA buffers and issuing a Purge Rx FIFO command
5308 * to allow the receiver to continue receiving.
5312 * info pointer to device extension
5314 * Return Value: None
5316 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
)
5320 int frame_start_index
;
5321 bool start_of_frame_found
= false;
5322 bool end_of_frame_found
= false;
5323 bool reprogram_dma
= false;
5325 DMABUFFERENTRY
*buffer_list
= info
->rx_buffer_list
;
5328 usc_DmaCmd( info
, DmaCmd_PauseRxChannel
);
5329 usc_RCmd( info
, RCmd_EnterHuntmode
);
5330 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5332 /* CurrentRxBuffer points to the 1st buffer of the next */
5333 /* possibly available receive frame. */
5335 frame_start_index
= start_index
= end_index
= info
->current_rx_buffer
;
5337 /* Search for an unfinished string of buffers. This means */
5338 /* that a receive frame started (at least one buffer with */
5339 /* count set to zero) but there is no terminiting buffer */
5340 /* (status set to non-zero). */
5342 while( !buffer_list
[end_index
].count
)
5344 /* Count field has been reset to zero by 16C32. */
5345 /* This buffer is currently in use. */
5347 if ( !start_of_frame_found
)
5349 start_of_frame_found
= true;
5350 frame_start_index
= end_index
;
5351 end_of_frame_found
= false;
5354 if ( buffer_list
[end_index
].status
)
5356 /* Status field has been set by 16C32. */
5357 /* This is the last buffer of a received frame. */
5359 /* We want to leave the buffers for this frame intact. */
5360 /* Move on to next possible frame. */
5362 start_of_frame_found
= false;
5363 end_of_frame_found
= true;
5366 /* advance to next buffer entry in linked list */
5368 if ( end_index
== info
->rx_buffer_count
)
5371 if ( start_index
== end_index
)
5373 /* The entire list has been searched with all Counts == 0 and */
5374 /* all Status == 0. The receive buffers are */
5375 /* completely screwed, reset all receive buffers! */
5376 mgsl_reset_rx_dma_buffers( info
);
5377 frame_start_index
= 0;
5378 start_of_frame_found
= false;
5379 reprogram_dma
= true;
5384 if ( start_of_frame_found
&& !end_of_frame_found
)
5386 /* There is an unfinished string of receive DMA buffers */
5387 /* as a result of the receiver overrun. */
5389 /* Reset the buffers for the unfinished frame */
5390 /* and reprogram the receive DMA controller to start */
5391 /* at the 1st buffer of unfinished frame. */
5393 start_index
= frame_start_index
;
5397 *((unsigned long *)&(info
->rx_buffer_list
[start_index
++].count
)) = DMABUFFERSIZE
;
5399 /* Adjust index for wrap around. */
5400 if ( start_index
== info
->rx_buffer_count
)
5403 } while( start_index
!= end_index
);
5405 reprogram_dma
= true;
5408 if ( reprogram_dma
)
5410 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
5411 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5412 usc_UnlatchRxstatusBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5414 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5416 /* This empties the receive FIFO and loads the RCC with RCLR */
5417 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5419 /* program 16C32 with physical address of 1st DMA buffer entry */
5420 phys_addr
= info
->rx_buffer_list
[frame_start_index
].phys_entry
;
5421 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5422 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5424 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5425 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5426 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5428 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5429 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5431 usc_OutDmaReg( info
, RDIAR
, BIT3
+ BIT2
);
5432 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5433 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5434 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5435 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5437 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5441 /* This empties the receive FIFO and loads the RCC with RCLR */
5442 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5443 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5446 } /* end of usc_process_rxoverrun_sync() */
5448 /* usc_stop_receiver()
5450 * Disable USC receiver
5452 * Arguments: info pointer to device instance data
5453 * Return Value: None
5455 static void usc_stop_receiver( struct mgsl_struct
*info
)
5457 if (debug_level
>= DEBUG_LEVEL_ISR
)
5458 printk("%s(%d):usc_stop_receiver(%s)\n",
5459 __FILE__
,__LINE__
, info
->device_name
);
5461 /* Disable receive DMA channel. */
5462 /* This also disables receive DMA channel interrupts */
5463 usc_DmaCmd( info
, DmaCmd_ResetRxChannel
);
5465 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5466 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5467 usc_DisableInterrupts( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5469 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5471 /* This empties the receive FIFO and loads the RCC with RCLR */
5472 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5473 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5475 info
->rx_enabled
= false;
5476 info
->rx_overflow
= false;
5477 info
->rx_rcc_underrun
= false;
5479 } /* end of stop_receiver() */
5481 /* usc_start_receiver()
5483 * Enable the USC receiver
5485 * Arguments: info pointer to device instance data
5486 * Return Value: None
5488 static void usc_start_receiver( struct mgsl_struct
*info
)
5492 if (debug_level
>= DEBUG_LEVEL_ISR
)
5493 printk("%s(%d):usc_start_receiver(%s)\n",
5494 __FILE__
,__LINE__
, info
->device_name
);
5496 mgsl_reset_rx_dma_buffers( info
);
5497 usc_stop_receiver( info
);
5499 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5500 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5502 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
5503 info
->params
.mode
== MGSL_MODE_RAW
) {
5504 /* DMA mode Transfers */
5505 /* Program the DMA controller. */
5506 /* Enable the DMA controller end of buffer interrupt. */
5508 /* program 16C32 with physical address of 1st DMA buffer entry */
5509 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
5510 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5511 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5513 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5514 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5515 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5517 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5518 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5520 usc_OutDmaReg( info
, RDIAR
, BIT3
+ BIT2
);
5521 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5522 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5523 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5524 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5526 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5528 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
5529 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5530 usc_EnableInterrupts(info
, RECEIVE_DATA
);
5532 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5533 usc_RCmd( info
, RCmd_EnterHuntmode
);
5535 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5538 usc_OutReg( info
, CCSR
, 0x1020 );
5540 info
->rx_enabled
= true;
5542 } /* end of usc_start_receiver() */
5544 /* usc_start_transmitter()
5546 * Enable the USC transmitter and send a transmit frame if
5547 * one is loaded in the DMA buffers.
5549 * Arguments: info pointer to device instance data
5550 * Return Value: None
5552 static void usc_start_transmitter( struct mgsl_struct
*info
)
5555 unsigned int FrameSize
;
5557 if (debug_level
>= DEBUG_LEVEL_ISR
)
5558 printk("%s(%d):usc_start_transmitter(%s)\n",
5559 __FILE__
,__LINE__
, info
->device_name
);
5561 if ( info
->xmit_cnt
) {
5563 /* If auto RTS enabled and RTS is inactive, then assert */
5564 /* RTS and set a flag indicating that the driver should */
5565 /* negate RTS when the transmission completes. */
5567 info
->drop_rts_on_tx_done
= false;
5569 if ( info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
5570 usc_get_serial_signals( info
);
5571 if ( !(info
->serial_signals
& SerialSignal_RTS
) ) {
5572 info
->serial_signals
|= SerialSignal_RTS
;
5573 usc_set_serial_signals( info
);
5574 info
->drop_rts_on_tx_done
= true;
5579 if ( info
->params
.mode
== MGSL_MODE_ASYNC
) {
5580 if ( !info
->tx_active
) {
5581 usc_UnlatchTxstatusBits(info
, TXSTATUS_ALL
);
5582 usc_ClearIrqPendingBits(info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5583 usc_EnableInterrupts(info
, TRANSMIT_DATA
);
5584 usc_load_txfifo(info
);
5587 /* Disable transmit DMA controller while programming. */
5588 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5590 /* Transmit DMA buffer is loaded, so program USC */
5591 /* to send the frame contained in the buffers. */
5593 FrameSize
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
;
5595 /* if operating in Raw sync mode, reset the rcc component
5596 * of the tx dma buffer entry, otherwise, the serial controller
5597 * will send a closing sync char after this count.
5599 if ( info
->params
.mode
== MGSL_MODE_RAW
)
5600 info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
= 0;
5602 /* Program the Transmit Character Length Register (TCLR) */
5603 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5604 usc_OutReg( info
, TCLR
, (u16
)FrameSize
);
5606 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5608 /* Program the address of the 1st DMA Buffer Entry in linked list */
5609 phys_addr
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].phys_entry
;
5610 usc_OutDmaReg( info
, NTARL
, (u16
)phys_addr
);
5611 usc_OutDmaReg( info
, NTARU
, (u16
)(phys_addr
>> 16) );
5613 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5614 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
5615 usc_EnableInterrupts( info
, TRANSMIT_STATUS
);
5617 if ( info
->params
.mode
== MGSL_MODE_RAW
&&
5618 info
->num_tx_dma_buffers
> 1 ) {
5619 /* When running external sync mode, attempt to 'stream' transmit */
5620 /* by filling tx dma buffers as they become available. To do this */
5621 /* we need to enable Tx DMA EOB Status interrupts : */
5623 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5624 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5626 usc_OutDmaReg( info
, TDIAR
, BIT2
|BIT3
);
5627 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT0
) );
5630 /* Initialize Transmit DMA Channel */
5631 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
5633 usc_TCmd( info
, TCmd_SendFrame
);
5635 mod_timer(&info
->tx_timer
, jiffies
+
5636 msecs_to_jiffies(5000));
5638 info
->tx_active
= true;
5641 if ( !info
->tx_enabled
) {
5642 info
->tx_enabled
= true;
5643 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
5644 usc_EnableTransmitter(info
,ENABLE_AUTO_CTS
);
5646 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
5649 } /* end of usc_start_transmitter() */
5651 /* usc_stop_transmitter()
5653 * Stops the transmitter and DMA
5655 * Arguments: info pointer to device isntance data
5656 * Return Value: None
5658 static void usc_stop_transmitter( struct mgsl_struct
*info
)
5660 if (debug_level
>= DEBUG_LEVEL_ISR
)
5661 printk("%s(%d):usc_stop_transmitter(%s)\n",
5662 __FILE__
,__LINE__
, info
->device_name
);
5664 del_timer(&info
->tx_timer
);
5666 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5667 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5668 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5670 usc_EnableTransmitter(info
,DISABLE_UNCONDITIONAL
);
5671 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5672 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5674 info
->tx_enabled
= false;
5675 info
->tx_active
= false;
5677 } /* end of usc_stop_transmitter() */
5679 /* usc_load_txfifo()
5681 * Fill the transmit FIFO until the FIFO is full or
5682 * there is no more data to load.
5684 * Arguments: info pointer to device extension (instance data)
5685 * Return Value: None
5687 static void usc_load_txfifo( struct mgsl_struct
*info
)
5692 if ( !info
->xmit_cnt
&& !info
->x_char
)
5695 /* Select transmit FIFO status readback in TICR */
5696 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
5698 /* load the Transmit FIFO until FIFOs full or all data sent */
5700 while( (Fifocount
= usc_InReg(info
, TICR
) >> 8) && info
->xmit_cnt
) {
5701 /* there is more space in the transmit FIFO and */
5702 /* there is more data in transmit buffer */
5704 if ( (info
->xmit_cnt
> 1) && (Fifocount
> 1) && !info
->x_char
) {
5705 /* write a 16-bit word from transmit buffer to 16C32 */
5707 TwoBytes
[0] = info
->xmit_buf
[info
->xmit_tail
++];
5708 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5709 TwoBytes
[1] = info
->xmit_buf
[info
->xmit_tail
++];
5710 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5712 outw( *((u16
*)TwoBytes
), info
->io_base
+ DATAREG
);
5714 info
->xmit_cnt
-= 2;
5715 info
->icount
.tx
+= 2;
5717 /* only 1 byte left to transmit or 1 FIFO slot left */
5719 outw( (inw( info
->io_base
+ CCAR
) & 0x0780) | (TDR
+LSBONLY
),
5720 info
->io_base
+ CCAR
);
5723 /* transmit pending high priority char */
5724 outw( info
->x_char
,info
->io_base
+ CCAR
);
5727 outw( info
->xmit_buf
[info
->xmit_tail
++],info
->io_base
+ CCAR
);
5728 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5735 } /* end of usc_load_txfifo() */
5739 * Reset the adapter to a known state and prepare it for further use.
5741 * Arguments: info pointer to device instance data
5742 * Return Value: None
5744 static void usc_reset( struct mgsl_struct
*info
)
5746 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5750 /* Set BIT30 of Misc Control Register */
5751 /* (Local Control Register 0x50) to force reset of USC. */
5753 volatile u32
*MiscCtrl
= (u32
*)(info
->lcr_base
+ 0x50);
5754 u32
*LCR0BRDR
= (u32
*)(info
->lcr_base
+ 0x28);
5756 info
->misc_ctrl_value
|= BIT30
;
5757 *MiscCtrl
= info
->misc_ctrl_value
;
5760 * Force at least 170ns delay before clearing
5761 * reset bit. Each read from LCR takes at least
5762 * 30ns so 10 times for 300ns to be safe.
5765 readval
= *MiscCtrl
;
5767 info
->misc_ctrl_value
&= ~BIT30
;
5768 *MiscCtrl
= info
->misc_ctrl_value
;
5770 *LCR0BRDR
= BUS_DESCRIPTOR(
5771 1, // Write Strobe Hold (0-3)
5772 2, // Write Strobe Delay (0-3)
5773 2, // Read Strobe Delay (0-3)
5774 0, // NWDD (Write data-data) (0-3)
5775 4, // NWAD (Write Addr-data) (0-31)
5776 0, // NXDA (Read/Write Data-Addr) (0-3)
5777 0, // NRDD (Read Data-Data) (0-3)
5778 5 // NRAD (Read Addr-Data) (0-31)
5782 outb( 0,info
->io_base
+ 8 );
5786 info
->loopback_bits
= 0;
5787 info
->usc_idle_mode
= 0;
5790 * Program the Bus Configuration Register (BCR)
5792 * <15> 0 Don't use separate address
5793 * <14..6> 0 reserved
5794 * <5..4> 00 IAckmode = Default, don't care
5795 * <3> 1 Bus Request Totem Pole output
5796 * <2> 1 Use 16 Bit data bus
5797 * <1> 0 IRQ Totem Pole output
5798 * <0> 0 Don't Shift Right Addr
5800 * 0000 0000 0000 1100 = 0x000c
5802 * By writing to io_base + SDPIN the Wait/Ack pin is
5803 * programmed to work as a Wait pin.
5806 outw( 0x000c,info
->io_base
+ SDPIN
);
5809 outw( 0,info
->io_base
);
5810 outw( 0,info
->io_base
+ CCAR
);
5812 /* select little endian byte ordering */
5813 usc_RTCmd( info
, RTCmd_SelectLittleEndian
);
5816 /* Port Control Register (PCR)
5818 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5819 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5820 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5821 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5822 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5823 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5824 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5825 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5827 * 1111 0000 1111 0101 = 0xf0f5
5830 usc_OutReg( info
, PCR
, 0xf0f5 );
5834 * Input/Output Control Register
5836 * <15..14> 00 CTS is active low input
5837 * <13..12> 00 DCD is active low input
5838 * <11..10> 00 TxREQ pin is input (DSR)
5839 * <9..8> 00 RxREQ pin is input (RI)
5840 * <7..6> 00 TxD is output (Transmit Data)
5841 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5842 * <2..0> 100 RxC is Output (drive with BRG0)
5844 * 0000 0000 0000 0100 = 0x0004
5847 usc_OutReg( info
, IOCR
, 0x0004 );
5849 } /* end of usc_reset() */
5851 /* usc_set_async_mode()
5853 * Program adapter for asynchronous communications.
5855 * Arguments: info pointer to device instance data
5856 * Return Value: None
5858 static void usc_set_async_mode( struct mgsl_struct
*info
)
5862 /* disable interrupts while programming USC */
5863 usc_DisableMasterIrqBit( info
);
5865 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5866 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5868 usc_loopback_frame( info
);
5870 /* Channel mode Register (CMR)
5872 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5873 * <13..12> 00 00 = 16X Clock
5874 * <11..8> 0000 Transmitter mode = Asynchronous
5875 * <7..6> 00 reserved?
5876 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5877 * <3..0> 0000 Receiver mode = Asynchronous
5879 * 0000 0000 0000 0000 = 0x0
5883 if ( info
->params
.stop_bits
!= 1 )
5885 usc_OutReg( info
, CMR
, RegValue
);
5888 /* Receiver mode Register (RMR)
5890 * <15..13> 000 encoding = None
5891 * <12..08> 00000 reserved (Sync Only)
5892 * <7..6> 00 Even parity
5893 * <5> 0 parity disabled
5894 * <4..2> 000 Receive Char Length = 8 bits
5895 * <1..0> 00 Disable Receiver
5897 * 0000 0000 0000 0000 = 0x0
5902 if ( info
->params
.data_bits
!= 8 )
5903 RegValue
|= BIT4
+BIT3
+BIT2
;
5905 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
5907 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
5911 usc_OutReg( info
, RMR
, RegValue
);
5914 /* Set IRQ trigger level */
5916 usc_RCmd( info
, RCmd_SelectRicrIntLevel
);
5919 /* Receive Interrupt Control Register (RICR)
5921 * <15..8> ? RxFIFO IRQ Request Level
5923 * Note: For async mode the receive FIFO level must be set
5924 * to 0 to avoid the situation where the FIFO contains fewer bytes
5925 * than the trigger level and no more data is expected.
5927 * <7> 0 Exited Hunt IA (Interrupt Arm)
5928 * <6> 0 Idle Received IA
5929 * <5> 0 Break/Abort IA
5931 * <3> 0 Queued status reflects oldest byte in FIFO
5933 * <1> 0 Rx Overrun IA
5934 * <0> 0 Select TC0 value for readback
5936 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5939 usc_OutReg( info
, RICR
, 0x0000 );
5941 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5942 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
5945 /* Transmit mode Register (TMR)
5947 * <15..13> 000 encoding = None
5948 * <12..08> 00000 reserved (Sync Only)
5949 * <7..6> 00 Transmit parity Even
5950 * <5> 0 Transmit parity Disabled
5951 * <4..2> 000 Tx Char Length = 8 bits
5952 * <1..0> 00 Disable Transmitter
5954 * 0000 0000 0000 0000 = 0x0
5959 if ( info
->params
.data_bits
!= 8 )
5960 RegValue
|= BIT4
+BIT3
+BIT2
;
5962 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
5964 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
5968 usc_OutReg( info
, TMR
, RegValue
);
5970 usc_set_txidle( info
);
5973 /* Set IRQ trigger level */
5975 usc_TCmd( info
, TCmd_SelectTicrIntLevel
);
5978 /* Transmit Interrupt Control Register (TICR)
5980 * <15..8> ? Transmit FIFO IRQ Level
5981 * <7> 0 Present IA (Interrupt Arm)
5982 * <6> 1 Idle Sent IA
5983 * <5> 0 Abort Sent IA
5984 * <4> 0 EOF/EOM Sent IA
5986 * <2> 0 1 = Wait for SW Trigger to Start Frame
5987 * <1> 0 Tx Underrun IA
5988 * <0> 0 TC0 constant on read back
5990 * 0000 0000 0100 0000 = 0x0040
5993 usc_OutReg( info
, TICR
, 0x1f40 );
5995 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5996 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
5998 usc_enable_async_clock( info
, info
->params
.data_rate
);
6001 /* Channel Control/status Register (CCSR)
6003 * <15> X RCC FIFO Overflow status (RO)
6004 * <14> X RCC FIFO Not Empty status (RO)
6005 * <13> 0 1 = Clear RCC FIFO (WO)
6006 * <12> X DPLL in Sync status (RO)
6007 * <11> X DPLL 2 Missed Clocks status (RO)
6008 * <10> X DPLL 1 Missed Clock status (RO)
6009 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6010 * <7> X SDLC Loop On status (RO)
6011 * <6> X SDLC Loop Send status (RO)
6012 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6013 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6014 * <1..0> 00 reserved
6016 * 0000 0000 0010 0000 = 0x0020
6019 usc_OutReg( info
, CCSR
, 0x0020 );
6021 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6022 RECEIVE_DATA
+ RECEIVE_STATUS
);
6024 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6025 RECEIVE_DATA
+ RECEIVE_STATUS
);
6027 usc_EnableMasterIrqBit( info
);
6029 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6030 /* Enable INTEN (Port 6, Bit12) */
6031 /* This connects the IRQ request signal to the ISA bus */
6032 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6035 if (info
->params
.loopback
) {
6036 info
->loopback_bits
= 0x300;
6037 outw(0x0300, info
->io_base
+ CCAR
);
6040 } /* end of usc_set_async_mode() */
6042 /* usc_loopback_frame()
6044 * Loop back a small (2 byte) dummy SDLC frame.
6045 * Interrupts and DMA are NOT used. The purpose of this is to
6046 * clear any 'stale' status info left over from running in async mode.
6048 * The 16C32 shows the strange behaviour of marking the 1st
6049 * received SDLC frame with a CRC error even when there is no
6050 * CRC error. To get around this a small dummy from of 2 bytes
6051 * is looped back when switching from async to sync mode.
6053 * Arguments: info pointer to device instance data
6054 * Return Value: None
6056 static void usc_loopback_frame( struct mgsl_struct
*info
)
6059 unsigned long oldmode
= info
->params
.mode
;
6061 info
->params
.mode
= MGSL_MODE_HDLC
;
6063 usc_DisableMasterIrqBit( info
);
6065 usc_set_sdlc_mode( info
);
6066 usc_enable_loopback( info
, 1 );
6068 /* Write 16-bit Time Constant for BRG0 */
6069 usc_OutReg( info
, TC0R
, 0 );
6071 /* Channel Control Register (CCR)
6073 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6074 * <13> 0 Trigger Tx on SW Command Disabled
6075 * <12> 0 Flag Preamble Disabled
6076 * <11..10> 00 Preamble Length = 8-Bits
6077 * <9..8> 01 Preamble Pattern = flags
6078 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6079 * <5> 0 Trigger Rx on SW Command Disabled
6082 * 0000 0001 0000 0000 = 0x0100
6085 usc_OutReg( info
, CCR
, 0x0100 );
6087 /* SETUP RECEIVER */
6088 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
6089 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
6091 /* SETUP TRANSMITTER */
6092 /* Program the Transmit Character Length Register (TCLR) */
6093 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6094 usc_OutReg( info
, TCLR
, 2 );
6095 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
6097 /* unlatch Tx status bits, and start transmit channel. */
6098 usc_UnlatchTxstatusBits(info
,TXSTATUS_ALL
);
6099 outw(0,info
->io_base
+ DATAREG
);
6101 /* ENABLE TRANSMITTER */
6102 usc_TCmd( info
, TCmd_SendFrame
);
6103 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
6105 /* WAIT FOR RECEIVE COMPLETE */
6106 for (i
=0 ; i
<1000 ; i
++)
6107 if (usc_InReg( info
, RCSR
) & (BIT8
+ BIT4
+ BIT3
+ BIT1
))
6110 /* clear Internal Data loopback mode */
6111 usc_enable_loopback(info
, 0);
6113 usc_EnableMasterIrqBit(info
);
6115 info
->params
.mode
= oldmode
;
6117 } /* end of usc_loopback_frame() */
6119 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6121 * Arguments: info pointer to adapter info structure
6122 * Return Value: None
6124 static void usc_set_sync_mode( struct mgsl_struct
*info
)
6126 usc_loopback_frame( info
);
6127 usc_set_sdlc_mode( info
);
6129 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6130 /* Enable INTEN (Port 6, Bit12) */
6131 /* This connects the IRQ request signal to the ISA bus */
6132 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6135 usc_enable_aux_clock(info
, info
->params
.clock_speed
);
6137 if (info
->params
.loopback
)
6138 usc_enable_loopback(info
,1);
6140 } /* end of mgsl_set_sync_mode() */
6142 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6144 * Arguments: info pointer to device instance data
6145 * Return Value: None
6147 static void usc_set_txidle( struct mgsl_struct
*info
)
6149 u16 usc_idle_mode
= IDLEMODE_FLAGS
;
6151 /* Map API idle mode to USC register bits */
6153 switch( info
->idle_mode
){
6154 case HDLC_TXIDLE_FLAGS
: usc_idle_mode
= IDLEMODE_FLAGS
; break;
6155 case HDLC_TXIDLE_ALT_ZEROS_ONES
: usc_idle_mode
= IDLEMODE_ALT_ONE_ZERO
; break;
6156 case HDLC_TXIDLE_ZEROS
: usc_idle_mode
= IDLEMODE_ZERO
; break;
6157 case HDLC_TXIDLE_ONES
: usc_idle_mode
= IDLEMODE_ONE
; break;
6158 case HDLC_TXIDLE_ALT_MARK_SPACE
: usc_idle_mode
= IDLEMODE_ALT_MARK_SPACE
; break;
6159 case HDLC_TXIDLE_SPACE
: usc_idle_mode
= IDLEMODE_SPACE
; break;
6160 case HDLC_TXIDLE_MARK
: usc_idle_mode
= IDLEMODE_MARK
; break;
6163 info
->usc_idle_mode
= usc_idle_mode
;
6164 //usc_OutReg(info, TCSR, usc_idle_mode);
6165 info
->tcsr_value
&= ~IDLEMODE_MASK
; /* clear idle mode bits */
6166 info
->tcsr_value
+= usc_idle_mode
;
6167 usc_OutReg(info
, TCSR
, info
->tcsr_value
);
6170 * if SyncLink WAN adapter is running in external sync mode, the
6171 * transmitter has been set to Monosync in order to try to mimic
6172 * a true raw outbound bit stream. Monosync still sends an open/close
6173 * sync char at the start/end of a frame. Try to match those sync
6174 * patterns to the idle mode set here
6176 if ( info
->params
.mode
== MGSL_MODE_RAW
) {
6177 unsigned char syncpat
= 0;
6178 switch( info
->idle_mode
) {
6179 case HDLC_TXIDLE_FLAGS
:
6182 case HDLC_TXIDLE_ALT_ZEROS_ONES
:
6185 case HDLC_TXIDLE_ZEROS
:
6186 case HDLC_TXIDLE_SPACE
:
6189 case HDLC_TXIDLE_ONES
:
6190 case HDLC_TXIDLE_MARK
:
6193 case HDLC_TXIDLE_ALT_MARK_SPACE
:
6198 usc_SetTransmitSyncChars(info
,syncpat
,syncpat
);
6201 } /* end of usc_set_txidle() */
6203 /* usc_get_serial_signals()
6205 * Query the adapter for the state of the V24 status (input) signals.
6207 * Arguments: info pointer to device instance data
6208 * Return Value: None
6210 static void usc_get_serial_signals( struct mgsl_struct
*info
)
6214 /* clear all serial signals except DTR and RTS */
6215 info
->serial_signals
&= SerialSignal_DTR
+ SerialSignal_RTS
;
6217 /* Read the Misc Interrupt status Register (MISR) to get */
6218 /* the V24 status signals. */
6220 status
= usc_InReg( info
, MISR
);
6222 /* set serial signal bits to reflect MISR */
6224 if ( status
& MISCSTATUS_CTS
)
6225 info
->serial_signals
|= SerialSignal_CTS
;
6227 if ( status
& MISCSTATUS_DCD
)
6228 info
->serial_signals
|= SerialSignal_DCD
;
6230 if ( status
& MISCSTATUS_RI
)
6231 info
->serial_signals
|= SerialSignal_RI
;
6233 if ( status
& MISCSTATUS_DSR
)
6234 info
->serial_signals
|= SerialSignal_DSR
;
6236 } /* end of usc_get_serial_signals() */
6238 /* usc_set_serial_signals()
6240 * Set the state of DTR and RTS based on contents of
6241 * serial_signals member of device extension.
6243 * Arguments: info pointer to device instance data
6244 * Return Value: None
6246 static void usc_set_serial_signals( struct mgsl_struct
*info
)
6249 unsigned char V24Out
= info
->serial_signals
;
6251 /* get the current value of the Port Control Register (PCR) */
6253 Control
= usc_InReg( info
, PCR
);
6255 if ( V24Out
& SerialSignal_RTS
)
6260 if ( V24Out
& SerialSignal_DTR
)
6265 usc_OutReg( info
, PCR
, Control
);
6267 } /* end of usc_set_serial_signals() */
6269 /* usc_enable_async_clock()
6271 * Enable the async clock at the specified frequency.
6273 * Arguments: info pointer to device instance data
6274 * data_rate data rate of clock in bps
6275 * 0 disables the AUX clock.
6276 * Return Value: None
6278 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 data_rate
)
6282 * Clock mode Control Register (CMCR)
6284 * <15..14> 00 counter 1 Disabled
6285 * <13..12> 00 counter 0 Disabled
6286 * <11..10> 11 BRG1 Input is TxC Pin
6287 * <9..8> 11 BRG0 Input is TxC Pin
6288 * <7..6> 01 DPLL Input is BRG1 Output
6289 * <5..3> 100 TxCLK comes from BRG0
6290 * <2..0> 100 RxCLK comes from BRG0
6292 * 0000 1111 0110 0100 = 0x0f64
6295 usc_OutReg( info
, CMCR
, 0x0f64 );
6299 * Write 16-bit Time Constant for BRG0
6300 * Time Constant = (ClkSpeed / data_rate) - 1
6301 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6304 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6305 usc_OutReg( info
, TC0R
, (u16
)((691200/data_rate
) - 1) );
6307 usc_OutReg( info
, TC0R
, (u16
)((921600/data_rate
) - 1) );
6311 * Hardware Configuration Register (HCR)
6312 * Clear Bit 1, BRG0 mode = Continuous
6313 * Set Bit 0 to enable BRG0.
6316 usc_OutReg( info
, HCR
,
6317 (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
6320 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6322 usc_OutReg( info
, IOCR
,
6323 (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
6325 /* data rate == 0 so turn off BRG0 */
6326 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
6329 } /* end of usc_enable_async_clock() */
6332 * Buffer Structures:
6334 * Normal memory access uses virtual addresses that can make discontiguous
6335 * physical memory pages appear to be contiguous in the virtual address
6336 * space (the processors memory mapping handles the conversions).
6338 * DMA transfers require physically contiguous memory. This is because
6339 * the DMA system controller and DMA bus masters deal with memory using
6340 * only physical addresses.
6342 * This causes a problem under Windows NT when large DMA buffers are
6343 * needed. Fragmentation of the nonpaged pool prevents allocations of
6344 * physically contiguous buffers larger than the PAGE_SIZE.
6346 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6347 * allows DMA transfers to physically discontiguous buffers. Information
6348 * about each data transfer buffer is contained in a memory structure
6349 * called a 'buffer entry'. A list of buffer entries is maintained
6350 * to track and control the use of the data transfer buffers.
6352 * To support this strategy we will allocate sufficient PAGE_SIZE
6353 * contiguous memory buffers to allow for the total required buffer
6356 * The 16C32 accesses the list of buffer entries using Bus Master
6357 * DMA. Control information is read from the buffer entries by the
6358 * 16C32 to control data transfers. status information is written to
6359 * the buffer entries by the 16C32 to indicate the status of completed
6362 * The CPU writes control information to the buffer entries to control
6363 * the 16C32 and reads status information from the buffer entries to
6364 * determine information about received and transmitted frames.
6366 * Because the CPU and 16C32 (adapter) both need simultaneous access
6367 * to the buffer entries, the buffer entry memory is allocated with
6368 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6369 * entry list to PAGE_SIZE.
6371 * The actual data buffers on the other hand will only be accessed
6372 * by the CPU or the adapter but not by both simultaneously. This allows
6373 * Scatter/Gather packet based DMA procedures for using physically
6374 * discontiguous pages.
6378 * mgsl_reset_tx_dma_buffers()
6380 * Set the count for all transmit buffers to 0 to indicate the
6381 * buffer is available for use and set the current buffer to the
6382 * first buffer. This effectively makes all buffers free and
6383 * discards any data in buffers.
6385 * Arguments: info pointer to device instance data
6386 * Return Value: None
6388 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
)
6392 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
6393 *((unsigned long *)&(info
->tx_buffer_list
[i
].count
)) = 0;
6396 info
->current_tx_buffer
= 0;
6397 info
->start_tx_dma_buffer
= 0;
6398 info
->tx_dma_buffers_used
= 0;
6400 info
->get_tx_holding_index
= 0;
6401 info
->put_tx_holding_index
= 0;
6402 info
->tx_holding_count
= 0;
6404 } /* end of mgsl_reset_tx_dma_buffers() */
6407 * num_free_tx_dma_buffers()
6409 * returns the number of free tx dma buffers available
6411 * Arguments: info pointer to device instance data
6412 * Return Value: number of free tx dma buffers
6414 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
)
6416 return info
->tx_buffer_count
- info
->tx_dma_buffers_used
;
6420 * mgsl_reset_rx_dma_buffers()
6422 * Set the count for all receive buffers to DMABUFFERSIZE
6423 * and set the current buffer to the first buffer. This effectively
6424 * makes all buffers free and discards any data in buffers.
6426 * Arguments: info pointer to device instance data
6427 * Return Value: None
6429 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
)
6433 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
6434 *((unsigned long *)&(info
->rx_buffer_list
[i
].count
)) = DMABUFFERSIZE
;
6435 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6436 // info->rx_buffer_list[i].status = 0;
6439 info
->current_rx_buffer
= 0;
6441 } /* end of mgsl_reset_rx_dma_buffers() */
6444 * mgsl_free_rx_frame_buffers()
6446 * Free the receive buffers used by a received SDLC
6447 * frame such that the buffers can be reused.
6451 * info pointer to device instance data
6452 * StartIndex index of 1st receive buffer of frame
6453 * EndIndex index of last receive buffer of frame
6455 * Return Value: None
6457 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
)
6460 DMABUFFERENTRY
*pBufEntry
;
6463 /* Starting with 1st buffer entry of the frame clear the status */
6464 /* field and set the count field to DMA Buffer Size. */
6469 pBufEntry
= &(info
->rx_buffer_list
[Index
]);
6471 if ( Index
== EndIndex
) {
6472 /* This is the last buffer of the frame! */
6476 /* reset current buffer for reuse */
6477 // pBufEntry->status = 0;
6478 // pBufEntry->count = DMABUFFERSIZE;
6479 *((unsigned long *)&(pBufEntry
->count
)) = DMABUFFERSIZE
;
6481 /* advance to next buffer entry in linked list */
6483 if ( Index
== info
->rx_buffer_count
)
6487 /* set current buffer to next buffer after last buffer of frame */
6488 info
->current_rx_buffer
= Index
;
6490 } /* end of free_rx_frame_buffers() */
6492 /* mgsl_get_rx_frame()
6494 * This function attempts to return a received SDLC frame from the
6495 * receive DMA buffers. Only frames received without errors are returned.
6497 * Arguments: info pointer to device extension
6498 * Return Value: true if frame returned, otherwise false
6500 static bool mgsl_get_rx_frame(struct mgsl_struct
*info
)
6502 unsigned int StartIndex
, EndIndex
; /* index of 1st and last buffers of Rx frame */
6503 unsigned short status
;
6504 DMABUFFERENTRY
*pBufEntry
;
6505 unsigned int framesize
= 0;
6506 bool ReturnCode
= false;
6507 unsigned long flags
;
6508 struct tty_struct
*tty
= info
->port
.tty
;
6509 bool return_frame
= false;
6512 * current_rx_buffer points to the 1st buffer of the next available
6513 * receive frame. To find the last buffer of the frame look for
6514 * a non-zero status field in the buffer entries. (The status
6515 * field is set by the 16C32 after completing a receive frame.
6518 StartIndex
= EndIndex
= info
->current_rx_buffer
;
6520 while( !info
->rx_buffer_list
[EndIndex
].status
) {
6522 * If the count field of the buffer entry is non-zero then
6523 * this buffer has not been used. (The 16C32 clears the count
6524 * field when it starts using the buffer.) If an unused buffer
6525 * is encountered then there are no frames available.
6528 if ( info
->rx_buffer_list
[EndIndex
].count
)
6531 /* advance to next buffer entry in linked list */
6533 if ( EndIndex
== info
->rx_buffer_count
)
6536 /* if entire list searched then no frame available */
6537 if ( EndIndex
== StartIndex
) {
6538 /* If this occurs then something bad happened,
6539 * all buffers have been 'used' but none mark
6540 * the end of a frame. Reset buffers and receiver.
6543 if ( info
->rx_enabled
){
6544 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6545 usc_start_receiver(info
);
6546 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6553 /* check status of receive frame */
6555 status
= info
->rx_buffer_list
[EndIndex
].status
;
6557 if ( status
& (RXSTATUS_SHORT_FRAME
+ RXSTATUS_OVERRUN
+
6558 RXSTATUS_CRC_ERROR
+ RXSTATUS_ABORT
) ) {
6559 if ( status
& RXSTATUS_SHORT_FRAME
)
6560 info
->icount
.rxshort
++;
6561 else if ( status
& RXSTATUS_ABORT
)
6562 info
->icount
.rxabort
++;
6563 else if ( status
& RXSTATUS_OVERRUN
)
6564 info
->icount
.rxover
++;
6566 info
->icount
.rxcrc
++;
6567 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
)
6568 return_frame
= true;
6571 #if SYNCLINK_GENERIC_HDLC
6573 info
->netdev
->stats
.rx_errors
++;
6574 info
->netdev
->stats
.rx_frame_errors
++;
6578 return_frame
= true;
6580 if ( return_frame
) {
6581 /* receive frame has no errors, get frame size.
6582 * The frame size is the starting value of the RCC (which was
6583 * set to 0xffff) minus the ending value of the RCC (decremented
6584 * once for each receive character) minus 2 for the 16-bit CRC.
6587 framesize
= RCLRVALUE
- info
->rx_buffer_list
[EndIndex
].rcc
;
6589 /* adjust frame size for CRC if any */
6590 if ( info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
6592 else if ( info
->params
.crc_type
== HDLC_CRC_32_CCITT
)
6596 if ( debug_level
>= DEBUG_LEVEL_BH
)
6597 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6598 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6600 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6601 mgsl_trace_block(info
,info
->rx_buffer_list
[StartIndex
].virt_addr
,
6602 min_t(int, framesize
, DMABUFFERSIZE
),0);
6605 if ( ( (info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) &&
6606 ((framesize
+1) > info
->max_frame_size
) ) ||
6607 (framesize
> info
->max_frame_size
) )
6608 info
->icount
.rxlong
++;
6610 /* copy dma buffer(s) to contiguous intermediate buffer */
6611 int copy_count
= framesize
;
6612 int index
= StartIndex
;
6613 unsigned char *ptmp
= info
->intermediate_rxbuffer
;
6615 if ( !(status
& RXSTATUS_CRC_ERROR
))
6616 info
->icount
.rxok
++;
6620 if ( copy_count
> DMABUFFERSIZE
)
6621 partial_count
= DMABUFFERSIZE
;
6623 partial_count
= copy_count
;
6625 pBufEntry
= &(info
->rx_buffer_list
[index
]);
6626 memcpy( ptmp
, pBufEntry
->virt_addr
, partial_count
);
6627 ptmp
+= partial_count
;
6628 copy_count
-= partial_count
;
6630 if ( ++index
== info
->rx_buffer_count
)
6634 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) {
6636 *ptmp
= (status
& RXSTATUS_CRC_ERROR
?
6640 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6641 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6642 __FILE__
,__LINE__
,info
->device_name
,
6646 #if SYNCLINK_GENERIC_HDLC
6648 hdlcdev_rx(info
,info
->intermediate_rxbuffer
,framesize
);
6651 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6654 /* Free the buffers used by this frame. */
6655 mgsl_free_rx_frame_buffers( info
, StartIndex
, EndIndex
);
6661 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6662 /* The receiver needs to restarted because of
6663 * a receive overflow (buffer or FIFO). If the
6664 * receive buffers are now empty, then restart receiver.
6667 if ( !info
->rx_buffer_list
[EndIndex
].status
&&
6668 info
->rx_buffer_list
[EndIndex
].count
) {
6669 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6670 usc_start_receiver(info
);
6671 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6677 } /* end of mgsl_get_rx_frame() */
6679 /* mgsl_get_raw_rx_frame()
6681 * This function attempts to return a received frame from the
6682 * receive DMA buffers when running in external loop mode. In this mode,
6683 * we will return at most one DMABUFFERSIZE frame to the application.
6684 * The USC receiver is triggering off of DCD going active to start a new
6685 * frame, and DCD going inactive to terminate the frame (similar to
6686 * processing a closing flag character).
6688 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6689 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6690 * status field and the RCC field will indicate the length of the
6691 * entire received frame. We take this RCC field and get the modulus
6692 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6693 * last Rx DMA buffer and return that last portion of the frame.
6695 * Arguments: info pointer to device extension
6696 * Return Value: true if frame returned, otherwise false
6698 static bool mgsl_get_raw_rx_frame(struct mgsl_struct
*info
)
6700 unsigned int CurrentIndex
, NextIndex
;
6701 unsigned short status
;
6702 DMABUFFERENTRY
*pBufEntry
;
6703 unsigned int framesize
= 0;
6704 bool ReturnCode
= false;
6705 unsigned long flags
;
6706 struct tty_struct
*tty
= info
->port
.tty
;
6709 * current_rx_buffer points to the 1st buffer of the next available
6710 * receive frame. The status field is set by the 16C32 after
6711 * completing a receive frame. If the status field of this buffer
6712 * is zero, either the USC is still filling this buffer or this
6713 * is one of a series of buffers making up a received frame.
6715 * If the count field of this buffer is zero, the USC is either
6716 * using this buffer or has used this buffer. Look at the count
6717 * field of the next buffer. If that next buffer's count is
6718 * non-zero, the USC is still actively using the current buffer.
6719 * Otherwise, if the next buffer's count field is zero, the
6720 * current buffer is complete and the USC is using the next
6723 CurrentIndex
= NextIndex
= info
->current_rx_buffer
;
6725 if ( NextIndex
== info
->rx_buffer_count
)
6728 if ( info
->rx_buffer_list
[CurrentIndex
].status
!= 0 ||
6729 (info
->rx_buffer_list
[CurrentIndex
].count
== 0 &&
6730 info
->rx_buffer_list
[NextIndex
].count
== 0)) {
6732 * Either the status field of this dma buffer is non-zero
6733 * (indicating the last buffer of a receive frame) or the next
6734 * buffer is marked as in use -- implying this buffer is complete
6735 * and an intermediate buffer for this received frame.
6738 status
= info
->rx_buffer_list
[CurrentIndex
].status
;
6740 if ( status
& (RXSTATUS_SHORT_FRAME
+ RXSTATUS_OVERRUN
+
6741 RXSTATUS_CRC_ERROR
+ RXSTATUS_ABORT
) ) {
6742 if ( status
& RXSTATUS_SHORT_FRAME
)
6743 info
->icount
.rxshort
++;
6744 else if ( status
& RXSTATUS_ABORT
)
6745 info
->icount
.rxabort
++;
6746 else if ( status
& RXSTATUS_OVERRUN
)
6747 info
->icount
.rxover
++;
6749 info
->icount
.rxcrc
++;
6753 * A receive frame is available, get frame size and status.
6755 * The frame size is the starting value of the RCC (which was
6756 * set to 0xffff) minus the ending value of the RCC (decremented
6757 * once for each receive character) minus 2 or 4 for the 16-bit
6760 * If the status field is zero, this is an intermediate buffer.
6763 * If the DMA Buffer Entry's Status field is non-zero, the
6764 * receive operation completed normally (ie: DCD dropped). The
6765 * RCC field is valid and holds the received frame size.
6766 * It is possible that the RCC field will be zero on a DMA buffer
6767 * entry with a non-zero status. This can occur if the total
6768 * frame size (number of bytes between the time DCD goes active
6769 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6770 * case the 16C32 has underrun on the RCC count and appears to
6771 * stop updating this counter to let us know the actual received
6772 * frame size. If this happens (non-zero status and zero RCC),
6773 * simply return the entire RxDMA Buffer
6777 * In the event that the final RxDMA Buffer is
6778 * terminated with a non-zero status and the RCC
6779 * field is zero, we interpret this as the RCC
6780 * having underflowed (received frame > 65535 bytes).
6782 * Signal the event to the user by passing back
6783 * a status of RxStatus_CrcError returning the full
6784 * buffer and let the app figure out what data is
6787 if ( info
->rx_buffer_list
[CurrentIndex
].rcc
)
6788 framesize
= RCLRVALUE
- info
->rx_buffer_list
[CurrentIndex
].rcc
;
6790 framesize
= DMABUFFERSIZE
;
6793 framesize
= DMABUFFERSIZE
;
6796 if ( framesize
> DMABUFFERSIZE
) {
6798 * if running in raw sync mode, ISR handler for
6799 * End Of Buffer events terminates all buffers at 4K.
6800 * If this frame size is said to be >4K, get the
6801 * actual number of bytes of the frame in this buffer.
6803 framesize
= framesize
% DMABUFFERSIZE
;
6807 if ( debug_level
>= DEBUG_LEVEL_BH
)
6808 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6809 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6811 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6812 mgsl_trace_block(info
,info
->rx_buffer_list
[CurrentIndex
].virt_addr
,
6813 min_t(int, framesize
, DMABUFFERSIZE
),0);
6816 /* copy dma buffer(s) to contiguous intermediate buffer */
6817 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6819 pBufEntry
= &(info
->rx_buffer_list
[CurrentIndex
]);
6820 memcpy( info
->intermediate_rxbuffer
, pBufEntry
->virt_addr
, framesize
);
6821 info
->icount
.rxok
++;
6823 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6826 /* Free the buffers used by this frame. */
6827 mgsl_free_rx_frame_buffers( info
, CurrentIndex
, CurrentIndex
);
6833 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6834 /* The receiver needs to restarted because of
6835 * a receive overflow (buffer or FIFO). If the
6836 * receive buffers are now empty, then restart receiver.
6839 if ( !info
->rx_buffer_list
[CurrentIndex
].status
&&
6840 info
->rx_buffer_list
[CurrentIndex
].count
) {
6841 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6842 usc_start_receiver(info
);
6843 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6849 } /* end of mgsl_get_raw_rx_frame() */
6851 /* mgsl_load_tx_dma_buffer()
6853 * Load the transmit DMA buffer with the specified data.
6857 * info pointer to device extension
6858 * Buffer pointer to buffer containing frame to load
6859 * BufferSize size in bytes of frame in Buffer
6861 * Return Value: None
6863 static void mgsl_load_tx_dma_buffer(struct mgsl_struct
*info
,
6864 const char *Buffer
, unsigned int BufferSize
)
6866 unsigned short Copycount
;
6868 DMABUFFERENTRY
*pBufEntry
;
6870 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6871 mgsl_trace_block(info
,Buffer
, min_t(int, BufferSize
, DMABUFFERSIZE
), 1);
6873 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
6874 /* set CMR:13 to start transmit when
6875 * next GoAhead (abort) is received
6877 info
->cmr_value
|= BIT13
;
6880 /* begin loading the frame in the next available tx dma
6881 * buffer, remember it's starting location for setting
6882 * up tx dma operation
6884 i
= info
->current_tx_buffer
;
6885 info
->start_tx_dma_buffer
= i
;
6887 /* Setup the status and RCC (Frame Size) fields of the 1st */
6888 /* buffer entry in the transmit DMA buffer list. */
6890 info
->tx_buffer_list
[i
].status
= info
->cmr_value
& 0xf000;
6891 info
->tx_buffer_list
[i
].rcc
= BufferSize
;
6892 info
->tx_buffer_list
[i
].count
= BufferSize
;
6894 /* Copy frame data from 1st source buffer to the DMA buffers. */
6895 /* The frame data may span multiple DMA buffers. */
6897 while( BufferSize
){
6898 /* Get a pointer to next DMA buffer entry. */
6899 pBufEntry
= &info
->tx_buffer_list
[i
++];
6901 if ( i
== info
->tx_buffer_count
)
6904 /* Calculate the number of bytes that can be copied from */
6905 /* the source buffer to this DMA buffer. */
6906 if ( BufferSize
> DMABUFFERSIZE
)
6907 Copycount
= DMABUFFERSIZE
;
6909 Copycount
= BufferSize
;
6911 /* Actually copy data from source buffer to DMA buffer. */
6912 /* Also set the data count for this individual DMA buffer. */
6913 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6914 mgsl_load_pci_memory(pBufEntry
->virt_addr
, Buffer
,Copycount
);
6916 memcpy(pBufEntry
->virt_addr
, Buffer
, Copycount
);
6918 pBufEntry
->count
= Copycount
;
6920 /* Advance source pointer and reduce remaining data count. */
6921 Buffer
+= Copycount
;
6922 BufferSize
-= Copycount
;
6924 ++info
->tx_dma_buffers_used
;
6927 /* remember next available tx dma buffer */
6928 info
->current_tx_buffer
= i
;
6930 } /* end of mgsl_load_tx_dma_buffer() */
6933 * mgsl_register_test()
6935 * Performs a register test of the 16C32.
6937 * Arguments: info pointer to device instance data
6938 * Return Value: true if test passed, otherwise false
6940 static bool mgsl_register_test( struct mgsl_struct
*info
)
6942 static unsigned short BitPatterns
[] =
6943 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
6944 static unsigned int Patterncount
= ARRAY_SIZE(BitPatterns
);
6947 unsigned long flags
;
6949 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6952 /* Verify the reset state of some registers. */
6954 if ( (usc_InReg( info
, SICR
) != 0) ||
6955 (usc_InReg( info
, IVR
) != 0) ||
6956 (usc_InDmaReg( info
, DIVR
) != 0) ){
6961 /* Write bit patterns to various registers but do it out of */
6962 /* sync, then read back and verify values. */
6964 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
6965 usc_OutReg( info
, TC0R
, BitPatterns
[i
] );
6966 usc_OutReg( info
, TC1R
, BitPatterns
[(i
+1)%Patterncount
] );
6967 usc_OutReg( info
, TCLR
, BitPatterns
[(i
+2)%Patterncount
] );
6968 usc_OutReg( info
, RCLR
, BitPatterns
[(i
+3)%Patterncount
] );
6969 usc_OutReg( info
, RSR
, BitPatterns
[(i
+4)%Patterncount
] );
6970 usc_OutDmaReg( info
, TBCR
, BitPatterns
[(i
+5)%Patterncount
] );
6972 if ( (usc_InReg( info
, TC0R
) != BitPatterns
[i
]) ||
6973 (usc_InReg( info
, TC1R
) != BitPatterns
[(i
+1)%Patterncount
]) ||
6974 (usc_InReg( info
, TCLR
) != BitPatterns
[(i
+2)%Patterncount
]) ||
6975 (usc_InReg( info
, RCLR
) != BitPatterns
[(i
+3)%Patterncount
]) ||
6976 (usc_InReg( info
, RSR
) != BitPatterns
[(i
+4)%Patterncount
]) ||
6977 (usc_InDmaReg( info
, TBCR
) != BitPatterns
[(i
+5)%Patterncount
]) ){
6985 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6989 } /* end of mgsl_register_test() */
6991 /* mgsl_irq_test() Perform interrupt test of the 16C32.
6993 * Arguments: info pointer to device instance data
6994 * Return Value: true if test passed, otherwise false
6996 static bool mgsl_irq_test( struct mgsl_struct
*info
)
6998 unsigned long EndTime
;
6999 unsigned long flags
;
7001 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7005 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7006 * The ISR sets irq_occurred to true.
7009 info
->irq_occurred
= false;
7011 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7012 /* Enable INTEN (Port 6, Bit12) */
7013 /* This connects the IRQ request signal to the ISA bus */
7014 /* on the ISA adapter. This has no effect for the PCI adapter */
7015 usc_OutReg( info
, PCR
, (unsigned short)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
) );
7017 usc_EnableMasterIrqBit(info
);
7018 usc_EnableInterrupts(info
, IO_PIN
);
7019 usc_ClearIrqPendingBits(info
, IO_PIN
);
7021 usc_UnlatchIostatusBits(info
, MISCSTATUS_TXC_LATCHED
);
7022 usc_EnableStatusIrqs(info
, SICR_TXC_ACTIVE
+ SICR_TXC_INACTIVE
);
7024 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7027 while( EndTime
-- && !info
->irq_occurred
) {
7028 msleep_interruptible(10);
7031 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7033 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7035 return info
->irq_occurred
;
7037 } /* end of mgsl_irq_test() */
7041 * Perform a DMA test of the 16C32. A small frame is
7042 * transmitted via DMA from a transmit buffer to a receive buffer
7043 * using single buffer DMA mode.
7045 * Arguments: info pointer to device instance data
7046 * Return Value: true if test passed, otherwise false
7048 static bool mgsl_dma_test( struct mgsl_struct
*info
)
7050 unsigned short FifoLevel
;
7051 unsigned long phys_addr
;
7052 unsigned int FrameSize
;
7056 unsigned short status
=0;
7057 unsigned long EndTime
;
7058 unsigned long flags
;
7059 MGSL_PARAMS tmp_params
;
7061 /* save current port options */
7062 memcpy(&tmp_params
,&info
->params
,sizeof(MGSL_PARAMS
));
7063 /* load default port options */
7064 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
7066 #define TESTFRAMESIZE 40
7068 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7070 /* setup 16C32 for SDLC DMA transfer mode */
7073 usc_set_sdlc_mode(info
);
7074 usc_enable_loopback(info
,1);
7076 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7077 * field of the buffer entry after fetching buffer address. This
7078 * way we can detect a DMA failure for a DMA read (which should be
7079 * non-destructive to system memory) before we try and write to
7080 * memory (where a failure could corrupt system memory).
7083 /* Receive DMA mode Register (RDMR)
7085 * <15..14> 11 DMA mode = Linked List Buffer mode
7086 * <13> 1 RSBinA/L = store Rx status Block in List entry
7087 * <12> 0 1 = Clear count of List Entry after fetching
7088 * <11..10> 00 Address mode = Increment
7089 * <9> 1 Terminate Buffer on RxBound
7090 * <8> 0 Bus Width = 16bits
7091 * <7..0> ? status Bits (write as 0s)
7093 * 1110 0010 0000 0000 = 0xe200
7096 usc_OutDmaReg( info
, RDMR
, 0xe200 );
7098 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7101 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7103 FrameSize
= TESTFRAMESIZE
;
7105 /* setup 1st transmit buffer entry: */
7106 /* with frame size and transmit control word */
7108 info
->tx_buffer_list
[0].count
= FrameSize
;
7109 info
->tx_buffer_list
[0].rcc
= FrameSize
;
7110 info
->tx_buffer_list
[0].status
= 0x4000;
7112 /* build a transmit frame in 1st transmit DMA buffer */
7114 TmpPtr
= info
->tx_buffer_list
[0].virt_addr
;
7115 for (i
= 0; i
< FrameSize
; i
++ )
7118 /* setup 1st receive buffer entry: */
7119 /* clear status, set max receive buffer size */
7121 info
->rx_buffer_list
[0].status
= 0;
7122 info
->rx_buffer_list
[0].count
= FrameSize
+ 4;
7124 /* zero out the 1st receive buffer */
7126 memset( info
->rx_buffer_list
[0].virt_addr
, 0, FrameSize
+ 4 );
7128 /* Set count field of next buffer entries to prevent */
7129 /* 16C32 from using buffers after the 1st one. */
7131 info
->tx_buffer_list
[1].count
= 0;
7132 info
->rx_buffer_list
[1].count
= 0;
7135 /***************************/
7136 /* Program 16C32 receiver. */
7137 /***************************/
7139 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7141 /* setup DMA transfers */
7142 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
7144 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7145 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
7146 usc_OutDmaReg( info
, NRARL
, (unsigned short)phys_addr
);
7147 usc_OutDmaReg( info
, NRARU
, (unsigned short)(phys_addr
>> 16) );
7149 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7150 usc_InDmaReg( info
, RDMR
);
7151 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
7153 /* Enable Receiver (RMR <1..0> = 10) */
7154 usc_OutReg( info
, RMR
, (unsigned short)((usc_InReg(info
, RMR
) & 0xfffc) | 0x0002) );
7156 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7159 /*************************************************************/
7160 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7161 /*************************************************************/
7163 /* Wait 100ms for interrupt. */
7164 EndTime
= jiffies
+ msecs_to_jiffies(100);
7167 if (time_after(jiffies
, EndTime
)) {
7172 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7173 status
= usc_InDmaReg( info
, RDMR
);
7174 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7176 if ( !(status
& BIT4
) && (status
& BIT5
) ) {
7177 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7178 /* BUSY (BIT 5) is active (channel still active). */
7179 /* This means the buffer entry read has completed. */
7185 /******************************/
7186 /* Program 16C32 transmitter. */
7187 /******************************/
7189 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7191 /* Program the Transmit Character Length Register (TCLR) */
7192 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7194 usc_OutReg( info
, TCLR
, (unsigned short)info
->tx_buffer_list
[0].count
);
7195 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7197 /* Program the address of the 1st DMA Buffer Entry in linked list */
7199 phys_addr
= info
->tx_buffer_list
[0].phys_entry
;
7200 usc_OutDmaReg( info
, NTARL
, (unsigned short)phys_addr
);
7201 usc_OutDmaReg( info
, NTARU
, (unsigned short)(phys_addr
>> 16) );
7203 /* unlatch Tx status bits, and start transmit channel. */
7205 usc_OutReg( info
, TCSR
, (unsigned short)(( usc_InReg(info
, TCSR
) & 0x0f00) | 0xfa) );
7206 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
7208 /* wait for DMA controller to fill transmit FIFO */
7210 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
7212 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7215 /**********************************/
7216 /* WAIT FOR TRANSMIT FIFO TO FILL */
7217 /**********************************/
7220 EndTime
= jiffies
+ msecs_to_jiffies(100);
7223 if (time_after(jiffies
, EndTime
)) {
7228 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7229 FifoLevel
= usc_InReg(info
, TICR
) >> 8;
7230 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7232 if ( FifoLevel
< 16 )
7235 if ( FrameSize
< 32 ) {
7236 /* This frame is smaller than the entire transmit FIFO */
7237 /* so wait for the entire frame to be loaded. */
7238 if ( FifoLevel
<= (32 - FrameSize
) )
7246 /* Enable 16C32 transmitter. */
7248 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7250 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7251 usc_TCmd( info
, TCmd_SendFrame
);
7252 usc_OutReg( info
, TMR
, (unsigned short)((usc_InReg(info
, TMR
) & 0xfffc) | 0x0002) );
7254 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7257 /******************************/
7258 /* WAIT FOR TRANSMIT COMPLETE */
7259 /******************************/
7262 EndTime
= jiffies
+ msecs_to_jiffies(100);
7264 /* While timer not expired wait for transmit complete */
7266 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7267 status
= usc_InReg( info
, TCSR
);
7268 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7270 while ( !(status
& (BIT6
+BIT5
+BIT4
+BIT2
+BIT1
)) ) {
7271 if (time_after(jiffies
, EndTime
)) {
7276 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7277 status
= usc_InReg( info
, TCSR
);
7278 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7284 /* CHECK FOR TRANSMIT ERRORS */
7285 if ( status
& (BIT5
+ BIT1
) )
7290 /* WAIT FOR RECEIVE COMPLETE */
7293 EndTime
= jiffies
+ msecs_to_jiffies(100);
7295 /* Wait for 16C32 to write receive status to buffer entry. */
7296 status
=info
->rx_buffer_list
[0].status
;
7297 while ( status
== 0 ) {
7298 if (time_after(jiffies
, EndTime
)) {
7302 status
=info
->rx_buffer_list
[0].status
;
7308 /* CHECK FOR RECEIVE ERRORS */
7309 status
= info
->rx_buffer_list
[0].status
;
7311 if ( status
& (BIT8
+ BIT3
+ BIT1
) ) {
7312 /* receive error has occurred */
7315 if ( memcmp( info
->tx_buffer_list
[0].virt_addr
,
7316 info
->rx_buffer_list
[0].virt_addr
, FrameSize
) ){
7322 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7324 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7326 /* restore current port options */
7327 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
7331 } /* end of mgsl_dma_test() */
7333 /* mgsl_adapter_test()
7335 * Perform the register, IRQ, and DMA tests for the 16C32.
7337 * Arguments: info pointer to device instance data
7338 * Return Value: 0 if success, otherwise -ENODEV
7340 static int mgsl_adapter_test( struct mgsl_struct
*info
)
7342 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7343 printk( "%s(%d):Testing device %s\n",
7344 __FILE__
,__LINE__
,info
->device_name
);
7346 if ( !mgsl_register_test( info
) ) {
7347 info
->init_error
= DiagStatus_AddressFailure
;
7348 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7349 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->io_base
) );
7353 if ( !mgsl_irq_test( info
) ) {
7354 info
->init_error
= DiagStatus_IrqFailure
;
7355 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7356 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->irq_level
) );
7360 if ( !mgsl_dma_test( info
) ) {
7361 info
->init_error
= DiagStatus_DmaFailure
;
7362 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7363 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->dma_level
) );
7367 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7368 printk( "%s(%d):device %s passed diagnostics\n",
7369 __FILE__
,__LINE__
,info
->device_name
);
7373 } /* end of mgsl_adapter_test() */
7375 /* mgsl_memory_test()
7377 * Test the shared memory on a PCI adapter.
7379 * Arguments: info pointer to device instance data
7380 * Return Value: true if test passed, otherwise false
7382 static bool mgsl_memory_test( struct mgsl_struct
*info
)
7384 static unsigned long BitPatterns
[] =
7385 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7386 unsigned long Patterncount
= ARRAY_SIZE(BitPatterns
);
7388 unsigned long TestLimit
= SHARED_MEM_ADDRESS_SIZE
/sizeof(unsigned long);
7389 unsigned long * TestAddr
;
7391 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
7394 TestAddr
= (unsigned long *)info
->memory_base
;
7396 /* Test data lines with test pattern at one location. */
7398 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
7399 *TestAddr
= BitPatterns
[i
];
7400 if ( *TestAddr
!= BitPatterns
[i
] )
7404 /* Test address lines with incrementing pattern over */
7405 /* entire address range. */
7407 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7412 TestAddr
= (unsigned long *)info
->memory_base
;
7414 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7415 if ( *TestAddr
!= i
* 4 )
7420 memset( info
->memory_base
, 0, SHARED_MEM_ADDRESS_SIZE
);
7424 } /* End Of mgsl_memory_test() */
7427 /* mgsl_load_pci_memory()
7429 * Load a large block of data into the PCI shared memory.
7430 * Use this instead of memcpy() or memmove() to move data
7431 * into the PCI shared memory.
7435 * This function prevents the PCI9050 interface chip from hogging
7436 * the adapter local bus, which can starve the 16C32 by preventing
7437 * 16C32 bus master cycles.
7439 * The PCI9050 documentation says that the 9050 will always release
7440 * control of the local bus after completing the current read
7441 * or write operation.
7443 * It appears that as long as the PCI9050 write FIFO is full, the
7444 * PCI9050 treats all of the writes as a single burst transaction
7445 * and will not release the bus. This causes DMA latency problems
7446 * at high speeds when copying large data blocks to the shared
7449 * This function in effect, breaks the a large shared memory write
7450 * into multiple transations by interleaving a shared memory read
7451 * which will flush the write FIFO and 'complete' the write
7452 * transation. This allows any pending DMA request to gain control
7453 * of the local bus in a timely fasion.
7457 * TargetPtr pointer to target address in PCI shared memory
7458 * SourcePtr pointer to source buffer for data
7459 * count count in bytes of data to copy
7461 * Return Value: None
7463 static void mgsl_load_pci_memory( char* TargetPtr
, const char* SourcePtr
,
7464 unsigned short count
)
7466 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7467 #define PCI_LOAD_INTERVAL 64
7469 unsigned short Intervalcount
= count
/ PCI_LOAD_INTERVAL
;
7470 unsigned short Index
;
7471 unsigned long Dummy
;
7473 for ( Index
= 0 ; Index
< Intervalcount
; Index
++ )
7475 memcpy(TargetPtr
, SourcePtr
, PCI_LOAD_INTERVAL
);
7476 Dummy
= *((volatile unsigned long *)TargetPtr
);
7477 TargetPtr
+= PCI_LOAD_INTERVAL
;
7478 SourcePtr
+= PCI_LOAD_INTERVAL
;
7481 memcpy( TargetPtr
, SourcePtr
, count
% PCI_LOAD_INTERVAL
);
7483 } /* End Of mgsl_load_pci_memory() */
7485 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
)
7490 printk("%s tx data:\n",info
->device_name
);
7492 printk("%s rx data:\n",info
->device_name
);
7500 for(i
=0;i
<linecount
;i
++)
7501 printk("%02X ",(unsigned char)data
[i
]);
7504 for(i
=0;i
<linecount
;i
++) {
7505 if (data
[i
]>=040 && data
[i
]<=0176)
7506 printk("%c",data
[i
]);
7515 } /* end of mgsl_trace_block() */
7517 /* mgsl_tx_timeout()
7519 * called when HDLC frame times out
7520 * update stats and do tx completion processing
7522 * Arguments: context pointer to device instance data
7523 * Return Value: None
7525 static void mgsl_tx_timeout(unsigned long context
)
7527 struct mgsl_struct
*info
= (struct mgsl_struct
*)context
;
7528 unsigned long flags
;
7530 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7531 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7532 __FILE__
,__LINE__
,info
->device_name
);
7533 if(info
->tx_active
&&
7534 (info
->params
.mode
== MGSL_MODE_HDLC
||
7535 info
->params
.mode
== MGSL_MODE_RAW
) ) {
7536 info
->icount
.txtimeout
++;
7538 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7539 info
->tx_active
= false;
7540 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
7542 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
7543 usc_loopmode_cancel_transmit( info
);
7545 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7547 #if SYNCLINK_GENERIC_HDLC
7549 hdlcdev_tx_done(info
);
7552 mgsl_bh_transmit(info
);
7554 } /* end of mgsl_tx_timeout() */
7556 /* signal that there are no more frames to send, so that
7557 * line is 'released' by echoing RxD to TxD when current
7558 * transmission is complete (or immediately if no tx in progress).
7560 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
)
7562 unsigned long flags
;
7564 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7565 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
7566 if (info
->tx_active
)
7567 info
->loopmode_send_done_requested
= true;
7569 usc_loopmode_send_done(info
);
7571 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7576 /* release the line by echoing RxD to TxD
7577 * upon completion of a transmit frame
7579 static void usc_loopmode_send_done( struct mgsl_struct
* info
)
7581 info
->loopmode_send_done_requested
= false;
7582 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7583 info
->cmr_value
&= ~BIT13
;
7584 usc_OutReg(info
, CMR
, info
->cmr_value
);
7587 /* abort a transmit in progress while in HDLC LoopMode
7589 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
)
7591 /* reset tx dma channel and purge TxFifo */
7592 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7593 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
7594 usc_loopmode_send_done( info
);
7597 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7598 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7599 * we must clear CMR:13 to begin repeating TxData to RxData
7601 static void usc_loopmode_insert_request( struct mgsl_struct
* info
)
7603 info
->loopmode_insert_requested
= true;
7605 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7606 * begin repeating TxData on RxData (complete insertion)
7608 usc_OutReg( info
, RICR
,
7609 (usc_InReg( info
, RICR
) | RXSTATUS_ABORT_RECEIVED
) );
7611 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7612 info
->cmr_value
|= BIT13
;
7613 usc_OutReg(info
, CMR
, info
->cmr_value
);
7616 /* return 1 if station is inserted into the loop, otherwise 0
7618 static int usc_loopmode_active( struct mgsl_struct
* info
)
7620 return usc_InReg( info
, CCSR
) & BIT7
? 1 : 0 ;
7623 #if SYNCLINK_GENERIC_HDLC
7626 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7627 * set encoding and frame check sequence (FCS) options
7629 * dev pointer to network device structure
7630 * encoding serial encoding setting
7631 * parity FCS setting
7633 * returns 0 if success, otherwise error code
7635 static int hdlcdev_attach(struct net_device
*dev
, unsigned short encoding
,
7636 unsigned short parity
)
7638 struct mgsl_struct
*info
= dev_to_port(dev
);
7639 unsigned char new_encoding
;
7640 unsigned short new_crctype
;
7642 /* return error if TTY interface open */
7643 if (info
->port
.count
)
7648 case ENCODING_NRZ
: new_encoding
= HDLC_ENCODING_NRZ
; break;
7649 case ENCODING_NRZI
: new_encoding
= HDLC_ENCODING_NRZI_SPACE
; break;
7650 case ENCODING_FM_MARK
: new_encoding
= HDLC_ENCODING_BIPHASE_MARK
; break;
7651 case ENCODING_FM_SPACE
: new_encoding
= HDLC_ENCODING_BIPHASE_SPACE
; break;
7652 case ENCODING_MANCHESTER
: new_encoding
= HDLC_ENCODING_BIPHASE_LEVEL
; break;
7653 default: return -EINVAL
;
7658 case PARITY_NONE
: new_crctype
= HDLC_CRC_NONE
; break;
7659 case PARITY_CRC16_PR1_CCITT
: new_crctype
= HDLC_CRC_16_CCITT
; break;
7660 case PARITY_CRC32_PR1_CCITT
: new_crctype
= HDLC_CRC_32_CCITT
; break;
7661 default: return -EINVAL
;
7664 info
->params
.encoding
= new_encoding
;
7665 info
->params
.crc_type
= new_crctype
;
7667 /* if network interface up, reprogram hardware */
7669 mgsl_program_hw(info
);
7675 * called by generic HDLC layer to send frame
7677 * skb socket buffer containing HDLC frame
7678 * dev pointer to network device structure
7680 static netdev_tx_t
hdlcdev_xmit(struct sk_buff
*skb
,
7681 struct net_device
*dev
)
7683 struct mgsl_struct
*info
= dev_to_port(dev
);
7684 unsigned long flags
;
7686 if (debug_level
>= DEBUG_LEVEL_INFO
)
7687 printk(KERN_INFO
"%s:hdlc_xmit(%s)\n",__FILE__
,dev
->name
);
7689 /* stop sending until this frame completes */
7690 netif_stop_queue(dev
);
7692 /* copy data to device buffers */
7693 info
->xmit_cnt
= skb
->len
;
7694 mgsl_load_tx_dma_buffer(info
, skb
->data
, skb
->len
);
7696 /* update network statistics */
7697 dev
->stats
.tx_packets
++;
7698 dev
->stats
.tx_bytes
+= skb
->len
;
7700 /* done with socket buffer, so free it */
7703 /* save start time for transmit timeout detection */
7704 dev
->trans_start
= jiffies
;
7706 /* start hardware transmitter if necessary */
7707 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7708 if (!info
->tx_active
)
7709 usc_start_transmitter(info
);
7710 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7712 return NETDEV_TX_OK
;
7716 * called by network layer when interface enabled
7717 * claim resources and initialize hardware
7719 * dev pointer to network device structure
7721 * returns 0 if success, otherwise error code
7723 static int hdlcdev_open(struct net_device
*dev
)
7725 struct mgsl_struct
*info
= dev_to_port(dev
);
7727 unsigned long flags
;
7729 if (debug_level
>= DEBUG_LEVEL_INFO
)
7730 printk("%s:hdlcdev_open(%s)\n",__FILE__
,dev
->name
);
7732 /* generic HDLC layer open processing */
7733 if ((rc
= hdlc_open(dev
)))
7736 /* arbitrate between network and tty opens */
7737 spin_lock_irqsave(&info
->netlock
, flags
);
7738 if (info
->port
.count
!= 0 || info
->netcount
!= 0) {
7739 printk(KERN_WARNING
"%s: hdlc_open returning busy\n", dev
->name
);
7740 spin_unlock_irqrestore(&info
->netlock
, flags
);
7744 spin_unlock_irqrestore(&info
->netlock
, flags
);
7746 /* claim resources and init adapter */
7747 if ((rc
= startup(info
)) != 0) {
7748 spin_lock_irqsave(&info
->netlock
, flags
);
7750 spin_unlock_irqrestore(&info
->netlock
, flags
);
7754 /* assert DTR and RTS, apply hardware settings */
7755 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
7756 mgsl_program_hw(info
);
7758 /* enable network layer transmit */
7759 dev
->trans_start
= jiffies
;
7760 netif_start_queue(dev
);
7762 /* inform generic HDLC layer of current DCD status */
7763 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
7764 usc_get_serial_signals(info
);
7765 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
7766 if (info
->serial_signals
& SerialSignal_DCD
)
7767 netif_carrier_on(dev
);
7769 netif_carrier_off(dev
);
7774 * called by network layer when interface is disabled
7775 * shutdown hardware and release resources
7777 * dev pointer to network device structure
7779 * returns 0 if success, otherwise error code
7781 static int hdlcdev_close(struct net_device
*dev
)
7783 struct mgsl_struct
*info
= dev_to_port(dev
);
7784 unsigned long flags
;
7786 if (debug_level
>= DEBUG_LEVEL_INFO
)
7787 printk("%s:hdlcdev_close(%s)\n",__FILE__
,dev
->name
);
7789 netif_stop_queue(dev
);
7791 /* shutdown adapter and release resources */
7796 spin_lock_irqsave(&info
->netlock
, flags
);
7798 spin_unlock_irqrestore(&info
->netlock
, flags
);
7804 * called by network layer to process IOCTL call to network device
7806 * dev pointer to network device structure
7807 * ifr pointer to network interface request structure
7808 * cmd IOCTL command code
7810 * returns 0 if success, otherwise error code
7812 static int hdlcdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
7814 const size_t size
= sizeof(sync_serial_settings
);
7815 sync_serial_settings new_line
;
7816 sync_serial_settings __user
*line
= ifr
->ifr_settings
.ifs_ifsu
.sync
;
7817 struct mgsl_struct
*info
= dev_to_port(dev
);
7820 if (debug_level
>= DEBUG_LEVEL_INFO
)
7821 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__
,dev
->name
);
7823 /* return error if TTY interface open */
7824 if (info
->port
.count
)
7827 if (cmd
!= SIOCWANDEV
)
7828 return hdlc_ioctl(dev
, ifr
, cmd
);
7830 switch(ifr
->ifr_settings
.type
) {
7831 case IF_GET_IFACE
: /* return current sync_serial_settings */
7833 ifr
->ifr_settings
.type
= IF_IFACE_SYNC_SERIAL
;
7834 if (ifr
->ifr_settings
.size
< size
) {
7835 ifr
->ifr_settings
.size
= size
; /* data size wanted */
7839 flags
= info
->params
.flags
& (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7840 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7841 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7842 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7845 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
): new_line
.clock_type
= CLOCK_EXT
; break;
7846 case (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_INT
; break;
7847 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_TXINT
; break;
7848 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
): new_line
.clock_type
= CLOCK_TXFROMRX
; break;
7849 default: new_line
.clock_type
= CLOCK_DEFAULT
;
7852 new_line
.clock_rate
= info
->params
.clock_speed
;
7853 new_line
.loopback
= info
->params
.loopback
? 1:0;
7855 if (copy_to_user(line
, &new_line
, size
))
7859 case IF_IFACE_SYNC_SERIAL
: /* set sync_serial_settings */
7861 if(!capable(CAP_NET_ADMIN
))
7863 if (copy_from_user(&new_line
, line
, size
))
7866 switch (new_line
.clock_type
)
7868 case CLOCK_EXT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
; break;
7869 case CLOCK_TXFROMRX
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
; break;
7870 case CLOCK_INT
: flags
= HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
; break;
7871 case CLOCK_TXINT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
; break;
7872 case CLOCK_DEFAULT
: flags
= info
->params
.flags
&
7873 (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7874 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7875 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7876 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
); break;
7877 default: return -EINVAL
;
7880 if (new_line
.loopback
!= 0 && new_line
.loopback
!= 1)
7883 info
->params
.flags
&= ~(HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7884 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7885 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7886 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7887 info
->params
.flags
|= flags
;
7889 info
->params
.loopback
= new_line
.loopback
;
7891 if (flags
& (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
))
7892 info
->params
.clock_speed
= new_line
.clock_rate
;
7894 info
->params
.clock_speed
= 0;
7896 /* if network interface up, reprogram hardware */
7898 mgsl_program_hw(info
);
7902 return hdlc_ioctl(dev
, ifr
, cmd
);
7907 * called by network layer when transmit timeout is detected
7909 * dev pointer to network device structure
7911 static void hdlcdev_tx_timeout(struct net_device
*dev
)
7913 struct mgsl_struct
*info
= dev_to_port(dev
);
7914 unsigned long flags
;
7916 if (debug_level
>= DEBUG_LEVEL_INFO
)
7917 printk("hdlcdev_tx_timeout(%s)\n",dev
->name
);
7919 dev
->stats
.tx_errors
++;
7920 dev
->stats
.tx_aborted_errors
++;
7922 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7923 usc_stop_transmitter(info
);
7924 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7926 netif_wake_queue(dev
);
7930 * called by device driver when transmit completes
7931 * reenable network layer transmit if stopped
7933 * info pointer to device instance information
7935 static void hdlcdev_tx_done(struct mgsl_struct
*info
)
7937 if (netif_queue_stopped(info
->netdev
))
7938 netif_wake_queue(info
->netdev
);
7942 * called by device driver when frame received
7943 * pass frame to network layer
7945 * info pointer to device instance information
7946 * buf pointer to buffer contianing frame data
7947 * size count of data bytes in buf
7949 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
)
7951 struct sk_buff
*skb
= dev_alloc_skb(size
);
7952 struct net_device
*dev
= info
->netdev
;
7954 if (debug_level
>= DEBUG_LEVEL_INFO
)
7955 printk("hdlcdev_rx(%s)\n", dev
->name
);
7958 printk(KERN_NOTICE
"%s: can't alloc skb, dropping packet\n",
7960 dev
->stats
.rx_dropped
++;
7964 memcpy(skb_put(skb
, size
), buf
, size
);
7966 skb
->protocol
= hdlc_type_trans(skb
, dev
);
7968 dev
->stats
.rx_packets
++;
7969 dev
->stats
.rx_bytes
+= size
;
7974 static const struct net_device_ops hdlcdev_ops
= {
7975 .ndo_open
= hdlcdev_open
,
7976 .ndo_stop
= hdlcdev_close
,
7977 .ndo_change_mtu
= hdlc_change_mtu
,
7978 .ndo_start_xmit
= hdlc_start_xmit
,
7979 .ndo_do_ioctl
= hdlcdev_ioctl
,
7980 .ndo_tx_timeout
= hdlcdev_tx_timeout
,
7984 * called by device driver when adding device instance
7985 * do generic HDLC initialization
7987 * info pointer to device instance information
7989 * returns 0 if success, otherwise error code
7991 static int hdlcdev_init(struct mgsl_struct
*info
)
7994 struct net_device
*dev
;
7997 /* allocate and initialize network and HDLC layer objects */
7999 if (!(dev
= alloc_hdlcdev(info
))) {
8000 printk(KERN_ERR
"%s:hdlc device allocation failure\n",__FILE__
);
8004 /* for network layer reporting purposes only */
8005 dev
->base_addr
= info
->io_base
;
8006 dev
->irq
= info
->irq_level
;
8007 dev
->dma
= info
->dma_level
;
8009 /* network layer callbacks and settings */
8010 dev
->netdev_ops
= &hdlcdev_ops
;
8011 dev
->watchdog_timeo
= 10 * HZ
;
8012 dev
->tx_queue_len
= 50;
8014 /* generic HDLC layer callbacks and settings */
8015 hdlc
= dev_to_hdlc(dev
);
8016 hdlc
->attach
= hdlcdev_attach
;
8017 hdlc
->xmit
= hdlcdev_xmit
;
8019 /* register objects with HDLC layer */
8020 if ((rc
= register_hdlc_device(dev
))) {
8021 printk(KERN_WARNING
"%s:unable to register hdlc device\n",__FILE__
);
8031 * called by device driver when removing device instance
8032 * do generic HDLC cleanup
8034 * info pointer to device instance information
8036 static void hdlcdev_exit(struct mgsl_struct
*info
)
8038 unregister_hdlc_device(info
->netdev
);
8039 free_netdev(info
->netdev
);
8040 info
->netdev
= NULL
;
8043 #endif /* CONFIG_HDLC */
8046 static int __devinit
synclink_init_one (struct pci_dev
*dev
,
8047 const struct pci_device_id
*ent
)
8049 struct mgsl_struct
*info
;
8051 if (pci_enable_device(dev
)) {
8052 printk("error enabling pci device %p\n", dev
);
8056 if (!(info
= mgsl_allocate_device())) {
8057 printk("can't allocate device instance data.\n");
8061 /* Copy user configuration info to device instance data */
8063 info
->io_base
= pci_resource_start(dev
, 2);
8064 info
->irq_level
= dev
->irq
;
8065 info
->phys_memory_base
= pci_resource_start(dev
, 3);
8067 /* Because veremap only works on page boundaries we must map
8068 * a larger area than is actually implemented for the LCR
8069 * memory range. We map a full page starting at the page boundary.
8071 info
->phys_lcr_base
= pci_resource_start(dev
, 0);
8072 info
->lcr_offset
= info
->phys_lcr_base
& (PAGE_SIZE
-1);
8073 info
->phys_lcr_base
&= ~(PAGE_SIZE
-1);
8075 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
8076 info
->io_addr_size
= 8;
8077 info
->irq_flags
= IRQF_SHARED
;
8079 if (dev
->device
== 0x0210) {
8080 /* Version 1 PCI9030 based universal PCI adapter */
8081 info
->misc_ctrl_value
= 0x007c4080;
8082 info
->hw_version
= 1;
8084 /* Version 0 PCI9050 based 5V PCI adapter
8085 * A PCI9050 bug prevents reading LCR registers if
8086 * LCR base address bit 7 is set. Maintain shadow
8087 * value so we can write to LCR misc control reg.
8089 info
->misc_ctrl_value
= 0x087e4546;
8090 info
->hw_version
= 0;
8093 mgsl_add_device(info
);
8098 static void __devexit
synclink_remove_one (struct pci_dev
*dev
)