release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/ata/pata_sl82c105.c

   1 /*
   2  * pata_sl82c105.c      - SL82C105 PATA for new ATA layer
   3  *                        (C) 2005 Red Hat Inc
   4  *
   5  * Based in part on linux/drivers/ide/pci/sl82c105.c
   6  *              SL82C105/Winbond 553 IDE driver
   7  *
   8  * and in part on the documentation and errata sheet
   9  *
  10  *
  11  * Note: The controller like many controllers has shared timings for
  12  * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
  13  * in the dma_stop function. Thus we actually don't need a set_dmamode
  14  * method as the PIO method is always called and will set the right PIO
  15  * timing parameters.
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/pci.h>
  21 #include <linux/init.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/delay.h>
  24 #include <scsi/scsi_host.h>
  25 #include <linux/libata.h>
  26
  27 #define DRV_NAME "pata_sl82c105"
  28 #define DRV_VERSION "0.3.3"
  29
  30 enum {
  31         /*
  32          * SL82C105 PCI config register 0x40 bits.
  33          */
  34         CTRL_IDE_IRQB   =       (1 << 30),
  35         CTRL_IDE_IRQA   =       (1 << 28),
  36         CTRL_LEGIRQ     =       (1 << 11),
  37         CTRL_P1F16      =       (1 << 5),
  38         CTRL_P1EN       =       (1 << 4),
  39         CTRL_P0F16      =       (1 << 1),
  40         CTRL_P0EN       =       (1 << 0)
  41 };
  42
  43 /**
  44  *      sl82c105_pre_reset              -       probe begin
  45  *      @link: ATA link
  46  *      @deadline: deadline jiffies for the operation
  47  *
  48  *      Set up cable type and use generic probe init
  49  */
  50
  51 static int sl82c105_pre_reset(struct ata_link *link, unsigned long deadline)
  52 {
  53         static const struct pci_bits sl82c105_enable_bits[] = {
  54                 { 0x40, 1, 0x01, 0x01 },
  55                 { 0x40, 1, 0x10, 0x10 }
  56         };
  57         struct ata_port *ap = link->ap;
  58         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  59
  60         if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no]))
  61                 return -ENOENT;
  62         return ata_sff_prereset(link, deadline);
  63 }
  64
  65
  66 /**
  67  *      sl82c105_configure_piomode      -       set chip PIO timing
  68  *      @ap: ATA interface
  69  *      @adev: ATA device
  70  *      @pio: PIO mode
  71  *
  72  *      Called to do the PIO mode setup. Our timing registers are shared
  73  *      so a configure_dmamode call will undo any work we do here and vice
  74  *      versa
  75  */
  76
  77 static void sl82c105_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
  78 {
  79         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  80         static u16 pio_timing[5] = {
  81                 0x50D, 0x407, 0x304, 0x242, 0x240
  82         };
  83         u16 dummy;
  84         int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
  85
  86         pci_write_config_word(pdev, timing, pio_timing[pio]);
  87         /* Can we lose this oddity of the old driver */
  88         pci_read_config_word(pdev, timing, &dummy);
  89 }
  90
  91 /**
  92  *      sl82c105_set_piomode    -       set initial PIO mode data
  93  *      @ap: ATA interface
  94  *      @adev: ATA device
  95  *
  96  *      Called to do the PIO mode setup. Our timing registers are shared
  97  *      but we want to set the PIO timing by default.
  98  */
  99
 100 static void sl82c105_set_piomode(struct ata_port *ap, struct ata_device *adev)
 101 {
 102         sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
 103 }
 104
 105 /**
 106  *      sl82c105_configure_dmamode      -       set DMA mode in chip
 107  *      @ap: ATA interface
 108  *      @adev: ATA device
 109  *
 110  *      Load DMA cycle times into the chip ready for a DMA transfer
 111  *      to occur.
 112  */
 113
 114 static void sl82c105_configure_dmamode(struct ata_port *ap, struct ata_device *adev)
 115 {
 116         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 117         static u16 dma_timing[3] = {
 118                 0x707, 0x201, 0x200
 119         };
 120         u16 dummy;
 121         int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
 122         int dma = adev->dma_mode - XFER_MW_DMA_0;
 123
 124         pci_write_config_word(pdev, timing, dma_timing[dma]);
 125         /* Can we lose this oddity of the old driver */
 126         pci_read_config_word(pdev, timing, &dummy);
 127 }
 128
 129 /**
 130  *      sl82c105_reset_engine   -       Reset the DMA engine
 131  *      @ap: ATA interface
 132  *
 133  *      The sl82c105 has some serious problems with the DMA engine
 134  *      when transfers don't run as expected or ATAPI is used. The
 135  *      recommended fix is to reset the engine each use using a chip
 136  *      test register.
 137  */
 138
 139 static void sl82c105_reset_engine(struct ata_port *ap)
 140 {
 141         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 142         u16 val;
 143
 144         pci_read_config_word(pdev, 0x7E, &val);
 145         pci_write_config_word(pdev, 0x7E, val | 4);
 146         pci_write_config_word(pdev, 0x7E, val & ~4);
 147 }
 148
 149
 150 static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
 151 {
 152         struct ata_port *ap = qc->ap;
 153
 154         udelay(100);
 155         sl82c105_reset_engine(ap);
 156         udelay(100);
 157
 158         /* Set the clocks for DMA */
 159         sl82c105_configure_dmamode(ap, qc->dev);
 160         /* Activate DMA */
 161         ata_bmdma_start(qc);
 162 }
 163
 164 /**
 165  *      sl82c105_bmdma_end              -       DMA engine stop
 166  *      @qc: ATA command
 167  *
 168  *      Reset the DMA engine each use as recommended by the errata
 169  *      document.
 170  *
 171  *      This function is also called to turn off DMA when a timeout occurs
 172  *      during DMA operation. In both cases we need to reset the engine,
 173  *      so no actual eng_timeout handler is required.
 174  *
 175  *      We assume bmdma_stop is always called if bmdma_start as called. If
 176  *      not then we may need to wrap qc_issue.
 177  */
 178
 179 static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc)
 180 {
 181         struct ata_port *ap = qc->ap;
 182
 183         ata_bmdma_stop(qc);
 184         sl82c105_reset_engine(ap);
 185         udelay(100);
 186
 187         /* This will redo the initial setup of the DMA device to matching
 188            PIO timings */
 189         sl82c105_set_piomode(ap, qc->dev);
 190 }
 191
 192 /**
 193  *      sl82c105_qc_defer       -       implement serialization
 194  *      @qc: command
 195  *
 196  *      We must issue one command per host not per channel because
 197  *      of the reset bug.
 198  *
 199  *      Q: is the scsi host lock sufficient ?
 200  */
 201
 202 static int sl82c105_qc_defer(struct ata_queued_cmd *qc)
 203 {
 204         struct ata_host *host = qc->ap->host;
 205         struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
 206         int rc;
 207
 208         /* First apply the usual rules */
 209         rc = ata_std_qc_defer(qc);
 210         if (rc != 0)
 211                 return rc;
 212
 213         /* Now apply serialization rules. Only allow a command if the
 214            other channel state machine is idle */
 215         if (alt && alt->qc_active)
 216                 return  ATA_DEFER_PORT;
 217         return 0;
 218 }
 219
 220 static struct scsi_host_template sl82c105_sht = {
 221         ATA_BMDMA_SHT(DRV_NAME),
 222 };
 223
 224 static struct ata_port_operations sl82c105_port_ops = {
 225         .inherits       = &ata_bmdma_port_ops,
 226         .qc_defer       = sl82c105_qc_defer,
 227         .bmdma_start    = sl82c105_bmdma_start,
 228         .bmdma_stop     = sl82c105_bmdma_stop,
 229         .cable_detect   = ata_cable_40wire,
 230         .set_piomode    = sl82c105_set_piomode,
 231         .prereset       = sl82c105_pre_reset,
 232 };
 233
 234 /**
 235  *      sl82c105_bridge_revision        -       find bridge version
 236  *      @pdev: PCI device for the ATA function
 237  *
 238  *      Locates the PCI bridge associated with the ATA function and
 239  *      providing it is a Winbond 553 reports the revision. If it cannot
 240  *      find a revision or the right device it returns -1
 241  */
 242
 243 static int sl82c105_bridge_revision(struct pci_dev *pdev)
 244 {
 245         struct pci_dev *bridge;
 246
 247         /*
 248          * The bridge should be part of the same device, but function 0.
 249          */
 250         bridge = pci_get_slot(pdev->bus,
 251                                PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
 252         if (!bridge)
 253                 return -1;
 254
 255         /*
 256          * Make sure it is a Winbond 553 and is an ISA bridge.
 257          */
 258         if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
 259             bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
 260             bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
 261                 pci_dev_put(bridge);
 262                 return -1;
 263         }
 264         /*
 265          * We need to find function 0's revision, not function 1
 266          */
 267         pci_dev_put(bridge);
 268         return bridge->revision;
 269 }
 270
 271
 272 static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 273 {
 274         static const struct ata_port_info info_dma = {
 275                 .flags = ATA_FLAG_SLAVE_POSS,
 276                 .pio_mask = ATA_PIO4,
 277                 .mwdma_mask = ATA_MWDMA2,
 278                 .port_ops = &sl82c105_port_ops
 279         };
 280         static const struct ata_port_info info_early = {
 281                 .flags = ATA_FLAG_SLAVE_POSS,
 282                 .pio_mask = ATA_PIO4,
 283                 .port_ops = &sl82c105_port_ops
 284         };
 285         /* for now use only the first port */
 286         const struct ata_port_info *ppi[] = { &info_early,
 287                                                NULL };
 288         u32 val;
 289         int rev;
 290         int rc;
 291
 292         rc = pcim_enable_device(dev);
 293         if (rc)
 294                 return rc;
 295
 296         rev = sl82c105_bridge_revision(dev);
 297
 298         if (rev == -1)
 299                 dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Unable to find bridge, disabling DMA.\n");
 300         else if (rev <= 5)
 301                 dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Early bridge revision, no DMA available.\n");
 302         else
 303                 ppi[0] = &info_dma;
 304
 305         pci_read_config_dword(dev, 0x40, &val);
 306         val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
 307         pci_write_config_dword(dev, 0x40, val);
 308
 309         return ata_pci_bmdma_init_one(dev, ppi, &sl82c105_sht, NULL, 0);
 310 }
 311
 312 static const struct pci_device_id sl82c105[] = {
 313         { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), },
 314
 315         { },
 316 };
 317
 318 static struct pci_driver sl82c105_pci_driver = {
 319         .name           = DRV_NAME,
 320         .id_table       = sl82c105,
 321         .probe          = sl82c105_init_one,
 322         .remove         = ata_pci_remove_one
 323 };
 324
 325 static int __init sl82c105_init(void)
 326 {
 327         return pci_register_driver(&sl82c105_pci_driver);
 328 }
 329
 330 static void __exit sl82c105_exit(void)
 331 {
 332         pci_unregister_driver(&sl82c105_pci_driver);
 333 }
 334
 335 MODULE_AUTHOR("Alan Cox");
 336 MODULE_DESCRIPTION("low-level driver for Sl82c105");
 337 MODULE_LICENSE("GPL");
 338 MODULE_DEVICE_TABLE(pci, sl82c105);
 339 MODULE_VERSION(DRV_VERSION);
 340
 341 module_init(sl82c105_init);
 342 module_exit(sl82c105_exit);