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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / ata / ahci.c
blob0a55c25cb643c45beb5a9780d8d160df376a7323
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include "ahci.h"
50
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 };
57
58 enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
63 board_ahci_yes_fbs,
64
65 /* board IDs for specific chipsets in alphabetical order */
66 board_ahci_mcp65,
67 board_ahci_mcp77,
68 board_ahci_mcp89,
69 board_ahci_mv,
70 board_ahci_sb600,
71 board_ahci_sb700, /* for SB700 and SB800 */
72 board_ahci_vt8251,
73
74 /* aliases */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
78 board_ahci_mcp79 = board_ahci_mcp77,
79 };
80
81 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
82 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 #ifdef CONFIG_PM
89 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90 static int ahci_pci_device_resume(struct pci_dev *pdev);
91 #endif
92
93 static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95 };
96
97 static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
99 .hardreset = ahci_vt8251_hardreset,
100 };
101
102 static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_p5wdh_hardreset,
105 };
106
107 static struct ata_port_operations ahci_sb600_ops = {
108 .inherits = &ahci_ops,
109 .softreset = ahci_sb600_softreset,
110 .pmp_softreset = ahci_sb600_softreset,
111 };
112
113 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
114
115 static const struct ata_port_info ahci_port_info[] = {
116 /* by features */
117 [board_ahci] =
118 {
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
123 },
124 [board_ahci_ign_iferr] =
125 {
126 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
131 },
132 [board_ahci_nosntf] =
133 {
134 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
139 },
140 [board_ahci_yes_fbs] =
141 {
142 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
143 .flags = AHCI_FLAG_COMMON,
144 .pio_mask = ATA_PIO4,
145 .udma_mask = ATA_UDMA6,
146 .port_ops = &ahci_ops,
147 },
148 /* by chipsets */
149 [board_ahci_mcp65] =
150 {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
152 AHCI_HFLAG_YES_NCQ),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_mcp77] =
159 {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
165 },
166 [board_ahci_mcp89] =
167 {
168 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
169 .flags = AHCI_FLAG_COMMON,
170 .pio_mask = ATA_PIO4,
171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
173 },
174 [board_ahci_mv] =
175 {
176 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
177 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
178 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
179 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_ops,
183 },
184 [board_ahci_sb600] =
185 {
186 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
187 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
188 AHCI_HFLAG_32BIT_ONLY),
189 .flags = AHCI_FLAG_COMMON,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_sb600_ops,
193 },
194 [board_ahci_sb700] = /* for SB700 and SB800 */
195 {
196 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
197 .flags = AHCI_FLAG_COMMON,
198 .pio_mask = ATA_PIO4,
199 .udma_mask = ATA_UDMA6,
200 .port_ops = &ahci_sb600_ops,
201 },
202 [board_ahci_vt8251] =
203 {
204 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
205 .flags = AHCI_FLAG_COMMON,
206 .pio_mask = ATA_PIO4,
207 .udma_mask = ATA_UDMA6,
208 .port_ops = &ahci_vt8251_ops,
209 },
210 };
211
212 static const struct pci_device_id ahci_pci_tbl[] = {
213 /* Intel */
214 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
215 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
216 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
217 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
218 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
219 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
220 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
221 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
222 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
223 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
224 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
225 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
226 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
227 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
228 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
229 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
232 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
233 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
234 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
237 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
238 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
239 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
240 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
241 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
242 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
243 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
244 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
245 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
246 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
247 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
248 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
249 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
250 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
251 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
252 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
253 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
254 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
255 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
256 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
257 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
258 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
259 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
260 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
261 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
262 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
263
264 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
265 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
266 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
267
268 /* ATI */
269 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
270 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
271 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
272 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
273 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
274 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
275 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
276
277 /* AMD */
278 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
279 /* AMD is using RAID class only for ahci controllers */
280 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
281 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
282
283 /* VIA */
284 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
285 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
286
287 /* NVIDIA */
288 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
289 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
290 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
292 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
293 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
294 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
295 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
297 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
309 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
325 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
349 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
361 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
372
373 /* SiS */
374 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
375 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
376 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
377
378 /* Marvell */
379 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
380 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
381 { PCI_DEVICE(0x1b4b, 0x9123),
382 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
383
384 /* Promise */
385 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
386
387 /* ASMedia */
388 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci },
389 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci },
390 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci },
391 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci },
392
393 /* Generic, PCI class code for AHCI */
394 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
395 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
396
397 { } /* terminate list */
398 };
399
400
401 static struct pci_driver ahci_pci_driver = {
402 .name = DRV_NAME,
403 .id_table = ahci_pci_tbl,
404 .probe = ahci_init_one,
405 .remove = ata_pci_remove_one,
406 #ifdef CONFIG_PM
407 .suspend = ahci_pci_device_suspend,
408 .resume = ahci_pci_device_resume,
409 #endif
410 };
411
412 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
413 static int marvell_enable;
414 #else
415 static int marvell_enable = 1;
416 #endif
417 module_param(marvell_enable, int, 0644);
418 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
419
420
421 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
422 struct ahci_host_priv *hpriv)
423 {
424 unsigned int force_port_map = 0;
425 unsigned int mask_port_map = 0;
426
427 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
428 dev_info(&pdev->dev, "JMB361 has only one port\n");
429 force_port_map = 1;
430 }
431
432 /*
433 * Temporary Marvell 6145 hack: PATA port presence
434 * is asserted through the standard AHCI port
435 * presence register, as bit 4 (counting from 0)
436 */
437 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
438 if (pdev->device == 0x6121)
439 mask_port_map = 0x3;
440 else
441 mask_port_map = 0xf;
442 dev_info(&pdev->dev,
443 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
444 }
445
446 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
447 mask_port_map);
448 }
449
450 static int ahci_pci_reset_controller(struct ata_host *host)
451 {
452 struct pci_dev *pdev = to_pci_dev(host->dev);
453
454 ahci_reset_controller(host);
455
456 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
457 struct ahci_host_priv *hpriv = host->private_data;
458 u16 tmp16;
459
460 /* configure PCS */
461 pci_read_config_word(pdev, 0x92, &tmp16);
462 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
463 tmp16 |= hpriv->port_map;
464 pci_write_config_word(pdev, 0x92, tmp16);
465 }
466 }
467
468 return 0;
469 }
470
471 static void ahci_pci_init_controller(struct ata_host *host)
472 {
473 struct ahci_host_priv *hpriv = host->private_data;
474 struct pci_dev *pdev = to_pci_dev(host->dev);
475 void __iomem *port_mmio;
476 u32 tmp;
477 int mv;
478
479 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
480 if (pdev->device == 0x6121)
481 mv = 2;
482 else
483 mv = 4;
484 port_mmio = __ahci_port_base(host, mv);
485
486 writel(0, port_mmio + PORT_IRQ_MASK);
487
488 /* clear port IRQ */
489 tmp = readl(port_mmio + PORT_IRQ_STAT);
490 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
491 if (tmp)
492 writel(tmp, port_mmio + PORT_IRQ_STAT);
493 }
494
495 ahci_init_controller(host);
496 }
497
498 static int ahci_sb600_check_ready(struct ata_link *link)
499 {
500 void __iomem *port_mmio = ahci_port_base(link->ap);
501 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
502 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
503
504 /*
505 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
506 * which can save timeout delay.
507 */
508 if (irq_status & PORT_IRQ_BAD_PMP)
509 return -EIO;
510
511 return ata_check_ready(status);
512 }
513
514 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
515 unsigned long deadline)
516 {
517 struct ata_port *ap = link->ap;
518 void __iomem *port_mmio = ahci_port_base(ap);
519 int pmp = sata_srst_pmp(link);
520 int rc;
521 u32 irq_sts;
522
523 DPRINTK("ENTER\n");
524
525 rc = ahci_do_softreset(link, class, pmp, deadline,
526 ahci_sb600_check_ready);
527
528 /*
529 * Soft reset fails on some ATI chips with IPMS set when PMP
530 * is enabled but SATA HDD/ODD is connected to SATA port,
531 * do soft reset again to port 0.
532 */
533 if (rc == -EIO) {
534 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
535 if (irq_sts & PORT_IRQ_BAD_PMP) {
536 ata_link_printk(link, KERN_WARNING,
537 "applying SB600 PMP SRST workaround "
538 "and retrying\n");
539 rc = ahci_do_softreset(link, class, 0, deadline,
540 ahci_check_ready);
541 }
542 }
543
544 return rc;
545 }
546
547 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
548 unsigned long deadline)
549 {
550 struct ata_port *ap = link->ap;
551 bool online;
552 int rc;
553
554 DPRINTK("ENTER\n");
555
556 ahci_stop_engine(ap);
557
558 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
559 deadline, &online, NULL);
560
561 ahci_start_engine(ap);
562
563 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
564
565 /* vt8251 doesn't clear BSY on signature FIS reception,
566 * request follow-up softreset.
567 */
568 return online ? -EAGAIN : rc;
569 }
570
571 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
572 unsigned long deadline)
573 {
574 struct ata_port *ap = link->ap;
575 struct ahci_port_priv *pp = ap->private_data;
576 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
577 struct ata_taskfile tf;
578 bool online;
579 int rc;
580
581 ahci_stop_engine(ap);
582
583 /* clear D2H reception area to properly wait for D2H FIS */
584 ata_tf_init(link->device, &tf);
585 tf.command = 0x80;
586 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
587
588 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
589 deadline, &online, NULL);
590
591 ahci_start_engine(ap);
592
593 if (online) {
594 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
595 ahci_check_ready);
596 if (rc)
597 ahci_kick_engine(ap);
598 }
599 return rc;
600 }
601
602 #ifdef CONFIG_PM
603 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
604 {
605 struct ata_host *host = dev_get_drvdata(&pdev->dev);
606 struct ahci_host_priv *hpriv = host->private_data;
607 void __iomem *mmio = hpriv->mmio;
608 u32 ctl;
609
610 if (mesg.event & PM_EVENT_SUSPEND &&
611 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
612 dev_printk(KERN_ERR, &pdev->dev,
613 "BIOS update required for suspend/resume\n");
614 return -EIO;
615 }
616
617 if (mesg.event & PM_EVENT_SLEEP) {
618 /* AHCI spec rev1.1 section 8.3.3:
619 * Software must disable interrupts prior to requesting a
620 * transition of the HBA to D3 state.
621 */
622 ctl = readl(mmio + HOST_CTL);
623 ctl &= ~HOST_IRQ_EN;
624 writel(ctl, mmio + HOST_CTL);
625 readl(mmio + HOST_CTL); /* flush */
626 }
627
628 return ata_pci_device_suspend(pdev, mesg);
629 }
630
631 static int ahci_pci_device_resume(struct pci_dev *pdev)
632 {
633 struct ata_host *host = dev_get_drvdata(&pdev->dev);
634 int rc;
635
636 rc = ata_pci_device_do_resume(pdev);
637 if (rc)
638 return rc;
639
640 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
641 rc = ahci_pci_reset_controller(host);
642 if (rc)
643 return rc;
644
645 ahci_pci_init_controller(host);
646 }
647
648 ata_host_resume(host);
649
650 return 0;
651 }
652 #endif
653
654 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
655 {
656 int rc;
657
658 if (using_dac &&
659 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
660 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
661 if (rc) {
662 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
663 if (rc) {
664 dev_printk(KERN_ERR, &pdev->dev,
665 "64-bit DMA enable failed\n");
666 return rc;
667 }
668 }
669 } else {
670 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
671 if (rc) {
672 dev_printk(KERN_ERR, &pdev->dev,
673 "32-bit DMA enable failed\n");
674 return rc;
675 }
676 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
677 if (rc) {
678 dev_printk(KERN_ERR, &pdev->dev,
679 "32-bit consistent DMA enable failed\n");
680 return rc;
681 }
682 }
683 return 0;
684 }
685
686 static void ahci_pci_print_info(struct ata_host *host)
687 {
688 struct pci_dev *pdev = to_pci_dev(host->dev);
689 u16 cc;
690 const char *scc_s;
691
692 pci_read_config_word(pdev, 0x0a, &cc);
693 if (cc == PCI_CLASS_STORAGE_IDE)
694 scc_s = "IDE";
695 else if (cc == PCI_CLASS_STORAGE_SATA)
696 scc_s = "SATA";
697 else if (cc == PCI_CLASS_STORAGE_RAID)
698 scc_s = "RAID";
699 else
700 scc_s = "unknown";
701
702 ahci_print_info(host, scc_s);
703 }
704
705 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
706 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
707 * support PMP and the 4726 either directly exports the device
708 * attached to the first downstream port or acts as a hardware storage
709 * controller and emulate a single ATA device (can be RAID 0/1 or some
710 * other configuration).
711 *
712 * When there's no device attached to the first downstream port of the
713 * 4726, "Config Disk" appears, which is a pseudo ATA device to
714 * configure the 4726. However, ATA emulation of the device is very
715 * lame. It doesn't send signature D2H Reg FIS after the initial
716 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
717 *
718 * The following function works around the problem by always using
719 * hardreset on the port and not depending on receiving signature FIS
720 * afterward. If signature FIS isn't received soon, ATA class is
721 * assumed without follow-up softreset.
722 */
723 static void ahci_p5wdh_workaround(struct ata_host *host)
724 {
725 static struct dmi_system_id sysids[] = {
726 {
727 .ident = "P5W DH Deluxe",
728 .matches = {
729 DMI_MATCH(DMI_SYS_VENDOR,
730 "ASUSTEK COMPUTER INC"),
731 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
732 },
733 },
734 { }
735 };
736 struct pci_dev *pdev = to_pci_dev(host->dev);
737
738 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
739 dmi_check_system(sysids)) {
740 struct ata_port *ap = host->ports[1];
741
742 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
743 "Deluxe on-board SIMG4726 workaround\n");
744
745 ap->ops = &ahci_p5wdh_ops;
746 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
747 }
748 }
749
750 /* only some SB600 ahci controllers can do 64bit DMA */
751 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
752 {
753 static const struct dmi_system_id sysids[] = {
754 /*
755 * The oldest version known to be broken is 0901 and
756 * working is 1501 which was released on 2007-10-26.
757 * Enable 64bit DMA on 1501 and anything newer.
758 *
759 * Please read bko#9412 for more info.
760 */
761 {
762 .ident = "ASUS M2A-VM",
763 .matches = {
764 DMI_MATCH(DMI_BOARD_VENDOR,
765 "ASUSTeK Computer INC."),
766 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
767 },
768 .driver_data = "20071026", /* yyyymmdd */
769 },
770 /*
771 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
772 * support 64bit DMA.
773 *
774 * BIOS versions earlier than 1.5 had the Manufacturer DMI
775 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
776 * This spelling mistake was fixed in BIOS version 1.5, so
777 * 1.5 and later have the Manufacturer as
778 * "MICRO-STAR INTERNATIONAL CO.,LTD".
779 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
780 *
781 * BIOS versions earlier than 1.9 had a Board Product Name
782 * DMI field of "MS-7376". This was changed to be
783 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
784 * match on DMI_BOARD_NAME of "MS-7376".
785 */
786 {
787 .ident = "MSI K9A2 Platinum",
788 .matches = {
789 DMI_MATCH(DMI_BOARD_VENDOR,
790 "MICRO-STAR INTER"),
791 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
792 },
793 },
794 { }
795 };
796 const struct dmi_system_id *match;
797 int year, month, date;
798 char buf[9];
799
800 match = dmi_first_match(sysids);
801 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
802 !match)
803 return false;
804
805 if (!match->driver_data)
806 goto enable_64bit;
807
808 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
809 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
810
811 if (strcmp(buf, match->driver_data) >= 0)
812 goto enable_64bit;
813 else {
814 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
815 "forcing 32bit DMA, update BIOS\n", match->ident);
816 return false;
817 }
818
819 enable_64bit:
820 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
821 match->ident);
822 return true;
823 }
824
825 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
826 {
827 static const struct dmi_system_id broken_systems[] = {
828 {
829 .ident = "HP Compaq nx6310",
830 .matches = {
831 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
832 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
833 },
834 /* PCI slot number of the controller */
835 .driver_data = (void *)0x1FUL,
836 },
837 {
838 .ident = "HP Compaq 6720s",
839 .matches = {
840 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
841 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
842 },
843 /* PCI slot number of the controller */
844 .driver_data = (void *)0x1FUL,
845 },
846
847 { } /* terminate list */
848 };
849 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
850
851 if (dmi) {
852 unsigned long slot = (unsigned long)dmi->driver_data;
853 /* apply the quirk only to on-board controllers */
854 return slot == PCI_SLOT(pdev->devfn);
855 }
856
857 return false;
858 }
859
860 static bool ahci_broken_suspend(struct pci_dev *pdev)
861 {
862 static const struct dmi_system_id sysids[] = {
863 /*
864 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
865 * to the harddisk doesn't become online after
866 * resuming from STR. Warn and fail suspend.
867 *
868 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
869 *
870 * Use dates instead of versions to match as HP is
871 * apparently recycling both product and version
872 * strings.
873 *
874 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
875 */
876 {
877 .ident = "dv4",
878 .matches = {
879 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
880 DMI_MATCH(DMI_PRODUCT_NAME,
881 "HP Pavilion dv4 Notebook PC"),
882 },
883 .driver_data = "20090105", /* F.30 */
884 },
885 {
886 .ident = "dv5",
887 .matches = {
888 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
889 DMI_MATCH(DMI_PRODUCT_NAME,
890 "HP Pavilion dv5 Notebook PC"),
891 },
892 .driver_data = "20090506", /* F.16 */
893 },
894 {
895 .ident = "dv6",
896 .matches = {
897 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
898 DMI_MATCH(DMI_PRODUCT_NAME,
899 "HP Pavilion dv6 Notebook PC"),
900 },
901 .driver_data = "20090423", /* F.21 */
902 },
903 {
904 .ident = "HDX18",
905 .matches = {
906 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
907 DMI_MATCH(DMI_PRODUCT_NAME,
908 "HP HDX18 Notebook PC"),
909 },
910 .driver_data = "20090430", /* F.23 */
911 },
912 /*
913 * Acer eMachines G725 has the same problem. BIOS
914 * V1.03 is known to be broken. V3.04 is known to
915 * work. Inbetween, there are V1.06, V2.06 and V3.03
916 * that we don't have much idea about. For now,
917 * blacklist anything older than V3.04.
918 *
919 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
920 */
921 {
922 .ident = "G725",
923 .matches = {
924 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
925 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
926 },
927 .driver_data = "20091216", /* V3.04 */
928 },
929 { } /* terminate list */
930 };
931 const struct dmi_system_id *dmi = dmi_first_match(sysids);
932 int year, month, date;
933 char buf[9];
934
935 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
936 return false;
937
938 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
939 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
940
941 return strcmp(buf, dmi->driver_data) < 0;
942 }
943
944 static bool ahci_broken_online(struct pci_dev *pdev)
945 {
946 #define ENCODE_BUSDEVFN(bus, slot, func) \
947 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
948 static const struct dmi_system_id sysids[] = {
949 /*
950 * There are several gigabyte boards which use
951 * SIMG5723s configured as hardware RAID. Certain
952 * 5723 firmware revisions shipped there keep the link
953 * online but fail to answer properly to SRST or
954 * IDENTIFY when no device is attached downstream
955 * causing libata to retry quite a few times leading
956 * to excessive detection delay.
957 *
958 * As these firmwares respond to the second reset try
959 * with invalid device signature, considering unknown
960 * sig as offline works around the problem acceptably.
961 */
962 {
963 .ident = "EP45-DQ6",
964 .matches = {
965 DMI_MATCH(DMI_BOARD_VENDOR,
966 "Gigabyte Technology Co., Ltd."),
967 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
968 },
969 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
970 },
971 {
972 .ident = "EP45-DS5",
973 .matches = {
974 DMI_MATCH(DMI_BOARD_VENDOR,
975 "Gigabyte Technology Co., Ltd."),
976 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
977 },
978 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
979 },
980 { } /* terminate list */
981 };
982 #undef ENCODE_BUSDEVFN
983 const struct dmi_system_id *dmi = dmi_first_match(sysids);
984 unsigned int val;
985
986 if (!dmi)
987 return false;
988
989 val = (unsigned long)dmi->driver_data;
990
991 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
992 }
993
994 #ifdef CONFIG_ATA_ACPI
995 static void ahci_gtf_filter_workaround(struct ata_host *host)
996 {
997 static const struct dmi_system_id sysids[] = {
998 /*
999 * Aspire 3810T issues a bunch of SATA enable commands
1000 * via _GTF including an invalid one and one which is
1001 * rejected by the device. Among the successful ones
1002 * is FPDMA non-zero offset enable which when enabled
1003 * only on the drive side leads to NCQ command
1004 * failures. Filter it out.
1005 */
1006 {
1007 .ident = "Aspire 3810T",
1008 .matches = {
1009 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1010 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1011 },
1012 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1013 },
1014 { }
1015 };
1016 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1017 unsigned int filter;
1018 int i;
1019
1020 if (!dmi)
1021 return;
1022
1023 filter = (unsigned long)dmi->driver_data;
1024 dev_printk(KERN_INFO, host->dev,
1025 "applying extra ACPI _GTF filter 0x%x for %s\n",
1026 filter, dmi->ident);
1027
1028 for (i = 0; i < host->n_ports; i++) {
1029 struct ata_port *ap = host->ports[i];
1030 struct ata_link *link;
1031 struct ata_device *dev;
1032
1033 ata_for_each_link(link, ap, EDGE)
1034 ata_for_each_dev(dev, link, ALL)
1035 dev->gtf_filter |= filter;
1036 }
1037 }
1038 #else
1039 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1040 {}
1041 #endif
1042
1043 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1044 {
1045 static int printed_version;
1046 unsigned int board_id = ent->driver_data;
1047 struct ata_port_info pi = ahci_port_info[board_id];
1048 const struct ata_port_info *ppi[] = { &pi, NULL };
1049 struct device *dev = &pdev->dev;
1050 struct ahci_host_priv *hpriv;
1051 struct ata_host *host;
1052 int n_ports, i, rc;
1053
1054 VPRINTK("ENTER\n");
1055
1056 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1057
1058 if (!printed_version++)
1059 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1060
1061 /* The AHCI driver can only drive the SATA ports, the PATA driver
1062 can drive them all so if both drivers are selected make sure
1063 AHCI stays out of the way */
1064 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1065 return -ENODEV;
1066
1067 /*
1068 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1069 * ahci, use ata_generic instead.
1070 */
1071 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1072 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1073 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1074 pdev->subsystem_device == 0xcb89)
1075 return -ENODEV;
1076
1077 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1078 * At the moment, we can only use the AHCI mode. Let the users know
1079 * that for SAS drives they're out of luck.
1080 */
1081 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1082 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
1083 "can only drive SATA devices with this driver\n");
1084
1085 /* acquire resources */
1086 rc = pcim_enable_device(pdev);
1087 if (rc)
1088 return rc;
1089
1090 /* AHCI controllers often implement SFF compatible interface.
1091 * Grab all PCI BARs just in case.
1092 */
1093 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1094 if (rc == -EBUSY)
1095 pcim_pin_device(pdev);
1096 if (rc)
1097 return rc;
1098
1099 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1100 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1101 u8 map;
1102
1103 /* ICH6s share the same PCI ID for both piix and ahci
1104 * modes. Enabling ahci mode while MAP indicates
1105 * combined mode is a bad idea. Yield to ata_piix.
1106 */
1107 pci_read_config_byte(pdev, ICH_MAP, &map);
1108 if (map & 0x3) {
1109 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
1110 "combined mode, can't enable AHCI mode\n");
1111 return -ENODEV;
1112 }
1113 }
1114
1115 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1116 if (!hpriv)
1117 return -ENOMEM;
1118 hpriv->flags |= (unsigned long)pi.private_data;
1119
1120 /* MCP65 revision A1 and A2 can't do MSI */
1121 if (board_id == board_ahci_mcp65 &&
1122 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1123 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1124
1125 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1126 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1127
1128 /* only some SB600s can do 64bit DMA */
1129 if (ahci_sb600_enable_64bit(pdev))
1130 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1131
1132 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1133 pci_intx(pdev, 1);
1134
1135 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1136
1137 /* save initial config */
1138 ahci_pci_save_initial_config(pdev, hpriv);
1139
1140 /* prepare host */
1141 if (hpriv->cap & HOST_CAP_NCQ) {
1142 pi.flags |= ATA_FLAG_NCQ;
1143 /*
1144 * Auto-activate optimization is supposed to be
1145 * supported on all AHCI controllers indicating NCQ
1146 * capability, but it seems to be broken on some
1147 * chipsets including NVIDIAs.
1148 */
1149 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1150 pi.flags |= ATA_FLAG_FPDMA_AA;
1151 }
1152
1153 if (hpriv->cap & HOST_CAP_PMP)
1154 pi.flags |= ATA_FLAG_PMP;
1155
1156 ahci_set_em_messages(hpriv, &pi);
1157
1158 if (ahci_broken_system_poweroff(pdev)) {
1159 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1160 dev_info(&pdev->dev,
1161 "quirky BIOS, skipping spindown on poweroff\n");
1162 }
1163
1164 if (ahci_broken_suspend(pdev)) {
1165 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1166 dev_printk(KERN_WARNING, &pdev->dev,
1167 "BIOS update required for suspend/resume\n");
1168 }
1169
1170 if (ahci_broken_online(pdev)) {
1171 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1172 dev_info(&pdev->dev,
1173 "online status unreliable, applying workaround\n");
1174 }
1175
1176 /* CAP.NP sometimes indicate the index of the last enabled
1177 * port, at other times, that of the last possible port, so
1178 * determining the maximum port number requires looking at
1179 * both CAP.NP and port_map.
1180 */
1181 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1182
1183 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1184 if (!host)
1185 return -ENOMEM;
1186 host->private_data = hpriv;
1187
1188 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1189 host->flags |= ATA_HOST_PARALLEL_SCAN;
1190 else
1191 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1192
1193 if (pi.flags & ATA_FLAG_EM)
1194 ahci_reset_em(host);
1195
1196 for (i = 0; i < host->n_ports; i++) {
1197 struct ata_port *ap = host->ports[i];
1198
1199 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1200 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1201 0x100 + ap->port_no * 0x80, "port");
1202
1203 /* set initial link pm policy */
1204 ap->pm_policy = NOT_AVAILABLE;
1205
1206 /* set enclosure management message type */
1207 if (ap->flags & ATA_FLAG_EM)
1208 ap->em_message_type = hpriv->em_msg_type;
1209
1210
1211 /* disabled/not-implemented port */
1212 if (!(hpriv->port_map & (1 << i)))
1213 ap->ops = &ata_dummy_port_ops;
1214 }
1215
1216 ahci_p5wdh_workaround(host);
1217
1218 /* apply gtf filter quirk */
1219 ahci_gtf_filter_workaround(host);
1220
1221 /* initialize adapter */
1222 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1223 if (rc)
1224 return rc;
1225
1226 rc = ahci_pci_reset_controller(host);
1227 if (rc)
1228 return rc;
1229
1230 ahci_pci_init_controller(host);
1231 ahci_pci_print_info(host);
1232
1233 pci_set_master(pdev);
1234 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1235 &ahci_sht);
1236 }
1237
1238 static int __init ahci_init(void)
1239 {
1240 return pci_register_driver(&ahci_pci_driver);
1241 }
1242
1243 static void __exit ahci_exit(void)
1244 {
1245 pci_unregister_driver(&ahci_pci_driver);
1246 }
1247
1248
1249 MODULE_AUTHOR("Jeff Garzik");
1250 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1251 MODULE_LICENSE("GPL");
1252 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1253 MODULE_VERSION(DRV_VERSION);
1254
1255 module_init(ahci_init);
1256 module_exit(ahci_exit);
Tomato firmware and modifications.