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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / sparc / mm / init_64.c
blob8869d63b09b5d1348c6a15741bdc98e9a20773f2
1 /*
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/initrd.h>
17 #include <linux/swap.h>
18 #include <linux/pagemap.h>
19 #include <linux/poison.h>
20 #include <linux/fs.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23 #include <linux/cache.h>
24 #include <linux/sort.h>
25 #include <linux/percpu.h>
26 #include <linux/memblock.h>
27 #include <linux/mmzone.h>
28 #include <linux/gfp.h>
29
30 #include <asm/head.h>
31 #include <asm/system.h>
32 #include <asm/page.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
37 #include <asm/io.h>
38 #include <asm/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
41 #include <asm/dma.h>
42 #include <asm/starfire.h>
43 #include <asm/tlb.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
46 #include <asm/tsb.h>
47 #include <asm/hypervisor.h>
48 #include <asm/prom.h>
49 #include <asm/mdesc.h>
50 #include <asm/cpudata.h>
51 #include <asm/irq.h>
52
53 #include "init_64.h"
54
55 unsigned long kern_linear_pte_xor[2] __read_mostly;
56
57 /* A bitmap, one bit for every 256MB of physical memory. If the bit
58 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
59 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
60 */
61 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
62
63 #ifndef CONFIG_DEBUG_PAGEALLOC
64 /* A special kernel TSB for 4MB and 256MB linear mappings.
65 * Space is allocated for this right after the trap table
66 * in arch/sparc64/kernel/head.S
67 */
68 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
69 #endif
70
71 #define MAX_BANKS 32
72
73 static struct linux_prom64_registers pavail[MAX_BANKS] __devinitdata;
74 static int pavail_ents __devinitdata;
75
76 static int cmp_p64(const void *a, const void *b)
77 {
78 const struct linux_prom64_registers *x = a, *y = b;
79
80 if (x->phys_addr > y->phys_addr)
81 return 1;
82 if (x->phys_addr < y->phys_addr)
83 return -1;
84 return 0;
85 }
86
87 static void __init read_obp_memory(const char *property,
88 struct linux_prom64_registers *regs,
89 int *num_ents)
90 {
91 int node = prom_finddevice("/memory");
92 int prop_size = prom_getproplen(node, property);
93 int ents, ret, i;
94
95 ents = prop_size / sizeof(struct linux_prom64_registers);
96 if (ents > MAX_BANKS) {
97 prom_printf("The machine has more %s property entries than "
98 "this kernel can support (%d).\n",
99 property, MAX_BANKS);
100 prom_halt();
101 }
102
103 ret = prom_getproperty(node, property, (char *) regs, prop_size);
104 if (ret == -1) {
105 prom_printf("Couldn't get %s property from /memory.\n");
106 prom_halt();
107 }
108
109 /* Sanitize what we got from the firmware, by page aligning
110 * everything.
111 */
112 for (i = 0; i < ents; i++) {
113 unsigned long base, size;
114
115 base = regs[i].phys_addr;
116 size = regs[i].reg_size;
117
118 size &= PAGE_MASK;
119 if (base & ~PAGE_MASK) {
120 unsigned long new_base = PAGE_ALIGN(base);
121
122 size -= new_base - base;
123 if ((long) size < 0L)
124 size = 0UL;
125 base = new_base;
126 }
127 if (size == 0UL) {
128 /* If it is empty, simply get rid of it.
129 * This simplifies the logic of the other
130 * functions that process these arrays.
131 */
132 memmove(&regs[i], &regs[i + 1],
133 (ents - i - 1) * sizeof(regs[0]));
134 i--;
135 ents--;
136 continue;
137 }
138 regs[i].phys_addr = base;
139 regs[i].reg_size = size;
140 }
141
142 *num_ents = ents;
143
144 sort(regs, ents, sizeof(struct linux_prom64_registers),
145 cmp_p64, NULL);
146 }
147
148 unsigned long sparc64_valid_addr_bitmap[VALID_ADDR_BITMAP_BYTES /
149 sizeof(unsigned long)];
150 EXPORT_SYMBOL(sparc64_valid_addr_bitmap);
151
152 /* Kernel physical address base and size in bytes. */
153 unsigned long kern_base __read_mostly;
154 unsigned long kern_size __read_mostly;
155
156 /* Initial ramdisk setup */
157 extern unsigned long sparc_ramdisk_image64;
158 extern unsigned int sparc_ramdisk_image;
159 extern unsigned int sparc_ramdisk_size;
160
161 struct page *mem_map_zero __read_mostly;
162 EXPORT_SYMBOL(mem_map_zero);
163
164 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
165
166 unsigned long sparc64_kern_pri_context __read_mostly;
167 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
168 unsigned long sparc64_kern_sec_context __read_mostly;
169
170 int num_kernel_image_mappings;
171
172 #ifdef CONFIG_DEBUG_DCFLUSH
173 atomic_t dcpage_flushes = ATOMIC_INIT(0);
174 #ifdef CONFIG_SMP
175 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
176 #endif
177 #endif
178
179 inline void flush_dcache_page_impl(struct page *page)
180 {
181 BUG_ON(tlb_type == hypervisor);
182 #ifdef CONFIG_DEBUG_DCFLUSH
183 atomic_inc(&dcpage_flushes);
184 #endif
185
186 #ifdef DCACHE_ALIASING_POSSIBLE
187 __flush_dcache_page(page_address(page),
188 ((tlb_type == spitfire) &&
189 page_mapping(page) != NULL));
190 #else
191 if (page_mapping(page) != NULL &&
192 tlb_type == spitfire)
193 __flush_icache_page(__pa(page_address(page)));
194 #endif
195 }
196
197 #define PG_dcache_dirty PG_arch_1
198 #define PG_dcache_cpu_shift 32UL
199 #define PG_dcache_cpu_mask \
200 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
201
202 #define dcache_dirty_cpu(page) \
203 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
204
205 static inline void set_dcache_dirty(struct page *page, int this_cpu)
206 {
207 unsigned long mask = this_cpu;
208 unsigned long non_cpu_bits;
209
210 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
211 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
212
213 __asm__ __volatile__("1:\n\t"
214 "ldx [%2], %%g7\n\t"
215 "and %%g7, %1, %%g1\n\t"
216 "or %%g1, %0, %%g1\n\t"
217 "casx [%2], %%g7, %%g1\n\t"
218 "cmp %%g7, %%g1\n\t"
219 "bne,pn %%xcc, 1b\n\t"
220 " nop"
221 : /* no outputs */
222 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
223 : "g1", "g7");
224 }
225
226 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
227 {
228 unsigned long mask = (1UL << PG_dcache_dirty);
229
230 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
231 "1:\n\t"
232 "ldx [%2], %%g7\n\t"
233 "srlx %%g7, %4, %%g1\n\t"
234 "and %%g1, %3, %%g1\n\t"
235 "cmp %%g1, %0\n\t"
236 "bne,pn %%icc, 2f\n\t"
237 " andn %%g7, %1, %%g1\n\t"
238 "casx [%2], %%g7, %%g1\n\t"
239 "cmp %%g7, %%g1\n\t"
240 "bne,pn %%xcc, 1b\n\t"
241 " nop\n"
242 "2:"
243 : /* no outputs */
244 : "r" (cpu), "r" (mask), "r" (&page->flags),
245 "i" (PG_dcache_cpu_mask),
246 "i" (PG_dcache_cpu_shift)
247 : "g1", "g7");
248 }
249
250 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
251 {
252 unsigned long tsb_addr = (unsigned long) ent;
253
254 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
255 tsb_addr = __pa(tsb_addr);
256
257 __tsb_insert(tsb_addr, tag, pte);
258 }
259
260 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
261 unsigned long _PAGE_SZBITS __read_mostly;
262
263 static void flush_dcache(unsigned long pfn)
264 {
265 struct page *page;
266
267 page = pfn_to_page(pfn);
268 if (page) {
269 unsigned long pg_flags;
270
271 pg_flags = page->flags;
272 if (pg_flags & (1UL << PG_dcache_dirty)) {
273 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
274 PG_dcache_cpu_mask);
275 int this_cpu = get_cpu();
276
277 /* This is just to optimize away some function calls
278 * in the SMP case.
279 */
280 if (cpu == this_cpu)
281 flush_dcache_page_impl(page);
282 else
283 smp_flush_dcache_page_impl(page, cpu);
284
285 clear_dcache_dirty_cpu(page, cpu);
286
287 put_cpu();
288 }
289 }
290 }
291
292 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
293 {
294 struct mm_struct *mm;
295 struct tsb *tsb;
296 unsigned long tag, flags;
297 unsigned long tsb_index, tsb_hash_shift;
298 pte_t pte = *ptep;
299
300 if (tlb_type != hypervisor) {
301 unsigned long pfn = pte_pfn(pte);
302
303 if (pfn_valid(pfn))
304 flush_dcache(pfn);
305 }
306
307 mm = vma->vm_mm;
308
309 tsb_index = MM_TSB_BASE;
310 tsb_hash_shift = PAGE_SHIFT;
311
312 spin_lock_irqsave(&mm->context.lock, flags);
313
314 #ifdef CONFIG_HUGETLB_PAGE
315 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
316 if ((tlb_type == hypervisor &&
317 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
318 (tlb_type != hypervisor &&
319 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
320 tsb_index = MM_TSB_HUGE;
321 tsb_hash_shift = HPAGE_SHIFT;
322 }
323 }
324 #endif
325
326 tsb = mm->context.tsb_block[tsb_index].tsb;
327 tsb += ((address >> tsb_hash_shift) &
328 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
329 tag = (address >> 22UL);
330 tsb_insert(tsb, tag, pte_val(pte));
331
332 spin_unlock_irqrestore(&mm->context.lock, flags);
333 }
334
335 void flush_dcache_page(struct page *page)
336 {
337 struct address_space *mapping;
338 int this_cpu;
339
340 if (tlb_type == hypervisor)
341 return;
342
343 /* Do not bother with the expensive D-cache flush if it
344 * is merely the zero page. The 'bigcore' testcase in GDB
345 * causes this case to run millions of times.
346 */
347 if (page == ZERO_PAGE(0))
348 return;
349
350 this_cpu = get_cpu();
351
352 mapping = page_mapping(page);
353 if (mapping && !mapping_mapped(mapping)) {
354 int dirty = test_bit(PG_dcache_dirty, &page->flags);
355 if (dirty) {
356 int dirty_cpu = dcache_dirty_cpu(page);
357
358 if (dirty_cpu == this_cpu)
359 goto out;
360 smp_flush_dcache_page_impl(page, dirty_cpu);
361 }
362 set_dcache_dirty(page, this_cpu);
363 } else {
364 /* We could delay the flush for the !page_mapping
365 * case too. But that case is for exec env/arg
366 * pages and those are %99 certainly going to get
367 * faulted into the tlb (and thus flushed) anyways.
368 */
369 flush_dcache_page_impl(page);
370 }
371
372 out:
373 put_cpu();
374 }
375 EXPORT_SYMBOL(flush_dcache_page);
376
377 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
378 {
379 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
380 if (tlb_type == spitfire) {
381 unsigned long kaddr;
382
383 /* This code only runs on Spitfire cpus so this is
384 * why we can assume _PAGE_PADDR_4U.
385 */
386 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
387 unsigned long paddr, mask = _PAGE_PADDR_4U;
388
389 if (kaddr >= PAGE_OFFSET)
390 paddr = kaddr & mask;
391 else {
392 pgd_t *pgdp = pgd_offset_k(kaddr);
393 pud_t *pudp = pud_offset(pgdp, kaddr);
394 pmd_t *pmdp = pmd_offset(pudp, kaddr);
395 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
396
397 paddr = pte_val(*ptep) & mask;
398 }
399 __flush_icache_page(paddr);
400 }
401 }
402 }
403 EXPORT_SYMBOL(flush_icache_range);
404
405 void mmu_info(struct seq_file *m)
406 {
407 if (tlb_type == cheetah)
408 seq_printf(m, "MMU Type\t: Cheetah\n");
409 else if (tlb_type == cheetah_plus)
410 seq_printf(m, "MMU Type\t: Cheetah+\n");
411 else if (tlb_type == spitfire)
412 seq_printf(m, "MMU Type\t: Spitfire\n");
413 else if (tlb_type == hypervisor)
414 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
415 else
416 seq_printf(m, "MMU Type\t: ???\n");
417
418 #ifdef CONFIG_DEBUG_DCFLUSH
419 seq_printf(m, "DCPageFlushes\t: %d\n",
420 atomic_read(&dcpage_flushes));
421 #ifdef CONFIG_SMP
422 seq_printf(m, "DCPageFlushesXC\t: %d\n",
423 atomic_read(&dcpage_flushes_xcall));
424 #endif /* CONFIG_SMP */
425 #endif /* CONFIG_DEBUG_DCFLUSH */
426 }
427
428 struct linux_prom_translation prom_trans[512] __read_mostly;
429 unsigned int prom_trans_ents __read_mostly;
430
431 unsigned long kern_locked_tte_data;
432
433 /* The obp translations are saved based on 8k pagesize, since obp can
434 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
435 * HI_OBP_ADDRESS range are handled in ktlb.S.
436 */
437 static inline int in_obp_range(unsigned long vaddr)
438 {
439 return (vaddr >= LOW_OBP_ADDRESS &&
440 vaddr < HI_OBP_ADDRESS);
441 }
442
443 static int cmp_ptrans(const void *a, const void *b)
444 {
445 const struct linux_prom_translation *x = a, *y = b;
446
447 if (x->virt > y->virt)
448 return 1;
449 if (x->virt < y->virt)
450 return -1;
451 return 0;
452 }
453
454 /* Read OBP translations property into 'prom_trans[]'. */
455 static void __init read_obp_translations(void)
456 {
457 int n, node, ents, first, last, i;
458
459 node = prom_finddevice("/virtual-memory");
460 n = prom_getproplen(node, "translations");
461 if (unlikely(n == 0 || n == -1)) {
462 prom_printf("prom_mappings: Couldn't get size.\n");
463 prom_halt();
464 }
465 if (unlikely(n > sizeof(prom_trans))) {
466 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
467 prom_halt();
468 }
469
470 if ((n = prom_getproperty(node, "translations",
471 (char *)&prom_trans[0],
472 sizeof(prom_trans))) == -1) {
473 prom_printf("prom_mappings: Couldn't get property.\n");
474 prom_halt();
475 }
476
477 n = n / sizeof(struct linux_prom_translation);
478
479 ents = n;
480
481 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
482 cmp_ptrans, NULL);
483
484 /* Now kick out all the non-OBP entries. */
485 for (i = 0; i < ents; i++) {
486 if (in_obp_range(prom_trans[i].virt))
487 break;
488 }
489 first = i;
490 for (; i < ents; i++) {
491 if (!in_obp_range(prom_trans[i].virt))
492 break;
493 }
494 last = i;
495
496 for (i = 0; i < (last - first); i++) {
497 struct linux_prom_translation *src = &prom_trans[i + first];
498 struct linux_prom_translation *dest = &prom_trans[i];
499
500 *dest = *src;
501 }
502 for (; i < ents; i++) {
503 struct linux_prom_translation *dest = &prom_trans[i];
504 dest->virt = dest->size = dest->data = 0x0UL;
505 }
506
507 prom_trans_ents = last - first;
508
509 if (tlb_type == spitfire) {
510 /* Clear diag TTE bits. */
511 for (i = 0; i < prom_trans_ents; i++)
512 prom_trans[i].data &= ~0x0003fe0000000000UL;
513 }
514 }
515
516 static void __init hypervisor_tlb_lock(unsigned long vaddr,
517 unsigned long pte,
518 unsigned long mmu)
519 {
520 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
521
522 if (ret != 0) {
523 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
524 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
525 prom_halt();
526 }
527 }
528
529 static unsigned long kern_large_tte(unsigned long paddr);
530
531 static void __init remap_kernel(void)
532 {
533 unsigned long phys_page, tte_vaddr, tte_data;
534 int i, tlb_ent = sparc64_highest_locked_tlbent();
535
536 tte_vaddr = (unsigned long) KERNBASE;
537 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
538 tte_data = kern_large_tte(phys_page);
539
540 kern_locked_tte_data = tte_data;
541
542 /* Now lock us into the TLBs via Hypervisor or OBP. */
543 if (tlb_type == hypervisor) {
544 for (i = 0; i < num_kernel_image_mappings; i++) {
545 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
546 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
547 tte_vaddr += 0x400000;
548 tte_data += 0x400000;
549 }
550 } else {
551 for (i = 0; i < num_kernel_image_mappings; i++) {
552 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
553 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
554 tte_vaddr += 0x400000;
555 tte_data += 0x400000;
556 }
557 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
558 }
559 if (tlb_type == cheetah_plus) {
560 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
561 CTX_CHEETAH_PLUS_NUC);
562 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
563 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
564 }
565 }
566
567
568 static void __init inherit_prom_mappings(void)
569 {
570 /* Now fixup OBP's idea about where we really are mapped. */
571 printk("Remapping the kernel... ");
572 remap_kernel();
573 printk("done.\n");
574 }
575
576 void prom_world(int enter)
577 {
578 if (!enter)
579 set_fs((mm_segment_t) { get_thread_current_ds() });
580
581 __asm__ __volatile__("flushw");
582 }
583
584 void __flush_dcache_range(unsigned long start, unsigned long end)
585 {
586 unsigned long va;
587
588 if (tlb_type == spitfire) {
589 int n = 0;
590
591 for (va = start; va < end; va += 32) {
592 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
593 if (++n >= 512)
594 break;
595 }
596 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
597 start = __pa(start);
598 end = __pa(end);
599 for (va = start; va < end; va += 32)
600 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
601 "membar #Sync"
602 : /* no outputs */
603 : "r" (va),
604 "i" (ASI_DCACHE_INVALIDATE));
605 }
606 }
607 EXPORT_SYMBOL(__flush_dcache_range);
608
609 /* get_new_mmu_context() uses "cache + 1". */
610 DEFINE_SPINLOCK(ctx_alloc_lock);
611 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
612 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
613 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
614 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
615
616 /* Caller does TLB context flushing on local CPU if necessary.
617 * The caller also ensures that CTX_VALID(mm->context) is false.
618 *
619 * We must be careful about boundary cases so that we never
620 * let the user have CTX 0 (nucleus) or we ever use a CTX
621 * version of zero (and thus NO_CONTEXT would not be caught
622 * by version mis-match tests in mmu_context.h).
623 *
624 * Always invoked with interrupts disabled.
625 */
626 void get_new_mmu_context(struct mm_struct *mm)
627 {
628 unsigned long ctx, new_ctx;
629 unsigned long orig_pgsz_bits;
630 unsigned long flags;
631 int new_version;
632
633 spin_lock_irqsave(&ctx_alloc_lock, flags);
634 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
635 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
636 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
637 new_version = 0;
638 if (new_ctx >= (1 << CTX_NR_BITS)) {
639 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
640 if (new_ctx >= ctx) {
641 int i;
642 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
643 CTX_FIRST_VERSION;
644 if (new_ctx == 1)
645 new_ctx = CTX_FIRST_VERSION;
646
647 /* Don't call memset, for 16 entries that's just
648 * plain silly...
649 */
650 mmu_context_bmap[0] = 3;
651 mmu_context_bmap[1] = 0;
652 mmu_context_bmap[2] = 0;
653 mmu_context_bmap[3] = 0;
654 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
655 mmu_context_bmap[i + 0] = 0;
656 mmu_context_bmap[i + 1] = 0;
657 mmu_context_bmap[i + 2] = 0;
658 mmu_context_bmap[i + 3] = 0;
659 }
660 new_version = 1;
661 goto out;
662 }
663 }
664 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
665 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
666 out:
667 tlb_context_cache = new_ctx;
668 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
669 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
670
671 if (unlikely(new_version))
672 smp_new_mmu_context_version();
673 }
674
675 static int numa_enabled = 1;
676 static int numa_debug;
677
678 static int __init early_numa(char *p)
679 {
680 if (!p)
681 return 0;
682
683 if (strstr(p, "off"))
684 numa_enabled = 0;
685
686 if (strstr(p, "debug"))
687 numa_debug = 1;
688
689 return 0;
690 }
691 early_param("numa", early_numa);
692
693 #define numadbg(f, a...) \
694 do { if (numa_debug) \
695 printk(KERN_INFO f, ## a); \
696 } while (0)
697
698 static void __init find_ramdisk(unsigned long phys_base)
699 {
700 #ifdef CONFIG_BLK_DEV_INITRD
701 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
702 unsigned long ramdisk_image;
703
704 /* Older versions of the bootloader only supported a
705 * 32-bit physical address for the ramdisk image
706 * location, stored at sparc_ramdisk_image. Newer
707 * SILO versions set sparc_ramdisk_image to zero and
708 * provide a full 64-bit physical address at
709 * sparc_ramdisk_image64.
710 */
711 ramdisk_image = sparc_ramdisk_image;
712 if (!ramdisk_image)
713 ramdisk_image = sparc_ramdisk_image64;
714
715 /* Another bootloader quirk. The bootloader normalizes
716 * the physical address to KERNBASE, so we have to
717 * factor that back out and add in the lowest valid
718 * physical page address to get the true physical address.
719 */
720 ramdisk_image -= KERNBASE;
721 ramdisk_image += phys_base;
722
723 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
724 ramdisk_image, sparc_ramdisk_size);
725
726 initrd_start = ramdisk_image;
727 initrd_end = ramdisk_image + sparc_ramdisk_size;
728
729 memblock_reserve(initrd_start, sparc_ramdisk_size);
730
731 initrd_start += PAGE_OFFSET;
732 initrd_end += PAGE_OFFSET;
733 }
734 #endif
735 }
736
737 struct node_mem_mask {
738 unsigned long mask;
739 unsigned long val;
740 unsigned long bootmem_paddr;
741 };
742 static struct node_mem_mask node_masks[MAX_NUMNODES];
743 static int num_node_masks;
744
745 int numa_cpu_lookup_table[NR_CPUS];
746 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
747
748 #ifdef CONFIG_NEED_MULTIPLE_NODES
749
750 struct mdesc_mblock {
751 u64 base;
752 u64 size;
753 u64 offset; /* RA-to-PA */
754 };
755 static struct mdesc_mblock *mblocks;
756 static int num_mblocks;
757
758 static unsigned long ra_to_pa(unsigned long addr)
759 {
760 int i;
761
762 for (i = 0; i < num_mblocks; i++) {
763 struct mdesc_mblock *m = &mblocks[i];
764
765 if (addr >= m->base &&
766 addr < (m->base + m->size)) {
767 addr += m->offset;
768 break;
769 }
770 }
771 return addr;
772 }
773
774 static int find_node(unsigned long addr)
775 {
776 int i;
777
778 addr = ra_to_pa(addr);
779 for (i = 0; i < num_node_masks; i++) {
780 struct node_mem_mask *p = &node_masks[i];
781
782 if ((addr & p->mask) == p->val)
783 return i;
784 }
785 return -1;
786 }
787
788 static unsigned long long nid_range(unsigned long long start,
789 unsigned long long end, int *nid)
790 {
791 *nid = find_node(start);
792 start += PAGE_SIZE;
793 while (start < end) {
794 int n = find_node(start);
795
796 if (n != *nid)
797 break;
798 start += PAGE_SIZE;
799 }
800
801 if (start > end)
802 start = end;
803
804 return start;
805 }
806 #else
807 static unsigned long long nid_range(unsigned long long start,
808 unsigned long long end, int *nid)
809 {
810 *nid = 0;
811 return end;
812 }
813 #endif
814
815 /* This must be invoked after performing all of the necessary
816 * add_active_range() calls for 'nid'. We need to be able to get
817 * correct data from get_pfn_range_for_nid().
818 */
819 static void __init allocate_node_data(int nid)
820 {
821 unsigned long paddr, num_pages, start_pfn, end_pfn;
822 struct pglist_data *p;
823
824 #ifdef CONFIG_NEED_MULTIPLE_NODES
825 paddr = memblock_alloc_nid(sizeof(struct pglist_data),
826 SMP_CACHE_BYTES, nid, nid_range);
827 if (!paddr) {
828 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
829 prom_halt();
830 }
831 NODE_DATA(nid) = __va(paddr);
832 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
833
834 NODE_DATA(nid)->bdata = &bootmem_node_data[nid];
835 #endif
836
837 p = NODE_DATA(nid);
838
839 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
840 p->node_start_pfn = start_pfn;
841 p->node_spanned_pages = end_pfn - start_pfn;
842
843 if (p->node_spanned_pages) {
844 num_pages = bootmem_bootmap_pages(p->node_spanned_pages);
845
846 paddr = memblock_alloc_nid(num_pages << PAGE_SHIFT, PAGE_SIZE, nid,
847 nid_range);
848 if (!paddr) {
849 prom_printf("Cannot allocate bootmap for nid[%d]\n",
850 nid);
851 prom_halt();
852 }
853 node_masks[nid].bootmem_paddr = paddr;
854 }
855 }
856
857 static void init_node_masks_nonnuma(void)
858 {
859 int i;
860
861 numadbg("Initializing tables for non-numa.\n");
862
863 node_masks[0].mask = node_masks[0].val = 0;
864 num_node_masks = 1;
865
866 for (i = 0; i < NR_CPUS; i++)
867 numa_cpu_lookup_table[i] = 0;
868
869 numa_cpumask_lookup_table[0] = CPU_MASK_ALL;
870 }
871
872 #ifdef CONFIG_NEED_MULTIPLE_NODES
873 struct pglist_data *node_data[MAX_NUMNODES];
874
875 EXPORT_SYMBOL(numa_cpu_lookup_table);
876 EXPORT_SYMBOL(numa_cpumask_lookup_table);
877 EXPORT_SYMBOL(node_data);
878
879 struct mdesc_mlgroup {
880 u64 node;
881 u64 latency;
882 u64 match;
883 u64 mask;
884 };
885 static struct mdesc_mlgroup *mlgroups;
886 static int num_mlgroups;
887
888 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
889 u32 cfg_handle)
890 {
891 u64 arc;
892
893 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
894 u64 target = mdesc_arc_target(md, arc);
895 const u64 *val;
896
897 val = mdesc_get_property(md, target,
898 "cfg-handle", NULL);
899 if (val && *val == cfg_handle)
900 return 0;
901 }
902 return -ENODEV;
903 }
904
905 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
906 u32 cfg_handle)
907 {
908 u64 arc, candidate, best_latency = ~(u64)0;
909
910 candidate = MDESC_NODE_NULL;
911 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
912 u64 target = mdesc_arc_target(md, arc);
913 const char *name = mdesc_node_name(md, target);
914 const u64 *val;
915
916 if (strcmp(name, "pio-latency-group"))
917 continue;
918
919 val = mdesc_get_property(md, target, "latency", NULL);
920 if (!val)
921 continue;
922
923 if (*val < best_latency) {
924 candidate = target;
925 best_latency = *val;
926 }
927 }
928
929 if (candidate == MDESC_NODE_NULL)
930 return -ENODEV;
931
932 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
933 }
934
935 int of_node_to_nid(struct device_node *dp)
936 {
937 const struct linux_prom64_registers *regs;
938 struct mdesc_handle *md;
939 u32 cfg_handle;
940 int count, nid;
941 u64 grp;
942
943 /* This is the right thing to do on currently supported
944 * SUN4U NUMA platforms as well, as the PCI controller does
945 * not sit behind any particular memory controller.
946 */
947 if (!mlgroups)
948 return -1;
949
950 regs = of_get_property(dp, "reg", NULL);
951 if (!regs)
952 return -1;
953
954 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
955
956 md = mdesc_grab();
957
958 count = 0;
959 nid = -1;
960 mdesc_for_each_node_by_name(md, grp, "group") {
961 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
962 nid = count;
963 break;
964 }
965 count++;
966 }
967
968 mdesc_release(md);
969
970 return nid;
971 }
972
973 static void __init add_node_ranges(void)
974 {
975 int i;
976
977 for (i = 0; i < memblock.memory.cnt; i++) {
978 unsigned long size = memblock_size_bytes(&memblock.memory, i);
979 unsigned long start, end;
980
981 start = memblock.memory.region[i].base;
982 end = start + size;
983 while (start < end) {
984 unsigned long this_end;
985 int nid;
986
987 this_end = nid_range(start, end, &nid);
988
989 numadbg("Adding active range nid[%d] "
990 "start[%lx] end[%lx]\n",
991 nid, start, this_end);
992
993 add_active_range(nid,
994 start >> PAGE_SHIFT,
995 this_end >> PAGE_SHIFT);
996
997 start = this_end;
998 }
999 }
1000 }
1001
1002 static int __init grab_mlgroups(struct mdesc_handle *md)
1003 {
1004 unsigned long paddr;
1005 int count = 0;
1006 u64 node;
1007
1008 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1009 count++;
1010 if (!count)
1011 return -ENOENT;
1012
1013 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1014 SMP_CACHE_BYTES);
1015 if (!paddr)
1016 return -ENOMEM;
1017
1018 mlgroups = __va(paddr);
1019 num_mlgroups = count;
1020
1021 count = 0;
1022 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1023 struct mdesc_mlgroup *m = &mlgroups[count++];
1024 const u64 *val;
1025
1026 m->node = node;
1027
1028 val = mdesc_get_property(md, node, "latency", NULL);
1029 m->latency = *val;
1030 val = mdesc_get_property(md, node, "address-match", NULL);
1031 m->match = *val;
1032 val = mdesc_get_property(md, node, "address-mask", NULL);
1033 m->mask = *val;
1034
1035 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1036 "match[%llx] mask[%llx]\n",
1037 count - 1, m->node, m->latency, m->match, m->mask);
1038 }
1039
1040 return 0;
1041 }
1042
1043 static int __init grab_mblocks(struct mdesc_handle *md)
1044 {
1045 unsigned long paddr;
1046 int count = 0;
1047 u64 node;
1048
1049 mdesc_for_each_node_by_name(md, node, "mblock")
1050 count++;
1051 if (!count)
1052 return -ENOENT;
1053
1054 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1055 SMP_CACHE_BYTES);
1056 if (!paddr)
1057 return -ENOMEM;
1058
1059 mblocks = __va(paddr);
1060 num_mblocks = count;
1061
1062 count = 0;
1063 mdesc_for_each_node_by_name(md, node, "mblock") {
1064 struct mdesc_mblock *m = &mblocks[count++];
1065 const u64 *val;
1066
1067 val = mdesc_get_property(md, node, "base", NULL);
1068 m->base = *val;
1069 val = mdesc_get_property(md, node, "size", NULL);
1070 m->size = *val;
1071 val = mdesc_get_property(md, node,
1072 "address-congruence-offset", NULL);
1073 m->offset = *val;
1074
1075 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1076 count - 1, m->base, m->size, m->offset);
1077 }
1078
1079 return 0;
1080 }
1081
1082 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1083 u64 grp, cpumask_t *mask)
1084 {
1085 u64 arc;
1086
1087 cpus_clear(*mask);
1088
1089 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1090 u64 target = mdesc_arc_target(md, arc);
1091 const char *name = mdesc_node_name(md, target);
1092 const u64 *id;
1093
1094 if (strcmp(name, "cpu"))
1095 continue;
1096 id = mdesc_get_property(md, target, "id", NULL);
1097 if (*id < nr_cpu_ids)
1098 cpu_set(*id, *mask);
1099 }
1100 }
1101
1102 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1103 {
1104 int i;
1105
1106 for (i = 0; i < num_mlgroups; i++) {
1107 struct mdesc_mlgroup *m = &mlgroups[i];
1108 if (m->node == node)
1109 return m;
1110 }
1111 return NULL;
1112 }
1113
1114 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1115 int index)
1116 {
1117 struct mdesc_mlgroup *candidate = NULL;
1118 u64 arc, best_latency = ~(u64)0;
1119 struct node_mem_mask *n;
1120
1121 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1122 u64 target = mdesc_arc_target(md, arc);
1123 struct mdesc_mlgroup *m = find_mlgroup(target);
1124 if (!m)
1125 continue;
1126 if (m->latency < best_latency) {
1127 candidate = m;
1128 best_latency = m->latency;
1129 }
1130 }
1131 if (!candidate)
1132 return -ENOENT;
1133
1134 if (num_node_masks != index) {
1135 printk(KERN_ERR "Inconsistent NUMA state, "
1136 "index[%d] != num_node_masks[%d]\n",
1137 index, num_node_masks);
1138 return -EINVAL;
1139 }
1140
1141 n = &node_masks[num_node_masks++];
1142
1143 n->mask = candidate->mask;
1144 n->val = candidate->match;
1145
1146 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1147 index, n->mask, n->val, candidate->latency);
1148
1149 return 0;
1150 }
1151
1152 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1153 int index)
1154 {
1155 cpumask_t mask;
1156 int cpu;
1157
1158 numa_parse_mdesc_group_cpus(md, grp, &mask);
1159
1160 for_each_cpu_mask(cpu, mask)
1161 numa_cpu_lookup_table[cpu] = index;
1162 numa_cpumask_lookup_table[index] = mask;
1163
1164 if (numa_debug) {
1165 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1166 for_each_cpu_mask(cpu, mask)
1167 printk("%d ", cpu);
1168 printk("]\n");
1169 }
1170
1171 return numa_attach_mlgroup(md, grp, index);
1172 }
1173
1174 static int __init numa_parse_mdesc(void)
1175 {
1176 struct mdesc_handle *md = mdesc_grab();
1177 int i, err, count;
1178 u64 node;
1179
1180 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1181 if (node == MDESC_NODE_NULL) {
1182 mdesc_release(md);
1183 return -ENOENT;
1184 }
1185
1186 err = grab_mblocks(md);
1187 if (err < 0)
1188 goto out;
1189
1190 err = grab_mlgroups(md);
1191 if (err < 0)
1192 goto out;
1193
1194 count = 0;
1195 mdesc_for_each_node_by_name(md, node, "group") {
1196 err = numa_parse_mdesc_group(md, node, count);
1197 if (err < 0)
1198 break;
1199 count++;
1200 }
1201
1202 add_node_ranges();
1203
1204 for (i = 0; i < num_node_masks; i++) {
1205 allocate_node_data(i);
1206 node_set_online(i);
1207 }
1208
1209 err = 0;
1210 out:
1211 mdesc_release(md);
1212 return err;
1213 }
1214
1215 static int __init numa_parse_jbus(void)
1216 {
1217 unsigned long cpu, index;
1218
1219 /* NUMA node id is encoded in bits 36 and higher, and there is
1220 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1221 */
1222 index = 0;
1223 for_each_present_cpu(cpu) {
1224 numa_cpu_lookup_table[cpu] = index;
1225 numa_cpumask_lookup_table[index] = cpumask_of_cpu(cpu);
1226 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1227 node_masks[index].val = cpu << 36UL;
1228
1229 index++;
1230 }
1231 num_node_masks = index;
1232
1233 add_node_ranges();
1234
1235 for (index = 0; index < num_node_masks; index++) {
1236 allocate_node_data(index);
1237 node_set_online(index);
1238 }
1239
1240 return 0;
1241 }
1242
1243 static int __init numa_parse_sun4u(void)
1244 {
1245 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1246 unsigned long ver;
1247
1248 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1249 if ((ver >> 32UL) == __JALAPENO_ID ||
1250 (ver >> 32UL) == __SERRANO_ID)
1251 return numa_parse_jbus();
1252 }
1253 return -1;
1254 }
1255
1256 static int __init bootmem_init_numa(void)
1257 {
1258 int err = -1;
1259
1260 numadbg("bootmem_init_numa()\n");
1261
1262 if (numa_enabled) {
1263 if (tlb_type == hypervisor)
1264 err = numa_parse_mdesc();
1265 else
1266 err = numa_parse_sun4u();
1267 }
1268 return err;
1269 }
1270
1271 #else
1272
1273 static int bootmem_init_numa(void)
1274 {
1275 return -1;
1276 }
1277
1278 #endif
1279
1280 static void __init bootmem_init_nonnuma(void)
1281 {
1282 unsigned long top_of_ram = memblock_end_of_DRAM();
1283 unsigned long total_ram = memblock_phys_mem_size();
1284 unsigned int i;
1285
1286 numadbg("bootmem_init_nonnuma()\n");
1287
1288 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1289 top_of_ram, total_ram);
1290 printk(KERN_INFO "Memory hole size: %ldMB\n",
1291 (top_of_ram - total_ram) >> 20);
1292
1293 init_node_masks_nonnuma();
1294
1295 for (i = 0; i < memblock.memory.cnt; i++) {
1296 unsigned long size = memblock_size_bytes(&memblock.memory, i);
1297 unsigned long start_pfn, end_pfn;
1298
1299 if (!size)
1300 continue;
1301
1302 start_pfn = memblock.memory.region[i].base >> PAGE_SHIFT;
1303 end_pfn = start_pfn + memblock_size_pages(&memblock.memory, i);
1304 add_active_range(0, start_pfn, end_pfn);
1305 }
1306
1307 allocate_node_data(0);
1308
1309 node_set_online(0);
1310 }
1311
1312 static void __init reserve_range_in_node(int nid, unsigned long start,
1313 unsigned long end)
1314 {
1315 numadbg(" reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n",
1316 nid, start, end);
1317 while (start < end) {
1318 unsigned long this_end;
1319 int n;
1320
1321 this_end = nid_range(start, end, &n);
1322 if (n == nid) {
1323 numadbg(" MATCH reserving range [%lx:%lx]\n",
1324 start, this_end);
1325 reserve_bootmem_node(NODE_DATA(nid), start,
1326 (this_end - start), BOOTMEM_DEFAULT);
1327 } else
1328 numadbg(" NO MATCH, advancing start to %lx\n",
1329 this_end);
1330
1331 start = this_end;
1332 }
1333 }
1334
1335 static void __init trim_reserved_in_node(int nid)
1336 {
1337 int i;
1338
1339 numadbg(" trim_reserved_in_node(%d)\n", nid);
1340
1341 for (i = 0; i < memblock.reserved.cnt; i++) {
1342 unsigned long start = memblock.reserved.region[i].base;
1343 unsigned long size = memblock_size_bytes(&memblock.reserved, i);
1344 unsigned long end = start + size;
1345
1346 reserve_range_in_node(nid, start, end);
1347 }
1348 }
1349
1350 static void __init bootmem_init_one_node(int nid)
1351 {
1352 struct pglist_data *p;
1353
1354 numadbg("bootmem_init_one_node(%d)\n", nid);
1355
1356 p = NODE_DATA(nid);
1357
1358 if (p->node_spanned_pages) {
1359 unsigned long paddr = node_masks[nid].bootmem_paddr;
1360 unsigned long end_pfn;
1361
1362 end_pfn = p->node_start_pfn + p->node_spanned_pages;
1363
1364 numadbg(" init_bootmem_node(%d, %lx, %lx, %lx)\n",
1365 nid, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn);
1366
1367 init_bootmem_node(p, paddr >> PAGE_SHIFT,
1368 p->node_start_pfn, end_pfn);
1369
1370 numadbg(" free_bootmem_with_active_regions(%d, %lx)\n",
1371 nid, end_pfn);
1372 free_bootmem_with_active_regions(nid, end_pfn);
1373
1374 trim_reserved_in_node(nid);
1375
1376 numadbg(" sparse_memory_present_with_active_regions(%d)\n",
1377 nid);
1378 sparse_memory_present_with_active_regions(nid);
1379 }
1380 }
1381
1382 static unsigned long __init bootmem_init(unsigned long phys_base)
1383 {
1384 unsigned long end_pfn;
1385 int nid;
1386
1387 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1388 max_pfn = max_low_pfn = end_pfn;
1389 min_low_pfn = (phys_base >> PAGE_SHIFT);
1390
1391 if (bootmem_init_numa() < 0)
1392 bootmem_init_nonnuma();
1393
1394
1395 for_each_online_node(nid)
1396 bootmem_init_one_node(nid);
1397
1398 sparse_init();
1399
1400 return end_pfn;
1401 }
1402
1403 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1404 static int pall_ents __initdata;
1405
1406 #ifdef CONFIG_DEBUG_PAGEALLOC
1407 static unsigned long __ref kernel_map_range(unsigned long pstart,
1408 unsigned long pend, pgprot_t prot)
1409 {
1410 unsigned long vstart = PAGE_OFFSET + pstart;
1411 unsigned long vend = PAGE_OFFSET + pend;
1412 unsigned long alloc_bytes = 0UL;
1413
1414 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1415 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1416 vstart, vend);
1417 prom_halt();
1418 }
1419
1420 while (vstart < vend) {
1421 unsigned long this_end, paddr = __pa(vstart);
1422 pgd_t *pgd = pgd_offset_k(vstart);
1423 pud_t *pud;
1424 pmd_t *pmd;
1425 pte_t *pte;
1426
1427 pud = pud_offset(pgd, vstart);
1428 if (pud_none(*pud)) {
1429 pmd_t *new;
1430
1431 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1432 alloc_bytes += PAGE_SIZE;
1433 pud_populate(&init_mm, pud, new);
1434 }
1435
1436 pmd = pmd_offset(pud, vstart);
1437 if (!pmd_present(*pmd)) {
1438 pte_t *new;
1439
1440 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1441 alloc_bytes += PAGE_SIZE;
1442 pmd_populate_kernel(&init_mm, pmd, new);
1443 }
1444
1445 pte = pte_offset_kernel(pmd, vstart);
1446 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1447 if (this_end > vend)
1448 this_end = vend;
1449
1450 while (vstart < this_end) {
1451 pte_val(*pte) = (paddr | pgprot_val(prot));
1452
1453 vstart += PAGE_SIZE;
1454 paddr += PAGE_SIZE;
1455 pte++;
1456 }
1457 }
1458
1459 return alloc_bytes;
1460 }
1461
1462 extern unsigned int kvmap_linear_patch[1];
1463 #endif /* CONFIG_DEBUG_PAGEALLOC */
1464
1465 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1466 {
1467 const unsigned long shift_256MB = 28;
1468 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1469 const unsigned long size_256MB = (1UL << shift_256MB);
1470
1471 while (start < end) {
1472 long remains;
1473
1474 remains = end - start;
1475 if (remains < size_256MB)
1476 break;
1477
1478 if (start & mask_256MB) {
1479 start = (start + size_256MB) & ~mask_256MB;
1480 continue;
1481 }
1482
1483 while (remains >= size_256MB) {
1484 unsigned long index = start >> shift_256MB;
1485
1486 __set_bit(index, kpte_linear_bitmap);
1487
1488 start += size_256MB;
1489 remains -= size_256MB;
1490 }
1491 }
1492 }
1493
1494 static void __init init_kpte_bitmap(void)
1495 {
1496 unsigned long i;
1497
1498 for (i = 0; i < pall_ents; i++) {
1499 unsigned long phys_start, phys_end;
1500
1501 phys_start = pall[i].phys_addr;
1502 phys_end = phys_start + pall[i].reg_size;
1503
1504 mark_kpte_bitmap(phys_start, phys_end);
1505 }
1506 }
1507
1508 static void __init kernel_physical_mapping_init(void)
1509 {
1510 #ifdef CONFIG_DEBUG_PAGEALLOC
1511 unsigned long i, mem_alloced = 0UL;
1512
1513 for (i = 0; i < pall_ents; i++) {
1514 unsigned long phys_start, phys_end;
1515
1516 phys_start = pall[i].phys_addr;
1517 phys_end = phys_start + pall[i].reg_size;
1518
1519 mem_alloced += kernel_map_range(phys_start, phys_end,
1520 PAGE_KERNEL);
1521 }
1522
1523 printk("Allocated %ld bytes for kernel page tables.\n",
1524 mem_alloced);
1525
1526 kvmap_linear_patch[0] = 0x01000000; /* nop */
1527 flushi(&kvmap_linear_patch[0]);
1528
1529 __flush_tlb_all();
1530 #endif
1531 }
1532
1533 #ifdef CONFIG_DEBUG_PAGEALLOC
1534 void kernel_map_pages(struct page *page, int numpages, int enable)
1535 {
1536 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1537 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1538
1539 kernel_map_range(phys_start, phys_end,
1540 (enable ? PAGE_KERNEL : __pgprot(0)));
1541
1542 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1543 PAGE_OFFSET + phys_end);
1544
1545 /* we should perform an IPI and flush all tlbs,
1546 * but that can deadlock->flush only current cpu.
1547 */
1548 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1549 PAGE_OFFSET + phys_end);
1550 }
1551 #endif
1552
1553 unsigned long __init find_ecache_flush_span(unsigned long size)
1554 {
1555 int i;
1556
1557 for (i = 0; i < pavail_ents; i++) {
1558 if (pavail[i].reg_size >= size)
1559 return pavail[i].phys_addr;
1560 }
1561
1562 return ~0UL;
1563 }
1564
1565 static void __init tsb_phys_patch(void)
1566 {
1567 struct tsb_ldquad_phys_patch_entry *pquad;
1568 struct tsb_phys_patch_entry *p;
1569
1570 pquad = &__tsb_ldquad_phys_patch;
1571 while (pquad < &__tsb_ldquad_phys_patch_end) {
1572 unsigned long addr = pquad->addr;
1573
1574 if (tlb_type == hypervisor)
1575 *(unsigned int *) addr = pquad->sun4v_insn;
1576 else
1577 *(unsigned int *) addr = pquad->sun4u_insn;
1578 wmb();
1579 __asm__ __volatile__("flush %0"
1580 : /* no outputs */
1581 : "r" (addr));
1582
1583 pquad++;
1584 }
1585
1586 p = &__tsb_phys_patch;
1587 while (p < &__tsb_phys_patch_end) {
1588 unsigned long addr = p->addr;
1589
1590 *(unsigned int *) addr = p->insn;
1591 wmb();
1592 __asm__ __volatile__("flush %0"
1593 : /* no outputs */
1594 : "r" (addr));
1595
1596 p++;
1597 }
1598 }
1599
1600 /* Don't mark as init, we give this to the Hypervisor. */
1601 #ifndef CONFIG_DEBUG_PAGEALLOC
1602 #define NUM_KTSB_DESCR 2
1603 #else
1604 #define NUM_KTSB_DESCR 1
1605 #endif
1606 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1607 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1608
1609 static void __init sun4v_ktsb_init(void)
1610 {
1611 unsigned long ktsb_pa;
1612
1613 /* First KTSB for PAGE_SIZE mappings. */
1614 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1615
1616 switch (PAGE_SIZE) {
1617 case 8 * 1024:
1618 default:
1619 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1620 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1621 break;
1622
1623 case 64 * 1024:
1624 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1625 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1626 break;
1627
1628 case 512 * 1024:
1629 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1630 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1631 break;
1632
1633 case 4 * 1024 * 1024:
1634 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1635 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1636 break;
1637 };
1638
1639 ktsb_descr[0].assoc = 1;
1640 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1641 ktsb_descr[0].ctx_idx = 0;
1642 ktsb_descr[0].tsb_base = ktsb_pa;
1643 ktsb_descr[0].resv = 0;
1644
1645 #ifndef CONFIG_DEBUG_PAGEALLOC
1646 /* Second KTSB for 4MB/256MB mappings. */
1647 ktsb_pa = (kern_base +
1648 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1649
1650 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1651 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1652 HV_PGSZ_MASK_256MB);
1653 ktsb_descr[1].assoc = 1;
1654 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1655 ktsb_descr[1].ctx_idx = 0;
1656 ktsb_descr[1].tsb_base = ktsb_pa;
1657 ktsb_descr[1].resv = 0;
1658 #endif
1659 }
1660
1661 void __cpuinit sun4v_ktsb_register(void)
1662 {
1663 unsigned long pa, ret;
1664
1665 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1666
1667 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1668 if (ret != 0) {
1669 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1670 "errors with %lx\n", pa, ret);
1671 prom_halt();
1672 }
1673 }
1674
1675 /* paging_init() sets up the page tables */
1676
1677 static unsigned long last_valid_pfn;
1678 pgd_t swapper_pg_dir[2048];
1679
1680 static void sun4u_pgprot_init(void);
1681 static void sun4v_pgprot_init(void);
1682
1683 void __init paging_init(void)
1684 {
1685 unsigned long end_pfn, shift, phys_base;
1686 unsigned long real_end, i;
1687
1688 /* These build time checkes make sure that the dcache_dirty_cpu()
1689 * page->flags usage will work.
1690 *
1691 * When a page gets marked as dcache-dirty, we store the
1692 * cpu number starting at bit 32 in the page->flags. Also,
1693 * functions like clear_dcache_dirty_cpu use the cpu mask
1694 * in 13-bit signed-immediate instruction fields.
1695 */
1696
1697 /*
1698 * Page flags must not reach into upper 32 bits that are used
1699 * for the cpu number
1700 */
1701 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1702
1703 /*
1704 * The bit fields placed in the high range must not reach below
1705 * the 32 bit boundary. Otherwise we cannot place the cpu field
1706 * at the 32 bit boundary.
1707 */
1708 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1709 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1710
1711 BUILD_BUG_ON(NR_CPUS > 4096);
1712
1713 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1714 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1715
1716 /* Invalidate both kernel TSBs. */
1717 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1718 #ifndef CONFIG_DEBUG_PAGEALLOC
1719 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1720 #endif
1721
1722 if (tlb_type == hypervisor)
1723 sun4v_pgprot_init();
1724 else
1725 sun4u_pgprot_init();
1726
1727 if (tlb_type == cheetah_plus ||
1728 tlb_type == hypervisor)
1729 tsb_phys_patch();
1730
1731 if (tlb_type == hypervisor) {
1732 sun4v_patch_tlb_handlers();
1733 sun4v_ktsb_init();
1734 }
1735
1736 memblock_init();
1737
1738 read_obp_translations();
1739 read_obp_memory("reg", &pall[0], &pall_ents);
1740 read_obp_memory("available", &pavail[0], &pavail_ents);
1741 read_obp_memory("available", &pavail[0], &pavail_ents);
1742
1743 phys_base = 0xffffffffffffffffUL;
1744 for (i = 0; i < pavail_ents; i++) {
1745 phys_base = min(phys_base, pavail[i].phys_addr);
1746 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
1747 }
1748
1749 memblock_reserve(kern_base, kern_size);
1750
1751 find_ramdisk(phys_base);
1752
1753 memblock_enforce_memory_limit(cmdline_memory_size);
1754
1755 memblock_analyze();
1756 memblock_dump_all();
1757
1758 set_bit(0, mmu_context_bmap);
1759
1760 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1761
1762 real_end = (unsigned long)_end;
1763 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1764 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1765 num_kernel_image_mappings);
1766
1767 /* Set kernel pgd to upper alias so physical page computations
1768 * work.
1769 */
1770 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1771
1772 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1773
1774 /* Now can init the kernel/bad page tables. */
1775 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1776 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1777
1778 inherit_prom_mappings();
1779
1780 init_kpte_bitmap();
1781
1782 /* Ok, we can use our TLB miss and window trap handlers safely. */
1783 setup_tba();
1784
1785 __flush_tlb_all();
1786
1787 if (tlb_type == hypervisor)
1788 sun4v_ktsb_register();
1789
1790 prom_build_devicetree();
1791 of_populate_present_mask();
1792 #ifndef CONFIG_SMP
1793 of_fill_in_cpu_data();
1794 #endif
1795
1796 if (tlb_type == hypervisor) {
1797 sun4v_mdesc_init();
1798 mdesc_populate_present_mask(cpu_all_mask);
1799 #ifndef CONFIG_SMP
1800 mdesc_fill_in_cpu_data(cpu_all_mask);
1801 #endif
1802 }
1803
1804 /* Once the OF device tree and MDESC have been setup, we know
1805 * the list of possible cpus. Therefore we can allocate the
1806 * IRQ stacks.
1807 */
1808 for_each_possible_cpu(i) {
1809 softirq_stack[i] = __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
1810 hardirq_stack[i] = __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
1811 }
1812
1813 /* Setup bootmem... */
1814 last_valid_pfn = end_pfn = bootmem_init(phys_base);
1815
1816 #ifndef CONFIG_NEED_MULTIPLE_NODES
1817 max_mapnr = last_valid_pfn;
1818 #endif
1819 kernel_physical_mapping_init();
1820
1821 {
1822 unsigned long max_zone_pfns[MAX_NR_ZONES];
1823
1824 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1825
1826 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1827
1828 free_area_init_nodes(max_zone_pfns);
1829 }
1830
1831 printk("Booting Linux...\n");
1832 }
1833
1834 int __devinit page_in_phys_avail(unsigned long paddr)
1835 {
1836 int i;
1837
1838 paddr &= PAGE_MASK;
1839
1840 for (i = 0; i < pavail_ents; i++) {
1841 unsigned long start, end;
1842
1843 start = pavail[i].phys_addr;
1844 end = start + pavail[i].reg_size;
1845
1846 if (paddr >= start && paddr < end)
1847 return 1;
1848 }
1849 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1850 return 1;
1851 #ifdef CONFIG_BLK_DEV_INITRD
1852 if (paddr >= __pa(initrd_start) &&
1853 paddr < __pa(PAGE_ALIGN(initrd_end)))
1854 return 1;
1855 #endif
1856
1857 return 0;
1858 }
1859
1860 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1861 static int pavail_rescan_ents __initdata;
1862
1863 /* Certain OBP calls, such as fetching "available" properties, can
1864 * claim physical memory. So, along with initializing the valid
1865 * address bitmap, what we do here is refetch the physical available
1866 * memory list again, and make sure it provides at least as much
1867 * memory as 'pavail' does.
1868 */
1869 static void __init setup_valid_addr_bitmap_from_pavail(unsigned long *bitmap)
1870 {
1871 int i;
1872
1873 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1874
1875 for (i = 0; i < pavail_ents; i++) {
1876 unsigned long old_start, old_end;
1877
1878 old_start = pavail[i].phys_addr;
1879 old_end = old_start + pavail[i].reg_size;
1880 while (old_start < old_end) {
1881 int n;
1882
1883 for (n = 0; n < pavail_rescan_ents; n++) {
1884 unsigned long new_start, new_end;
1885
1886 new_start = pavail_rescan[n].phys_addr;
1887 new_end = new_start +
1888 pavail_rescan[n].reg_size;
1889
1890 if (new_start <= old_start &&
1891 new_end >= (old_start + PAGE_SIZE)) {
1892 set_bit(old_start >> 22, bitmap);
1893 goto do_next_page;
1894 }
1895 }
1896
1897 prom_printf("mem_init: Lost memory in pavail\n");
1898 prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
1899 pavail[i].phys_addr,
1900 pavail[i].reg_size);
1901 prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
1902 pavail_rescan[i].phys_addr,
1903 pavail_rescan[i].reg_size);
1904 prom_printf("mem_init: Cannot continue, aborting.\n");
1905 prom_halt();
1906
1907 do_next_page:
1908 old_start += PAGE_SIZE;
1909 }
1910 }
1911 }
1912
1913 static void __init patch_tlb_miss_handler_bitmap(void)
1914 {
1915 extern unsigned int valid_addr_bitmap_insn[];
1916 extern unsigned int valid_addr_bitmap_patch[];
1917
1918 valid_addr_bitmap_insn[1] = valid_addr_bitmap_patch[1];
1919 mb();
1920 valid_addr_bitmap_insn[0] = valid_addr_bitmap_patch[0];
1921 flushi(&valid_addr_bitmap_insn[0]);
1922 }
1923
1924 void __init mem_init(void)
1925 {
1926 unsigned long codepages, datapages, initpages;
1927 unsigned long addr, last;
1928
1929 addr = PAGE_OFFSET + kern_base;
1930 last = PAGE_ALIGN(kern_size) + addr;
1931 while (addr < last) {
1932 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1933 addr += PAGE_SIZE;
1934 }
1935
1936 setup_valid_addr_bitmap_from_pavail(sparc64_valid_addr_bitmap);
1937 patch_tlb_miss_handler_bitmap();
1938
1939 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1940
1941 #ifdef CONFIG_NEED_MULTIPLE_NODES
1942 {
1943 int i;
1944 for_each_online_node(i) {
1945 if (NODE_DATA(i)->node_spanned_pages != 0) {
1946 totalram_pages +=
1947 free_all_bootmem_node(NODE_DATA(i));
1948 }
1949 }
1950 }
1951 #else
1952 totalram_pages = free_all_bootmem();
1953 #endif
1954
1955 /* We subtract one to account for the mem_map_zero page
1956 * allocated below.
1957 */
1958 totalram_pages -= 1;
1959 num_physpages = totalram_pages;
1960
1961 /*
1962 * Set up the zero page, mark it reserved, so that page count
1963 * is not manipulated when freeing the page from user ptes.
1964 */
1965 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1966 if (mem_map_zero == NULL) {
1967 prom_printf("paging_init: Cannot alloc zero page.\n");
1968 prom_halt();
1969 }
1970 SetPageReserved(mem_map_zero);
1971
1972 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1973 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1974 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1975 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1976 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1977 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1978
1979 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1980 nr_free_pages() << (PAGE_SHIFT-10),
1981 codepages << (PAGE_SHIFT-10),
1982 datapages << (PAGE_SHIFT-10),
1983 initpages << (PAGE_SHIFT-10),
1984 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1985
1986 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1987 cheetah_ecache_flush_init();
1988 }
1989
1990 void free_initmem(void)
1991 {
1992 unsigned long addr, initend;
1993 int do_free = 1;
1994
1995 /* If the physical memory maps were trimmed by kernel command
1996 * line options, don't even try freeing this initmem stuff up.
1997 * The kernel image could have been in the trimmed out region
1998 * and if so the freeing below will free invalid page structs.
1999 */
2000 if (cmdline_memory_size)
2001 do_free = 0;
2002
2003 /*
2004 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2005 */
2006 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2007 initend = (unsigned long)(__init_end) & PAGE_MASK;
2008 for (; addr < initend; addr += PAGE_SIZE) {
2009 unsigned long page;
2010 struct page *p;
2011
2012 page = (addr +
2013 ((unsigned long) __va(kern_base)) -
2014 ((unsigned long) KERNBASE));
2015 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2016
2017 if (do_free) {
2018 p = virt_to_page(page);
2019
2020 ClearPageReserved(p);
2021 init_page_count(p);
2022 __free_page(p);
2023 num_physpages++;
2024 totalram_pages++;
2025 }
2026 }
2027 }
2028
2029 #ifdef CONFIG_BLK_DEV_INITRD
2030 void free_initrd_mem(unsigned long start, unsigned long end)
2031 {
2032 if (start < end)
2033 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
2034 for (; start < end; start += PAGE_SIZE) {
2035 struct page *p = virt_to_page(start);
2036
2037 ClearPageReserved(p);
2038 init_page_count(p);
2039 __free_page(p);
2040 num_physpages++;
2041 totalram_pages++;
2042 }
2043 }
2044 #endif
2045
2046 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2047 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2048 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2049 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2050 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2051 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2052
2053 pgprot_t PAGE_KERNEL __read_mostly;
2054 EXPORT_SYMBOL(PAGE_KERNEL);
2055
2056 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2057 pgprot_t PAGE_COPY __read_mostly;
2058
2059 pgprot_t PAGE_SHARED __read_mostly;
2060 EXPORT_SYMBOL(PAGE_SHARED);
2061
2062 unsigned long pg_iobits __read_mostly;
2063
2064 unsigned long _PAGE_IE __read_mostly;
2065 EXPORT_SYMBOL(_PAGE_IE);
2066
2067 unsigned long _PAGE_E __read_mostly;
2068 EXPORT_SYMBOL(_PAGE_E);
2069
2070 unsigned long _PAGE_CACHE __read_mostly;
2071 EXPORT_SYMBOL(_PAGE_CACHE);
2072
2073 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2074 unsigned long vmemmap_table[VMEMMAP_SIZE];
2075
2076 int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
2077 {
2078 unsigned long vstart = (unsigned long) start;
2079 unsigned long vend = (unsigned long) (start + nr);
2080 unsigned long phys_start = (vstart - VMEMMAP_BASE);
2081 unsigned long phys_end = (vend - VMEMMAP_BASE);
2082 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2083 unsigned long end = VMEMMAP_ALIGN(phys_end);
2084 unsigned long pte_base;
2085
2086 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2087 _PAGE_CP_4U | _PAGE_CV_4U |
2088 _PAGE_P_4U | _PAGE_W_4U);
2089 if (tlb_type == hypervisor)
2090 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2091 _PAGE_CP_4V | _PAGE_CV_4V |
2092 _PAGE_P_4V | _PAGE_W_4V);
2093
2094 for (; addr < end; addr += VMEMMAP_CHUNK) {
2095 unsigned long *vmem_pp =
2096 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2097 void *block;
2098
2099 if (!(*vmem_pp & _PAGE_VALID)) {
2100 block = vmemmap_alloc_block(1UL << 22, node);
2101 if (!block)
2102 return -ENOMEM;
2103
2104 *vmem_pp = pte_base | __pa(block);
2105
2106 printk(KERN_INFO "[%p-%p] page_structs=%lu "
2107 "node=%d entry=%lu/%lu\n", start, block, nr,
2108 node,
2109 addr >> VMEMMAP_CHUNK_SHIFT,
2110 VMEMMAP_SIZE);
2111 }
2112 }
2113 return 0;
2114 }
2115 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2116
2117 static void prot_init_common(unsigned long page_none,
2118 unsigned long page_shared,
2119 unsigned long page_copy,
2120 unsigned long page_readonly,
2121 unsigned long page_exec_bit)
2122 {
2123 PAGE_COPY = __pgprot(page_copy);
2124 PAGE_SHARED = __pgprot(page_shared);
2125
2126 protection_map[0x0] = __pgprot(page_none);
2127 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2128 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2129 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2130 protection_map[0x4] = __pgprot(page_readonly);
2131 protection_map[0x5] = __pgprot(page_readonly);
2132 protection_map[0x6] = __pgprot(page_copy);
2133 protection_map[0x7] = __pgprot(page_copy);
2134 protection_map[0x8] = __pgprot(page_none);
2135 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2136 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2137 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2138 protection_map[0xc] = __pgprot(page_readonly);
2139 protection_map[0xd] = __pgprot(page_readonly);
2140 protection_map[0xe] = __pgprot(page_shared);
2141 protection_map[0xf] = __pgprot(page_shared);
2142 }
2143
2144 static void __init sun4u_pgprot_init(void)
2145 {
2146 unsigned long page_none, page_shared, page_copy, page_readonly;
2147 unsigned long page_exec_bit;
2148
2149 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2150 _PAGE_CACHE_4U | _PAGE_P_4U |
2151 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2152 _PAGE_EXEC_4U);
2153 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2154 _PAGE_CACHE_4U | _PAGE_P_4U |
2155 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2156 _PAGE_EXEC_4U | _PAGE_L_4U);
2157
2158 _PAGE_IE = _PAGE_IE_4U;
2159 _PAGE_E = _PAGE_E_4U;
2160 _PAGE_CACHE = _PAGE_CACHE_4U;
2161
2162 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2163 __ACCESS_BITS_4U | _PAGE_E_4U);
2164
2165 #ifdef CONFIG_DEBUG_PAGEALLOC
2166 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
2167 0xfffff80000000000UL;
2168 #else
2169 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2170 0xfffff80000000000UL;
2171 #endif
2172 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2173 _PAGE_P_4U | _PAGE_W_4U);
2174
2175 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2176
2177 _PAGE_SZBITS = _PAGE_SZBITS_4U;
2178 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2179 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2180 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2181
2182
2183 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2184 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2185 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2186 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2187 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2188 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2189 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2190
2191 page_exec_bit = _PAGE_EXEC_4U;
2192
2193 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2194 page_exec_bit);
2195 }
2196
2197 static void __init sun4v_pgprot_init(void)
2198 {
2199 unsigned long page_none, page_shared, page_copy, page_readonly;
2200 unsigned long page_exec_bit;
2201
2202 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2203 _PAGE_CACHE_4V | _PAGE_P_4V |
2204 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2205 _PAGE_EXEC_4V);
2206 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2207
2208 _PAGE_IE = _PAGE_IE_4V;
2209 _PAGE_E = _PAGE_E_4V;
2210 _PAGE_CACHE = _PAGE_CACHE_4V;
2211
2212 #ifdef CONFIG_DEBUG_PAGEALLOC
2213 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2214 0xfffff80000000000UL;
2215 #else
2216 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2217 0xfffff80000000000UL;
2218 #endif
2219 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2220 _PAGE_P_4V | _PAGE_W_4V);
2221
2222 #ifdef CONFIG_DEBUG_PAGEALLOC
2223 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2224 0xfffff80000000000UL;
2225 #else
2226 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2227 0xfffff80000000000UL;
2228 #endif
2229 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2230 _PAGE_P_4V | _PAGE_W_4V);
2231
2232 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2233 __ACCESS_BITS_4V | _PAGE_E_4V);
2234
2235 _PAGE_SZBITS = _PAGE_SZBITS_4V;
2236 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2237 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2238 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2239 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2240
2241 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2242 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2243 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2244 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2245 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2246 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2247 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2248
2249 page_exec_bit = _PAGE_EXEC_4V;
2250
2251 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2252 page_exec_bit);
2253 }
2254
2255 unsigned long pte_sz_bits(unsigned long sz)
2256 {
2257 if (tlb_type == hypervisor) {
2258 switch (sz) {
2259 case 8 * 1024:
2260 default:
2261 return _PAGE_SZ8K_4V;
2262 case 64 * 1024:
2263 return _PAGE_SZ64K_4V;
2264 case 512 * 1024:
2265 return _PAGE_SZ512K_4V;
2266 case 4 * 1024 * 1024:
2267 return _PAGE_SZ4MB_4V;
2268 };
2269 } else {
2270 switch (sz) {
2271 case 8 * 1024:
2272 default:
2273 return _PAGE_SZ8K_4U;
2274 case 64 * 1024:
2275 return _PAGE_SZ64K_4U;
2276 case 512 * 1024:
2277 return _PAGE_SZ512K_4U;
2278 case 4 * 1024 * 1024:
2279 return _PAGE_SZ4MB_4U;
2280 };
2281 }
2282 }
2283
2284 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2285 {
2286 pte_t pte;
2287
2288 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2289 pte_val(pte) |= (((unsigned long)space) << 32);
2290 pte_val(pte) |= pte_sz_bits(page_size);
2291
2292 return pte;
2293 }
2294
2295 static unsigned long kern_large_tte(unsigned long paddr)
2296 {
2297 unsigned long val;
2298
2299 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2300 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2301 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2302 if (tlb_type == hypervisor)
2303 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2304 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2305 _PAGE_EXEC_4V | _PAGE_W_4V);
2306
2307 return val | paddr;
2308 }
2309
2310 /* If not locked, zap it. */
2311 void __flush_tlb_all(void)
2312 {
2313 unsigned long pstate;
2314 int i;
2315
2316 __asm__ __volatile__("flushw\n\t"
2317 "rdpr %%pstate, %0\n\t"
2318 "wrpr %0, %1, %%pstate"
2319 : "=r" (pstate)
2320 : "i" (PSTATE_IE));
2321 if (tlb_type == hypervisor) {
2322 sun4v_mmu_demap_all();
2323 } else if (tlb_type == spitfire) {
2324 for (i = 0; i < 64; i++) {
2325 /* NOTE: Always runs on spitfire, so no
2326 * cheetah+ page size encodings.
2327 */
2328 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2329 "flush %%g6"
2330 : /* No outputs */
2331 : "r" (0),
2332 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2333
2334 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2335 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2336 "membar #Sync"
2337 : /* no outputs */
2338 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2339 spitfire_put_dtlb_data(i, 0x0UL);
2340 }
2341
2342 /* NOTE: Always runs on spitfire, so no
2343 * cheetah+ page size encodings.
2344 */
2345 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2346 "flush %%g6"
2347 : /* No outputs */
2348 : "r" (0),
2349 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2350
2351 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2352 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2353 "membar #Sync"
2354 : /* no outputs */
2355 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2356 spitfire_put_itlb_data(i, 0x0UL);
2357 }
2358 }
2359 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2360 cheetah_flush_dtlb_all();
2361 cheetah_flush_itlb_all();
2362 }
2363 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2364 : : "r" (pstate));
2365 }
Tomato firmware and modifications.