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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / sh / kernel / cpu / sh2a / fpu.c
bloba94250c52286dea82c59d897b7ce649755eed1f8
1
2 #include <linux/sched.h>
3 #include <linux/signal.h>
4 #include <asm/processor.h>
5 #include <asm/io.h>
6 #include <asm/fpu.h>
7
8 /* The PR (precision) bit in the FP Status Register must be clear when
9 * an frchg instruction is executed, otherwise the instruction is undefined.
10 * Executing frchg with PR set causes a trap on some SH4 implementations.
11 */
12
13 #define FPSCR_RCHG 0x00000000
14
15
16 /*
17 * Save FPU registers onto task structure.
18 */
19 void save_fpu(struct task_struct *tsk)
20 {
21 unsigned long dummy;
22
23 enable_fpu();
24 asm volatile("sts.l fpul, @-%0\n\t"
25 "sts.l fpscr, @-%0\n\t"
26 "fmov.s fr15, @-%0\n\t"
27 "fmov.s fr14, @-%0\n\t"
28 "fmov.s fr13, @-%0\n\t"
29 "fmov.s fr12, @-%0\n\t"
30 "fmov.s fr11, @-%0\n\t"
31 "fmov.s fr10, @-%0\n\t"
32 "fmov.s fr9, @-%0\n\t"
33 "fmov.s fr8, @-%0\n\t"
34 "fmov.s fr7, @-%0\n\t"
35 "fmov.s fr6, @-%0\n\t"
36 "fmov.s fr5, @-%0\n\t"
37 "fmov.s fr4, @-%0\n\t"
38 "fmov.s fr3, @-%0\n\t"
39 "fmov.s fr2, @-%0\n\t"
40 "fmov.s fr1, @-%0\n\t"
41 "fmov.s fr0, @-%0\n\t"
42 "lds %3, fpscr\n\t"
43 : "=r" (dummy)
44 : "0" ((char *)(&tsk->thread.xstate->hardfpu.status)),
45 "r" (FPSCR_RCHG),
46 "r" (FPSCR_INIT)
47 : "memory");
48
49 disable_fpu();
50 }
51
52 void restore_fpu(struct task_struct *tsk)
53 {
54 unsigned long dummy;
55
56 enable_fpu();
57 asm volatile("fmov.s @%0+, fr0\n\t"
58 "fmov.s @%0+, fr1\n\t"
59 "fmov.s @%0+, fr2\n\t"
60 "fmov.s @%0+, fr3\n\t"
61 "fmov.s @%0+, fr4\n\t"
62 "fmov.s @%0+, fr5\n\t"
63 "fmov.s @%0+, fr6\n\t"
64 "fmov.s @%0+, fr7\n\t"
65 "fmov.s @%0+, fr8\n\t"
66 "fmov.s @%0+, fr9\n\t"
67 "fmov.s @%0+, fr10\n\t"
68 "fmov.s @%0+, fr11\n\t"
69 "fmov.s @%0+, fr12\n\t"
70 "fmov.s @%0+, fr13\n\t"
71 "fmov.s @%0+, fr14\n\t"
72 "fmov.s @%0+, fr15\n\t"
73 "lds.l @%0+, fpscr\n\t"
74 "lds.l @%0+, fpul\n\t"
75 : "=r" (dummy)
76 : "0" (tsk->thread.xstate), "r" (FPSCR_RCHG)
77 : "memory");
78 disable_fpu();
79 }
80
81 /*
82 * Emulate arithmetic ops on denormalized number for some FPU insns.
83 */
84
85 /* denormalized float * float */
86 static int denormal_mulf(int hx, int hy)
87 {
88 unsigned int ix, iy;
89 unsigned long long m, n;
90 int exp, w;
91
92 ix = hx & 0x7fffffff;
93 iy = hy & 0x7fffffff;
94 if (iy < 0x00800000 || ix == 0)
95 return ((hx ^ hy) & 0x80000000);
96
97 exp = (iy & 0x7f800000) >> 23;
98 ix &= 0x007fffff;
99 iy = (iy & 0x007fffff) | 0x00800000;
100 m = (unsigned long long)ix * iy;
101 n = m;
102 w = -1;
103 while (n) { n >>= 1; w++; }
104
105 exp += w - 126 - 46;
106 if (exp > 0)
107 ix = ((int) (m >> (w - 23)) & 0x007fffff) | (exp << 23);
108 else if (exp + 22 >= 0)
109 ix = (int) (m >> (w - 22 - exp)) & 0x007fffff;
110 else
111 ix = 0;
112
113 ix |= (hx ^ hy) & 0x80000000;
114 return ix;
115 }
116
117 /* denormalized double * double */
118 static void mult64(unsigned long long x, unsigned long long y,
119 unsigned long long *highp, unsigned long long *lowp)
120 {
121 unsigned long long sub0, sub1, sub2, sub3;
122 unsigned long long high, low;
123
124 sub0 = (x >> 32) * (unsigned long) (y >> 32);
125 sub1 = (x & 0xffffffffLL) * (unsigned long) (y >> 32);
126 sub2 = (x >> 32) * (unsigned long) (y & 0xffffffffLL);
127 sub3 = (x & 0xffffffffLL) * (unsigned long) (y & 0xffffffffLL);
128 low = sub3;
129 high = 0LL;
130 sub3 += (sub1 << 32);
131 if (low > sub3)
132 high++;
133 low = sub3;
134 sub3 += (sub2 << 32);
135 if (low > sub3)
136 high++;
137 low = sub3;
138 high += (sub1 >> 32) + (sub2 >> 32);
139 high += sub0;
140 *lowp = low;
141 *highp = high;
142 }
143
144 static inline long long rshift64(unsigned long long mh,
145 unsigned long long ml, int n)
146 {
147 if (n >= 64)
148 return mh >> (n - 64);
149 return (mh << (64 - n)) | (ml >> n);
150 }
151
152 static long long denormal_muld(long long hx, long long hy)
153 {
154 unsigned long long ix, iy;
155 unsigned long long mh, ml, nh, nl;
156 int exp, w;
157
158 ix = hx & 0x7fffffffffffffffLL;
159 iy = hy & 0x7fffffffffffffffLL;
160 if (iy < 0x0010000000000000LL || ix == 0)
161 return ((hx ^ hy) & 0x8000000000000000LL);
162
163 exp = (iy & 0x7ff0000000000000LL) >> 52;
164 ix &= 0x000fffffffffffffLL;
165 iy = (iy & 0x000fffffffffffffLL) | 0x0010000000000000LL;
166 mult64(ix, iy, &mh, &ml);
167 nh = mh;
168 nl = ml;
169 w = -1;
170 if (nh) {
171 while (nh) { nh >>= 1; w++;}
172 w += 64;
173 } else
174 while (nl) { nl >>= 1; w++;}
175
176 exp += w - 1022 - 52 * 2;
177 if (exp > 0)
178 ix = (rshift64(mh, ml, w - 52) & 0x000fffffffffffffLL)
179 | ((long long)exp << 52);
180 else if (exp + 51 >= 0)
181 ix = rshift64(mh, ml, w - 51 - exp) & 0x000fffffffffffffLL;
182 else
183 ix = 0;
184
185 ix |= (hx ^ hy) & 0x8000000000000000LL;
186 return ix;
187 }
188
189 /* ix - iy where iy: denormal and ix, iy >= 0 */
190 static int denormal_subf1(unsigned int ix, unsigned int iy)
191 {
192 int frac;
193 int exp;
194
195 if (ix < 0x00800000)
196 return ix - iy;
197
198 exp = (ix & 0x7f800000) >> 23;
199 if (exp - 1 > 31)
200 return ix;
201 iy >>= exp - 1;
202 if (iy == 0)
203 return ix;
204
205 frac = (ix & 0x007fffff) | 0x00800000;
206 frac -= iy;
207 while (frac < 0x00800000) {
208 if (--exp == 0)
209 return frac;
210 frac <<= 1;
211 }
212
213 return (exp << 23) | (frac & 0x007fffff);
214 }
215
216 /* ix + iy where iy: denormal and ix, iy >= 0 */
217 static int denormal_addf1(unsigned int ix, unsigned int iy)
218 {
219 int frac;
220 int exp;
221
222 if (ix < 0x00800000)
223 return ix + iy;
224
225 exp = (ix & 0x7f800000) >> 23;
226 if (exp - 1 > 31)
227 return ix;
228 iy >>= exp - 1;
229 if (iy == 0)
230 return ix;
231
232 frac = (ix & 0x007fffff) | 0x00800000;
233 frac += iy;
234 if (frac >= 0x01000000) {
235 frac >>= 1;
236 ++exp;
237 }
238
239 return (exp << 23) | (frac & 0x007fffff);
240 }
241
242 static int denormal_addf(int hx, int hy)
243 {
244 unsigned int ix, iy;
245 int sign;
246
247 if ((hx ^ hy) & 0x80000000) {
248 sign = hx & 0x80000000;
249 ix = hx & 0x7fffffff;
250 iy = hy & 0x7fffffff;
251 if (iy < 0x00800000) {
252 ix = denormal_subf1(ix, iy);
253 if ((int) ix < 0) {
254 ix = -ix;
255 sign ^= 0x80000000;
256 }
257 } else {
258 ix = denormal_subf1(iy, ix);
259 sign ^= 0x80000000;
260 }
261 } else {
262 sign = hx & 0x80000000;
263 ix = hx & 0x7fffffff;
264 iy = hy & 0x7fffffff;
265 if (iy < 0x00800000)
266 ix = denormal_addf1(ix, iy);
267 else
268 ix = denormal_addf1(iy, ix);
269 }
270
271 return sign | ix;
272 }
273
274 /* ix - iy where iy: denormal and ix, iy >= 0 */
275 static long long denormal_subd1(unsigned long long ix, unsigned long long iy)
276 {
277 long long frac;
278 int exp;
279
280 if (ix < 0x0010000000000000LL)
281 return ix - iy;
282
283 exp = (ix & 0x7ff0000000000000LL) >> 52;
284 if (exp - 1 > 63)
285 return ix;
286 iy >>= exp - 1;
287 if (iy == 0)
288 return ix;
289
290 frac = (ix & 0x000fffffffffffffLL) | 0x0010000000000000LL;
291 frac -= iy;
292 while (frac < 0x0010000000000000LL) {
293 if (--exp == 0)
294 return frac;
295 frac <<= 1;
296 }
297
298 return ((long long)exp << 52) | (frac & 0x000fffffffffffffLL);
299 }
300
301 /* ix + iy where iy: denormal and ix, iy >= 0 */
302 static long long denormal_addd1(unsigned long long ix, unsigned long long iy)
303 {
304 long long frac;
305 long long exp;
306
307 if (ix < 0x0010000000000000LL)
308 return ix + iy;
309
310 exp = (ix & 0x7ff0000000000000LL) >> 52;
311 if (exp - 1 > 63)
312 return ix;
313 iy >>= exp - 1;
314 if (iy == 0)
315 return ix;
316
317 frac = (ix & 0x000fffffffffffffLL) | 0x0010000000000000LL;
318 frac += iy;
319 if (frac >= 0x0020000000000000LL) {
320 frac >>= 1;
321 ++exp;
322 }
323
324 return (exp << 52) | (frac & 0x000fffffffffffffLL);
325 }
326
327 static long long denormal_addd(long long hx, long long hy)
328 {
329 unsigned long long ix, iy;
330 long long sign;
331
332 if ((hx ^ hy) & 0x8000000000000000LL) {
333 sign = hx & 0x8000000000000000LL;
334 ix = hx & 0x7fffffffffffffffLL;
335 iy = hy & 0x7fffffffffffffffLL;
336 if (iy < 0x0010000000000000LL) {
337 ix = denormal_subd1(ix, iy);
338 if ((int) ix < 0) {
339 ix = -ix;
340 sign ^= 0x8000000000000000LL;
341 }
342 } else {
343 ix = denormal_subd1(iy, ix);
344 sign ^= 0x8000000000000000LL;
345 }
346 } else {
347 sign = hx & 0x8000000000000000LL;
348 ix = hx & 0x7fffffffffffffffLL;
349 iy = hy & 0x7fffffffffffffffLL;
350 if (iy < 0x0010000000000000LL)
351 ix = denormal_addd1(ix, iy);
352 else
353 ix = denormal_addd1(iy, ix);
354 }
355
356 return sign | ix;
357 }
358
359 /**
360 * denormal_to_double - Given denormalized float number,
361 * store double float
362 *
363 * @fpu: Pointer to sh_fpu_hard structure
364 * @n: Index to FP register
365 */
366 static void
367 denormal_to_double (struct sh_fpu_hard_struct *fpu, int n)
368 {
369 unsigned long du, dl;
370 unsigned long x = fpu->fpul;
371 int exp = 1023 - 126;
372
373 if (x != 0 && (x & 0x7f800000) == 0) {
374 du = (x & 0x80000000);
375 while ((x & 0x00800000) == 0) {
376 x <<= 1;
377 exp--;
378 }
379 x &= 0x007fffff;
380 du |= (exp << 20) | (x >> 3);
381 dl = x << 29;
382
383 fpu->fp_regs[n] = du;
384 fpu->fp_regs[n+1] = dl;
385 }
386 }
387
388 /**
389 * ieee_fpe_handler - Handle denormalized number exception
390 *
391 * @regs: Pointer to register structure
392 *
393 * Returns 1 when it's handled (should not cause exception).
394 */
395 static int
396 ieee_fpe_handler (struct pt_regs *regs)
397 {
398 unsigned short insn = *(unsigned short *) regs->pc;
399 unsigned short finsn;
400 unsigned long nextpc;
401 int nib[4] = {
402 (insn >> 12) & 0xf,
403 (insn >> 8) & 0xf,
404 (insn >> 4) & 0xf,
405 insn & 0xf};
406
407 if (nib[0] == 0xb ||
408 (nib[0] == 0x4 && nib[2] == 0x0 && nib[3] == 0xb)) /* bsr & jsr */
409 regs->pr = regs->pc + 4;
410 if (nib[0] == 0xa || nib[0] == 0xb) { /* bra & bsr */
411 nextpc = regs->pc + 4 + ((short) ((insn & 0xfff) << 4) >> 3);
412 finsn = *(unsigned short *) (regs->pc + 2);
413 } else if (nib[0] == 0x8 && nib[1] == 0xd) { /* bt/s */
414 if (regs->sr & 1)
415 nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1);
416 else
417 nextpc = regs->pc + 4;
418 finsn = *(unsigned short *) (regs->pc + 2);
419 } else if (nib[0] == 0x8 && nib[1] == 0xf) { /* bf/s */
420 if (regs->sr & 1)
421 nextpc = regs->pc + 4;
422 else
423 nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1);
424 finsn = *(unsigned short *) (regs->pc + 2);
425 } else if (nib[0] == 0x4 && nib[3] == 0xb &&
426 (nib[2] == 0x0 || nib[2] == 0x2)) { /* jmp & jsr */
427 nextpc = regs->regs[nib[1]];
428 finsn = *(unsigned short *) (regs->pc + 2);
429 } else if (nib[0] == 0x0 && nib[3] == 0x3 &&
430 (nib[2] == 0x0 || nib[2] == 0x2)) { /* braf & bsrf */
431 nextpc = regs->pc + 4 + regs->regs[nib[1]];
432 finsn = *(unsigned short *) (regs->pc + 2);
433 } else if (insn == 0x000b) { /* rts */
434 nextpc = regs->pr;
435 finsn = *(unsigned short *) (regs->pc + 2);
436 } else {
437 nextpc = regs->pc + 2;
438 finsn = insn;
439 }
440
441 #define FPSCR_FPU_ERROR (1 << 17)
442
443 if ((finsn & 0xf1ff) == 0xf0ad) { /* fcnvsd */
444 struct task_struct *tsk = current;
445
446 if ((tsk->thread.xstate->hardfpu.fpscr & FPSCR_FPU_ERROR)) {
447 /* FPU error */
448 denormal_to_double (&tsk->thread.xstate->hardfpu,
449 (finsn >> 8) & 0xf);
450 } else
451 return 0;
452
453 regs->pc = nextpc;
454 return 1;
455 } else if ((finsn & 0xf00f) == 0xf002) { /* fmul */
456 struct task_struct *tsk = current;
457 int fpscr;
458 int n, m, prec;
459 unsigned int hx, hy;
460
461 n = (finsn >> 8) & 0xf;
462 m = (finsn >> 4) & 0xf;
463 hx = tsk->thread.xstate->hardfpu.fp_regs[n];
464 hy = tsk->thread.xstate->hardfpu.fp_regs[m];
465 fpscr = tsk->thread.xstate->hardfpu.fpscr;
466 prec = fpscr & (1 << 19);
467
468 if ((fpscr & FPSCR_FPU_ERROR)
469 && (prec && ((hx & 0x7fffffff) < 0x00100000
470 || (hy & 0x7fffffff) < 0x00100000))) {
471 long long llx, lly;
472
473 /* FPU error because of denormal */
474 llx = ((long long) hx << 32)
475 | tsk->thread.xstate->hardfpu.fp_regs[n+1];
476 lly = ((long long) hy << 32)
477 | tsk->thread.xstate->hardfpu.fp_regs[m+1];
478 if ((hx & 0x7fffffff) >= 0x00100000)
479 llx = denormal_muld(lly, llx);
480 else
481 llx = denormal_muld(llx, lly);
482 tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
483 tsk->thread.xstate->hardfpu.fp_regs[n+1] = llx & 0xffffffff;
484 } else if ((fpscr & FPSCR_FPU_ERROR)
485 && (!prec && ((hx & 0x7fffffff) < 0x00800000
486 || (hy & 0x7fffffff) < 0x00800000))) {
487 /* FPU error because of denormal */
488 if ((hx & 0x7fffffff) >= 0x00800000)
489 hx = denormal_mulf(hy, hx);
490 else
491 hx = denormal_mulf(hx, hy);
492 tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
493 } else
494 return 0;
495
496 regs->pc = nextpc;
497 return 1;
498 } else if ((finsn & 0xf00e) == 0xf000) { /* fadd, fsub */
499 struct task_struct *tsk = current;
500 int fpscr;
501 int n, m, prec;
502 unsigned int hx, hy;
503
504 n = (finsn >> 8) & 0xf;
505 m = (finsn >> 4) & 0xf;
506 hx = tsk->thread.xstate->hardfpu.fp_regs[n];
507 hy = tsk->thread.xstate->hardfpu.fp_regs[m];
508 fpscr = tsk->thread.xstate->hardfpu.fpscr;
509 prec = fpscr & (1 << 19);
510
511 if ((fpscr & FPSCR_FPU_ERROR)
512 && (prec && ((hx & 0x7fffffff) < 0x00100000
513 || (hy & 0x7fffffff) < 0x00100000))) {
514 long long llx, lly;
515
516 /* FPU error because of denormal */
517 llx = ((long long) hx << 32)
518 | tsk->thread.xstate->hardfpu.fp_regs[n+1];
519 lly = ((long long) hy << 32)
520 | tsk->thread.xstate->hardfpu.fp_regs[m+1];
521 if ((finsn & 0xf00f) == 0xf000)
522 llx = denormal_addd(llx, lly);
523 else
524 llx = denormal_addd(llx, lly ^ (1LL << 63));
525 tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
526 tsk->thread.xstate->hardfpu.fp_regs[n+1] = llx & 0xffffffff;
527 } else if ((fpscr & FPSCR_FPU_ERROR)
528 && (!prec && ((hx & 0x7fffffff) < 0x00800000
529 || (hy & 0x7fffffff) < 0x00800000))) {
530 /* FPU error because of denormal */
531 if ((finsn & 0xf00f) == 0xf000)
532 hx = denormal_addf(hx, hy);
533 else
534 hx = denormal_addf(hx, hy ^ 0x80000000);
535 tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
536 } else
537 return 0;
538
539 regs->pc = nextpc;
540 return 1;
541 }
542
543 return 0;
544 }
545
546 BUILD_TRAP_HANDLER(fpu_error)
547 {
548 struct task_struct *tsk = current;
549 TRAP_HANDLER_DECL;
550
551 __unlazy_fpu(tsk, regs);
552 if (ieee_fpe_handler(regs)) {
553 tsk->thread.xstate->hardfpu.fpscr &=
554 ~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK);
555 grab_fpu(regs);
556 restore_fpu(tsk);
557 task_thread_info(tsk)->status |= TS_USEDFPU;
558 return;
559 }
560
561 force_sig(SIGFPE, tsk);
562 }
Tomato firmware and modifications.