release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/include/asm/system_64.h

   1 #ifndef __ASM_SH_SYSTEM_64_H
   2 #define __ASM_SH_SYSTEM_64_H
   3
   4 /*
   5  * include/asm-sh/system_64.h
   6  *
   7  * Copyright (C) 2000, 2001  Paolo Alberelli
   8  * Copyright (C) 2003  Paul Mundt
   9  * Copyright (C) 2004  Richard Curnow
  10  *
  11  * This file is subject to the terms and conditions of the GNU General Public
  12  * License.  See the file "COPYING" in the main directory of this archive
  13  * for more details.
  14  */
  15 #include <cpu/registers.h>
  16 #include <asm/processor.h>
  17
  18 /*
  19  *      switch_to() should switch tasks to task nr n, first
  20  */
  21 struct thread_struct;
  22 struct task_struct *sh64_switch_to(struct task_struct *prev,
  23                                    struct thread_struct *prev_thread,
  24                                    struct task_struct *next,
  25                                    struct thread_struct *next_thread);
  26
  27 #define switch_to(prev,next,last)                               \
  28 do {                                                            \
  29         if (last_task_used_math != next) {                      \
  30                 struct pt_regs *regs = next->thread.uregs;      \
  31                 if (regs) regs->sr |= SR_FD;                    \
  32         }                                                       \
  33         last = sh64_switch_to(prev, &prev->thread, next,        \
  34                               &next->thread);                   \
  35 } while (0)
  36
  37 #define jump_to_uncached()      do { } while (0)
  38 #define back_to_cached()        do { } while (0)
  39
  40 #define __icbi(addr)    __asm__ __volatile__ ( "icbi %0, 0\n\t" : : "r" (addr))
  41 #define __ocbp(addr)    __asm__ __volatile__ ( "ocbp %0, 0\n\t" : : "r" (addr))
  42 #define __ocbi(addr)    __asm__ __volatile__ ( "ocbi %0, 0\n\t" : : "r" (addr))
  43 #define __ocbwb(addr)   __asm__ __volatile__ ( "ocbwb %0, 0\n\t" : : "r" (addr))
  44
  45 static inline reg_size_t register_align(void *val)
  46 {
  47         return (unsigned long long)(signed long long)(signed long)val;
  48 }
  49
  50 extern void phys_stext(void);
  51
  52 static inline void trigger_address_error(void)
  53 {
  54         phys_stext();
  55 }
  56
  57 #define SR_BL_LL        0x0000000010000000LL
  58
  59 static inline void set_bl_bit(void)
  60 {
  61         unsigned long long __dummy0, __dummy1 = SR_BL_LL;
  62
  63         __asm__ __volatile__("getcon    " __SR ", %0\n\t"
  64                              "or        %0, %1, %0\n\t"
  65                              "putcon    %0, " __SR "\n\t"
  66                              : "=&r" (__dummy0)
  67                              : "r" (__dummy1));
  68
  69 }
  70
  71 static inline void clear_bl_bit(void)
  72 {
  73         unsigned long long __dummy0, __dummy1 = ~SR_BL_LL;
  74
  75         __asm__ __volatile__("getcon    " __SR ", %0\n\t"
  76                              "and       %0, %1, %0\n\t"
  77                              "putcon    %0, " __SR "\n\t"
  78                              : "=&r" (__dummy0)
  79                              : "r" (__dummy1));
  80 }
  81
  82 #endif /* __ASM_SH_SYSTEM_64_H */