release/src-rt-6.x.4708/linux/linux-2.6.36/arch/powerpc/sysdev/cpm_common.c

   1 /*
   2  * Common CPM code
   3  *
   4  * Author: Scott Wood <scottwood@freescale.com>
   5  *
   6  * Copyright 2007 Freescale Semiconductor, Inc.
   7  *
   8  * Some parts derived from commproc.c/cpm2_common.c, which is:
   9  * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
  10  * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
  11  * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
  12  * 2006 (c) MontaVista Software, Inc.
  13  * Vitaly Bordug <vbordug@ru.mvista.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of version 2 of the GNU General Public License as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/of_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/of.h>
  24 #include <linux/slab.h>
  25
  26 #include <asm/udbg.h>
  27 #include <asm/io.h>
  28 #include <asm/system.h>
  29 #include <asm/rheap.h>
  30 #include <asm/cpm.h>
  31
  32 #include <mm/mmu_decl.h>
  33
  34 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
  35 #include <linux/of_gpio.h>
  36 #endif
  37
  38 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
  39 static u32 __iomem *cpm_udbg_txdesc =
  40         (u32 __iomem __force *)CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;
  41
  42 static void udbg_putc_cpm(char c)
  43 {
  44         u8 __iomem *txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]);
  45
  46         if (c == '\n')
  47                 udbg_putc_cpm('\r');
  48
  49         while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000)
  50                 ;
  51
  52         out_8(txbuf, c);
  53         out_be32(&cpm_udbg_txdesc[0], 0xa0000001);
  54 }
  55
  56 void __init udbg_init_cpm(void)
  57 {
  58         if (cpm_udbg_txdesc) {
  59 #ifdef CONFIG_CPM2
  60                 setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG);
  61 #endif
  62                 udbg_putc = udbg_putc_cpm;
  63         }
  64 }
  65 #endif
  66
  67 static spinlock_t cpm_muram_lock;
  68 static rh_block_t cpm_boot_muram_rh_block[16];
  69 static rh_info_t cpm_muram_info;
  70 static u8 __iomem *muram_vbase;
  71 static phys_addr_t muram_pbase;
  72
  73 /* Max address size we deal with */
  74 #define OF_MAX_ADDR_CELLS       4
  75
  76 int cpm_muram_init(void)
  77 {
  78         struct device_node *np;
  79         struct resource r;
  80         u32 zero[OF_MAX_ADDR_CELLS] = {};
  81         resource_size_t max = 0;
  82         int i = 0;
  83         int ret = 0;
  84
  85         if (muram_pbase)
  86                 return 0;
  87
  88         spin_lock_init(&cpm_muram_lock);
  89         /* initialize the info header */
  90         rh_init(&cpm_muram_info, 1,
  91                 sizeof(cpm_boot_muram_rh_block) /
  92                 sizeof(cpm_boot_muram_rh_block[0]),
  93                 cpm_boot_muram_rh_block);
  94
  95         np = of_find_compatible_node(NULL, NULL, "fsl,cpm-muram-data");
  96         if (!np) {
  97                 /* try legacy bindings */
  98                 np = of_find_node_by_name(NULL, "data-only");
  99                 if (!np) {
 100                         printk(KERN_ERR "Cannot find CPM muram data node");
 101                         ret = -ENODEV;
 102                         goto out;
 103                 }
 104         }
 105
 106         muram_pbase = of_translate_address(np, zero);
 107         if (muram_pbase == (phys_addr_t)OF_BAD_ADDR) {
 108                 printk(KERN_ERR "Cannot translate zero through CPM muram node");
 109                 ret = -ENODEV;
 110                 goto out;
 111         }
 112
 113         while (of_address_to_resource(np, i++, &r) == 0) {
 114                 if (r.end > max)
 115                         max = r.end;
 116
 117                 rh_attach_region(&cpm_muram_info, r.start - muram_pbase,
 118                                  r.end - r.start + 1);
 119         }
 120
 121         muram_vbase = ioremap(muram_pbase, max - muram_pbase + 1);
 122         if (!muram_vbase) {
 123                 printk(KERN_ERR "Cannot map CPM muram");
 124                 ret = -ENOMEM;
 125         }
 126
 127 out:
 128         of_node_put(np);
 129         return ret;
 130 }
 131
 132 /**
 133  * cpm_muram_alloc - allocate the requested size worth of multi-user ram
 134  * @size: number of bytes to allocate
 135  * @align: requested alignment, in bytes
 136  *
 137  * This function returns an offset into the muram area.
 138  * Use cpm_dpram_addr() to get the virtual address of the area.
 139  * Use cpm_muram_free() to free the allocation.
 140  */
 141 unsigned long cpm_muram_alloc(unsigned long size, unsigned long align)
 142 {
 143         unsigned long start;
 144         unsigned long flags;
 145
 146         spin_lock_irqsave(&cpm_muram_lock, flags);
 147         cpm_muram_info.alignment = align;
 148         start = rh_alloc(&cpm_muram_info, size, "commproc");
 149         spin_unlock_irqrestore(&cpm_muram_lock, flags);
 150
 151         return start;
 152 }
 153 EXPORT_SYMBOL(cpm_muram_alloc);
 154
 155 /**
 156  * cpm_muram_free - free a chunk of multi-user ram
 157  * @offset: The beginning of the chunk as returned by cpm_muram_alloc().
 158  */
 159 int cpm_muram_free(unsigned long offset)
 160 {
 161         int ret;
 162         unsigned long flags;
 163
 164         spin_lock_irqsave(&cpm_muram_lock, flags);
 165         ret = rh_free(&cpm_muram_info, offset);
 166         spin_unlock_irqrestore(&cpm_muram_lock, flags);
 167
 168         return ret;
 169 }
 170 EXPORT_SYMBOL(cpm_muram_free);
 171
 172 /**
 173  * cpm_muram_alloc_fixed - reserve a specific region of multi-user ram
 174  * @offset: the offset into the muram area to reserve
 175  * @size: the number of bytes to reserve
 176  *
 177  * This function returns "start" on success, -ENOMEM on failure.
 178  * Use cpm_dpram_addr() to get the virtual address of the area.
 179  * Use cpm_muram_free() to free the allocation.
 180  */
 181 unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size)
 182 {
 183         unsigned long start;
 184         unsigned long flags;
 185
 186         spin_lock_irqsave(&cpm_muram_lock, flags);
 187         cpm_muram_info.alignment = 1;
 188         start = rh_alloc_fixed(&cpm_muram_info, offset, size, "commproc");
 189         spin_unlock_irqrestore(&cpm_muram_lock, flags);
 190
 191         return start;
 192 }
 193 EXPORT_SYMBOL(cpm_muram_alloc_fixed);
 194
 195 /**
 196  * cpm_muram_addr - turn a muram offset into a virtual address
 197  * @offset: muram offset to convert
 198  */
 199 void __iomem *cpm_muram_addr(unsigned long offset)
 200 {
 201         return muram_vbase + offset;
 202 }
 203 EXPORT_SYMBOL(cpm_muram_addr);
 204
 205 unsigned long cpm_muram_offset(void __iomem *addr)
 206 {
 207         return addr - (void __iomem *)muram_vbase;
 208 }
 209 EXPORT_SYMBOL(cpm_muram_offset);
 210
 211 /**
 212  * cpm_muram_dma - turn a muram virtual address into a DMA address
 213  * @offset: virtual address from cpm_muram_addr() to convert
 214  */
 215 dma_addr_t cpm_muram_dma(void __iomem *addr)
 216 {
 217         return muram_pbase + ((u8 __iomem *)addr - muram_vbase);
 218 }
 219 EXPORT_SYMBOL(cpm_muram_dma);
 220
 221 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
 222
 223 struct cpm2_ioports {
 224         u32 dir, par, sor, odr, dat;
 225         u32 res[3];
 226 };
 227
 228 struct cpm2_gpio32_chip {
 229         struct of_mm_gpio_chip mm_gc;
 230         spinlock_t lock;
 231
 232         /* shadowed data register to clear/set bits safely */
 233         u32 cpdata;
 234 };
 235
 236 static inline struct cpm2_gpio32_chip *
 237 to_cpm2_gpio32_chip(struct of_mm_gpio_chip *mm_gc)
 238 {
 239         return container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc);
 240 }
 241
 242 static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
 243 {
 244         struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
 245         struct cpm2_ioports __iomem *iop = mm_gc->regs;
 246
 247         cpm2_gc->cpdata = in_be32(&iop->dat);
 248 }
 249
 250 static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
 251 {
 252         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 253         struct cpm2_ioports __iomem *iop = mm_gc->regs;
 254         u32 pin_mask;
 255
 256         pin_mask = 1 << (31 - gpio);
 257
 258         return !!(in_be32(&iop->dat) & pin_mask);
 259 }
 260
 261 static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
 262         int value)
 263 {
 264         struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
 265         struct cpm2_ioports __iomem *iop = mm_gc->regs;
 266
 267         if (value)
 268                 cpm2_gc->cpdata |= pin_mask;
 269         else
 270                 cpm2_gc->cpdata &= ~pin_mask;
 271
 272         out_be32(&iop->dat, cpm2_gc->cpdata);
 273 }
 274
 275 static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
 276 {
 277         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 278         struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
 279         unsigned long flags;
 280         u32 pin_mask = 1 << (31 - gpio);
 281
 282         spin_lock_irqsave(&cpm2_gc->lock, flags);
 283
 284         __cpm2_gpio32_set(mm_gc, pin_mask, value);
 285
 286         spin_unlock_irqrestore(&cpm2_gc->lock, flags);
 287 }
 288
 289 static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 290 {
 291         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 292         struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
 293         struct cpm2_ioports __iomem *iop = mm_gc->regs;
 294         unsigned long flags;
 295         u32 pin_mask = 1 << (31 - gpio);
 296
 297         spin_lock_irqsave(&cpm2_gc->lock, flags);
 298
 299         setbits32(&iop->dir, pin_mask);
 300         __cpm2_gpio32_set(mm_gc, pin_mask, val);
 301
 302         spin_unlock_irqrestore(&cpm2_gc->lock, flags);
 303
 304         return 0;
 305 }
 306
 307 static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
 308 {
 309         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 310         struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
 311         struct cpm2_ioports __iomem *iop = mm_gc->regs;
 312         unsigned long flags;
 313         u32 pin_mask = 1 << (31 - gpio);
 314
 315         spin_lock_irqsave(&cpm2_gc->lock, flags);
 316
 317         clrbits32(&iop->dir, pin_mask);
 318
 319         spin_unlock_irqrestore(&cpm2_gc->lock, flags);
 320
 321         return 0;
 322 }
 323
 324 int cpm2_gpiochip_add32(struct device_node *np)
 325 {
 326         struct cpm2_gpio32_chip *cpm2_gc;
 327         struct of_mm_gpio_chip *mm_gc;
 328         struct gpio_chip *gc;
 329
 330         cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
 331         if (!cpm2_gc)
 332                 return -ENOMEM;
 333
 334         spin_lock_init(&cpm2_gc->lock);
 335
 336         mm_gc = &cpm2_gc->mm_gc;
 337         gc = &mm_gc->gc;
 338
 339         mm_gc->save_regs = cpm2_gpio32_save_regs;
 340         gc->ngpio = 32;
 341         gc->direction_input = cpm2_gpio32_dir_in;
 342         gc->direction_output = cpm2_gpio32_dir_out;
 343         gc->get = cpm2_gpio32_get;
 344         gc->set = cpm2_gpio32_set;
 345
 346         return of_mm_gpiochip_add(np, mm_gc);
 347 }
 348 #endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */