release/src-rt-6.x.4708/linux/linux-2.6.36/arch/powerpc/platforms/pasemi/pci.c

   1 /*
   2  * Copyright (C) 2006 PA Semi, Inc
   3  *
   4  * Authors: Kip Walker, PA Semi
   5  *          Olof Johansson, PA Semi
   6  *
   7  * Maintained by: Olof Johansson <olof@lixom.net>
   8  *
   9  * Based on arch/powerpc/platforms/maple/pci.c
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25
  26 #include <linux/kernel.h>
  27 #include <linux/pci.h>
  28
  29 #include <asm/pci-bridge.h>
  30 #include <asm/machdep.h>
  31
  32 #include <asm/ppc-pci.h>
  33
  34 #define PA_PXP_CFA(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
  35
  36 static inline int pa_pxp_offset_valid(u8 bus, u8 devfn, int offset)
  37 {
  38         /* Device 0 Function 0 is special: It's config space spans function 1 as
  39          * well, so allow larger offset. It's really a two-function device but the
  40          * second function does not probe.
  41          */
  42         if (bus == 0 && devfn == 0)
  43                 return offset < 8192;
  44         else
  45                 return offset < 4096;
  46 }
  47
  48 static void volatile __iomem *pa_pxp_cfg_addr(struct pci_controller *hose,
  49                                        u8 bus, u8 devfn, int offset)
  50 {
  51         return hose->cfg_data + PA_PXP_CFA(bus, devfn, offset);
  52 }
  53
  54 static inline int is_root_port(int busno, int devfn)
  55 {
  56         return ((busno == 0) && (PCI_FUNC(devfn) < 4) &&
  57                  ((PCI_SLOT(devfn) == 16) || (PCI_SLOT(devfn) == 17)));
  58 }
  59
  60 static inline int is_5945_reg(int reg)
  61 {
  62         return (((reg >= 0x18) && (reg < 0x34)) ||
  63                 ((reg >= 0x158) && (reg < 0x178)));
  64 }
  65
  66 static int workaround_5945(struct pci_bus *bus, unsigned int devfn,
  67                            int offset, int len, u32 *val)
  68 {
  69         struct pci_controller *hose;
  70         void volatile __iomem *addr, *dummy;
  71         int byte;
  72         u32 tmp;
  73
  74         if (!is_root_port(bus->number, devfn) || !is_5945_reg(offset))
  75                 return 0;
  76
  77         hose = pci_bus_to_host(bus);
  78
  79         addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset & ~0x3);
  80         byte = offset & 0x3;
  81
  82         dummy = pa_pxp_cfg_addr(hose, bus->number, devfn, 0x10);
  83         out_le32(dummy, 0);
  84         tmp = in_le32(addr);
  85         out_le32(addr, tmp);
  86
  87         switch (len) {
  88         case 1:
  89                 *val = (tmp >> (8*byte)) & 0xff;
  90                 break;
  91         case 2:
  92                 if (byte == 0)
  93                         *val = tmp & 0xffff;
  94                 else
  95                         *val = (tmp >> 16) & 0xffff;
  96                 break;
  97         default:
  98                 *val = tmp;
  99                 break;
 100         }
 101
 102         return 1;
 103 }
 104
 105 static int pa_pxp_read_config(struct pci_bus *bus, unsigned int devfn,
 106                               int offset, int len, u32 *val)
 107 {
 108         struct pci_controller *hose;
 109         void volatile __iomem *addr;
 110
 111         hose = pci_bus_to_host(bus);
 112         if (!hose)
 113                 return PCIBIOS_DEVICE_NOT_FOUND;
 114
 115         if (!pa_pxp_offset_valid(bus->number, devfn, offset))
 116                 return PCIBIOS_BAD_REGISTER_NUMBER;
 117
 118         if (workaround_5945(bus, devfn, offset, len, val))
 119                 return PCIBIOS_SUCCESSFUL;
 120
 121         addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset);
 122
 123         /*
 124          * Note: the caller has already checked that offset is
 125          * suitably aligned and that len is 1, 2 or 4.
 126          */
 127         switch (len) {
 128         case 1:
 129                 *val = in_8(addr);
 130                 break;
 131         case 2:
 132                 *val = in_le16(addr);
 133                 break;
 134         default:
 135                 *val = in_le32(addr);
 136                 break;
 137         }
 138
 139         return PCIBIOS_SUCCESSFUL;
 140 }
 141
 142 static int pa_pxp_write_config(struct pci_bus *bus, unsigned int devfn,
 143                                int offset, int len, u32 val)
 144 {
 145         struct pci_controller *hose;
 146         void volatile __iomem *addr;
 147
 148         hose = pci_bus_to_host(bus);
 149         if (!hose)
 150                 return PCIBIOS_DEVICE_NOT_FOUND;
 151
 152         if (!pa_pxp_offset_valid(bus->number, devfn, offset))
 153                 return PCIBIOS_BAD_REGISTER_NUMBER;
 154
 155         addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset);
 156
 157         /*
 158          * Note: the caller has already checked that offset is
 159          * suitably aligned and that len is 1, 2 or 4.
 160          */
 161         switch (len) {
 162         case 1:
 163                 out_8(addr, val);
 164                 break;
 165         case 2:
 166                 out_le16(addr, val);
 167                 break;
 168         default:
 169                 out_le32(addr, val);
 170                 break;
 171         }
 172         return PCIBIOS_SUCCESSFUL;
 173 }
 174
 175 static struct pci_ops pa_pxp_ops = {
 176         .read = pa_pxp_read_config,
 177         .write = pa_pxp_write_config,
 178 };
 179
 180 static void __init setup_pa_pxp(struct pci_controller *hose)
 181 {
 182         hose->ops = &pa_pxp_ops;
 183         hose->cfg_data = ioremap(0xe0000000, 0x10000000);
 184 }
 185
 186 static int __init pas_add_bridge(struct device_node *dev)
 187 {
 188         struct pci_controller *hose;
 189
 190         pr_debug("Adding PCI host bridge %s\n", dev->full_name);
 191
 192         hose = pcibios_alloc_controller(dev);
 193         if (!hose)
 194                 return -ENOMEM;
 195
 196         hose->first_busno = 0;
 197         hose->last_busno = 0xff;
 198
 199         setup_pa_pxp(hose);
 200
 201         printk(KERN_INFO "Found PA-PXP PCI host bridge.\n");
 202
 203         /* Interpret the "ranges" property */
 204         pci_process_bridge_OF_ranges(hose, dev, 1);
 205
 206         return 0;
 207 }
 208
 209 void __init pas_pci_init(void)
 210 {
 211         struct device_node *np, *root;
 212
 213         root = of_find_node_by_path("/");
 214         if (!root) {
 215                 printk(KERN_CRIT "pas_pci_init: can't find root "
 216                         "of device tree\n");
 217                 return;
 218         }
 219
 220         for (np = NULL; (np = of_get_next_child(root, np)) != NULL;)
 221                 if (np->name && !strcmp(np->name, "pxp") && !pas_add_bridge(np))
 222                         of_node_get(np);
 223
 224         of_node_put(root);
 225
 226         /* Setup the linkage between OF nodes and PHBs */
 227         pci_devs_phb_init();
 228
 229         /* Use the common resource allocation mechanism */
 230         pci_probe_only = 1;
 231 }
 232
 233 void __iomem *pasemi_pci_getcfgaddr(struct pci_dev *dev, int offset)
 234 {
 235         struct pci_controller *hose;
 236
 237         hose = pci_bus_to_host(dev->bus);
 238
 239         return (void __iomem *)pa_pxp_cfg_addr(hose, dev->bus->number, dev->devfn, offset);
 240 }