[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / powerpc / mm / tlb_low_64e.S
| blob | 2d6d55e3a94f794acdc17cf47633eb7d6688b36f |
1 /*
2 * Low level TLB miss handlers for Book3E
3 *
4 * Copyright (C) 2008-2009
5 * Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
13 #include <asm/processor.h>
14 #include <asm/reg.h>
15 #include <asm/page.h>
16 #include <asm/mmu.h>
17 #include <asm/ppc_asm.h>
18 #include <asm/asm-offsets.h>
19 #include <asm/cputable.h>
20 #include <asm/pgtable.h>
21 #include <asm/exception-64e.h>
22 #include <asm/ppc-opcode.h>
24 #ifdef CONFIG_PPC_64K_PAGES
25 #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE+1)
26 #else
27 #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE)
28 #endif
29 #define VPTE_PUD_SHIFT (VPTE_PMD_SHIFT + PMD_INDEX_SIZE)
30 #define VPTE_PGD_SHIFT (VPTE_PUD_SHIFT + PUD_INDEX_SIZE)
31 #define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE)
34 /**********************************************************************
35 * *
36 * TLB miss handling for Book3E with TLB reservation and HES support *
37 * *
38 **********************************************************************/
41 /* Data TLB miss */
42 START_EXCEPTION(data_tlb_miss)
43 TLB_MISS_PROLOG
45 /* Now we handle the fault proper. We only save DEAR in normal
46 * fault case since that's the only interesting values here.
47 * We could probably also optimize by not saving SRR0/1 in the
48 * linear mapping case but I'll leave that for later
49 */
50 mfspr r14,SPRN_ESR
51 mfspr r16,SPRN_DEAR /* get faulting address */
52 srdi r15,r16,60 /* get region */
53 cmpldi cr0,r15,0xc /* linear mapping ? */
54 TLB_MISS_STATS_SAVE_INFO
55 beq tlb_load_linear /* yes -> go to linear map load */
57 /* The page tables are mapped virtually linear. At this point, though,
58 * we don't know whether we are trying to fault in a first level
59 * virtual address or a virtual page table address. We can get that
60 * from bit 0x1 of the region ID which we have set for a page table
61 */
62 andi. r10,r15,0x1
63 bne- virt_page_table_tlb_miss
65 std r14,EX_TLB_ESR(r12); /* save ESR */
66 std r16,EX_TLB_DEAR(r12); /* save DEAR */
68 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
69 li r11,_PAGE_PRESENT
70 oris r11,r11,_PAGE_ACCESSED@h
72 /* We do the user/kernel test for the PID here along with the RW test
73 */
74 cmpldi cr0,r15,0 /* Check for user region */
76 /* We pre-test some combination of permissions to avoid double
77 * faults:
78 *
79 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
80 * ESR_ST is 0x00800000
81 * _PAGE_BAP_SW is 0x00000010
82 * So the shift is >> 19. This tests for supervisor writeability.
83 * If the page happens to be supervisor writeable and not user
84 * writeable, we will take a new fault later, but that should be
85 * a rare enough case.
86 *
87 * We also move ESR_ST in _PAGE_DIRTY position
88 * _PAGE_DIRTY is 0x00001000 so the shift is >> 11
89 *
90 * MAS1 is preset for all we need except for TID that needs to
91 * be cleared for kernel translations
92 */
93 rlwimi r11,r14,32-19,27,27
94 rlwimi r11,r14,32-16,19,19
95 beq normal_tlb_miss
96 1: mfspr r10,SPRN_MAS1
97 cmpldi cr0,r15,8 /* Check for vmalloc region */
98 rlwinm r10,r10,0,16,1 /* Clear TID */
99 mtspr SPRN_MAS1,r10
100 beq+ normal_tlb_miss
102 /* We got a crappy address, just fault with whatever DEAR and ESR
103 * are here
104 */
105 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
106 TLB_MISS_EPILOG_ERROR
107 b exc_data_storage_book3e
109 /* Instruction TLB miss */
110 START_EXCEPTION(instruction_tlb_miss)
111 TLB_MISS_PROLOG
113 /* If we take a recursive fault, the second level handler may need
114 * to know whether we are handling a data or instruction fault in
115 * order to get to the right store fault handler. We provide that
116 * info by writing a crazy value in ESR in our exception frame
117 */
118 li r14,-1 /* store to exception frame is done later */
120 /* Now we handle the fault proper. We only save DEAR in the non
121 * linear mapping case since we know the linear mapping case will
122 * not re-enter. We could indeed optimize and also not save SRR0/1
123 * in the linear mapping case but I'll leave that for later
124 *
125 * Faulting address is SRR0 which is already in r16
126 */
127 srdi r15,r16,60 /* get region */
128 cmpldi cr0,r15,0xc /* linear mapping ? */
129 TLB_MISS_STATS_SAVE_INFO
130 beq tlb_load_linear /* yes -> go to linear map load */
132 /* We do the user/kernel test for the PID here along with the RW test
133 */
134 li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
135 oris r11,r11,_PAGE_ACCESSED@h
137 cmpldi cr0,r15,0 /* Check for user region */
138 std r14,EX_TLB_ESR(r12) /* write crazy -1 to frame */
139 beq normal_tlb_miss
140 1: mfspr r10,SPRN_MAS1
141 cmpldi cr0,r15,8 /* Check for vmalloc region */
142 rlwinm r10,r10,0,16,1 /* Clear TID */
143 mtspr SPRN_MAS1,r10
144 beq+ normal_tlb_miss
146 /* We got a crappy address, just fault */
147 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
148 TLB_MISS_EPILOG_ERROR
149 b exc_instruction_storage_book3e
151 /*
152 * This is the guts of the first-level TLB miss handler for direct
153 * misses. We are entered with:
154 *
155 * r16 = faulting address
156 * r15 = region ID
157 * r14 = crap (free to use)
158 * r13 = PACA
159 * r12 = TLB exception frame in PACA
160 * r11 = PTE permission mask
161 * r10 = crap (free to use)
162 */
163 normal_tlb_miss:
164 /* So we first construct the page table address. We do that by
165 * shifting the bottom of the address (not the region ID) by
166 * PAGE_SHIFT-3, clearing the bottom 3 bits (get a PTE ptr) and
167 * or'ing the fourth high bit.
168 *
169 * NOTE: For 64K pages, we do things slightly differently in
170 * order to handle the weird page table format used by linux
171 */
172 ori r10,r15,0x1
173 #ifdef CONFIG_PPC_64K_PAGES
174 /* For the top bits, 16 bytes per PTE */
175 rldicl r14,r16,64-(PAGE_SHIFT-4),PAGE_SHIFT-4+4
176 /* Now create the bottom bits as 0 in position 0x8000 and
177 * the rest calculated for 8 bytes per PTE
178 */
179 rldicl r15,r16,64-(PAGE_SHIFT-3),64-15
180 /* Insert the bottom bits in */
181 rlwimi r14,r15,0,16,31
182 #else
183 rldicl r14,r16,64-(PAGE_SHIFT-3),PAGE_SHIFT-3+4
184 #endif
185 sldi r15,r10,60
186 clrrdi r14,r14,3
187 or r10,r15,r14
189 BEGIN_MMU_FTR_SECTION
190 /* Set the TLB reservation and seach for existing entry. Then load
191 * the entry.
192 */
193 PPC_TLBSRX_DOT(0,r16)
194 ld r14,0(r10)
195 beq normal_tlb_miss_done
196 MMU_FTR_SECTION_ELSE
197 ld r14,0(r10)
198 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
200 finish_normal_tlb_miss:
201 /* Check if required permissions are met */
202 andc. r15,r11,r14
203 bne- normal_tlb_miss_access_fault
205 /* Now we build the MAS:
206 *
207 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
208 * MAS 1 : Almost fully setup
209 * - PID already updated by caller if necessary
210 * - TSIZE need change if !base page size, not
211 * yet implemented for now
212 * MAS 2 : Defaults not useful, need to be redone
213 * MAS 3+7 : Needs to be done
214 *
215 * TODO: mix up code below for better scheduling
216 */
217 clrrdi r11,r16,12 /* Clear low crap in EA */
218 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
219 mtspr SPRN_MAS2,r11
221 /* Check page size, if not standard, update MAS1 */
222 rldicl r11,r14,64-8,64-8
223 #ifdef CONFIG_PPC_64K_PAGES
224 cmpldi cr0,r11,BOOK3E_PAGESZ_64K
225 #else
226 cmpldi cr0,r11,BOOK3E_PAGESZ_4K
227 #endif
228 beq- 1f
229 mfspr r11,SPRN_MAS1
230 rlwimi r11,r14,31,21,24
231 rlwinm r11,r11,0,21,19
232 mtspr SPRN_MAS1,r11
233 1:
234 /* Move RPN in position */
235 rldicr r11,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
236 clrldi r15,r11,12 /* Clear crap at the top */
237 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
238 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
240 andi. r11,r14,_PAGE_DIRTY
241 bne 1f
242 li r11,MAS3_SW|MAS3_UW
243 andc r15,r15,r11
244 1:
245 BEGIN_MMU_FTR_SECTION
246 srdi r16,r15,32
247 mtspr SPRN_MAS3,r15
248 mtspr SPRN_MAS7,r16
249 MMU_FTR_SECTION_ELSE
250 mtspr SPRN_MAS7_MAS3,r15
251 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
253 tlbwe
255 normal_tlb_miss_done:
256 /* We don't bother with restoring DEAR or ESR since we know we are
257 * level 0 and just going back to userland. They are only needed
258 * if you are going to take an access fault
259 */
260 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
261 TLB_MISS_EPILOG_SUCCESS
262 rfi
264 normal_tlb_miss_access_fault:
265 /* We need to check if it was an instruction miss */
266 andi. r10,r11,_PAGE_EXEC
267 bne 1f
268 ld r14,EX_TLB_DEAR(r12)
269 ld r15,EX_TLB_ESR(r12)
270 mtspr SPRN_DEAR,r14
271 mtspr SPRN_ESR,r15
272 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
273 TLB_MISS_EPILOG_ERROR
274 b exc_data_storage_book3e
275 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
276 TLB_MISS_EPILOG_ERROR
277 b exc_instruction_storage_book3e
280 virt_page_table_tlb_miss:
281 /* Are we hitting a kernel page table ? */
282 andi. r10,r15,0x8
284 /* The cool thing now is that r10 contains 0 for user and 8 for kernel,
285 * and we happen to have the swapper_pg_dir at offset 8 from the user
286 * pgdir in the PACA :-).
287 */
288 add r11,r10,r13
290 /* If kernel, we need to clear MAS1 TID */
291 beq 1f
292 mfspr r10,SPRN_MAS1
293 rlwinm r10,r10,0,16,1 /* Clear TID */
294 mtspr SPRN_MAS1,r10
295 1:
296 BEGIN_MMU_FTR_SECTION
297 /* Search if we already have a TLB entry for that virtual address, and
298 * if we do, bail out.
299 */
300 PPC_TLBSRX_DOT(0,r16)
301 beq virt_page_table_tlb_miss_done
302 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
304 /* Now, we need to walk the page tables. First check if we are in
305 * range.
306 */
307 rldicl. r10,r16,64-(VPTE_INDEX_SIZE+3),VPTE_INDEX_SIZE+3+4
308 bne- virt_page_table_tlb_miss_fault
310 /* Get the PGD pointer */
311 ld r15,PACAPGD(r11)
312 cmpldi cr0,r15,0
313 beq- virt_page_table_tlb_miss_fault
315 /* Get to PGD entry */
316 rldicl r11,r16,64-VPTE_PGD_SHIFT,64-PGD_INDEX_SIZE-3
317 clrrdi r10,r11,3
318 ldx r15,r10,r15
319 cmpldi cr0,r15,0
320 beq virt_page_table_tlb_miss_fault
322 #ifndef CONFIG_PPC_64K_PAGES
323 /* Get to PUD entry */
324 rldicl r11,r16,64-VPTE_PUD_SHIFT,64-PUD_INDEX_SIZE-3
325 clrrdi r10,r11,3
326 ldx r15,r10,r15
327 cmpldi cr0,r15,0
328 beq virt_page_table_tlb_miss_fault
329 #endif /* CONFIG_PPC_64K_PAGES */
331 /* Get to PMD entry */
332 rldicl r11,r16,64-VPTE_PMD_SHIFT,64-PMD_INDEX_SIZE-3
333 clrrdi r10,r11,3
334 ldx r15,r10,r15
335 cmpldi cr0,r15,0
336 beq virt_page_table_tlb_miss_fault
338 /* Ok, we're all right, we can now create a kernel translation for
339 * a 4K or 64K page from r16 -> r15.
340 */
341 /* Now we build the MAS:
342 *
343 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
344 * MAS 1 : Almost fully setup
345 * - PID already updated by caller if necessary
346 * - TSIZE for now is base page size always
347 * MAS 2 : Use defaults
348 * MAS 3+7 : Needs to be done
349 *
350 * So we only do MAS 2 and 3 for now...
351 */
352 clrldi r11,r15,4 /* remove region ID from RPN */
353 ori r10,r11,1 /* Or-in SR */
355 BEGIN_MMU_FTR_SECTION
356 srdi r16,r10,32
357 mtspr SPRN_MAS3,r10
358 mtspr SPRN_MAS7,r16
359 MMU_FTR_SECTION_ELSE
360 mtspr SPRN_MAS7_MAS3,r10
361 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
363 tlbwe
365 BEGIN_MMU_FTR_SECTION
366 virt_page_table_tlb_miss_done:
368 /* We have overriden MAS2:EPN but currently our primary TLB miss
369 * handler will always restore it so that should not be an issue,
370 * if we ever optimize the primary handler to not write MAS2 on
371 * some cases, we'll have to restore MAS2:EPN here based on the
372 * original fault's DEAR. If we do that we have to modify the
373 * ITLB miss handler to also store SRR0 in the exception frame
374 * as DEAR.
375 *
376 * However, one nasty thing we did is we cleared the reservation
377 * (well, potentially we did). We do a trick here thus if we
378 * are not a level 0 exception (we interrupted the TLB miss) we
379 * offset the return address by -4 in order to replay the tlbsrx
380 * instruction there
381 */
382 subf r10,r13,r12
383 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
384 bne- 1f
385 ld r11,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
386 addi r10,r11,-4
387 std r10,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
388 1:
389 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
390 /* Return to caller, normal case */
391 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK);
392 TLB_MISS_EPILOG_SUCCESS
393 rfi
395 virt_page_table_tlb_miss_fault:
396 /* If we fault here, things are a little bit tricky. We need to call
397 * either data or instruction store fault, and we need to retreive
398 * the original fault address and ESR (for data).
399 *
400 * The thing is, we know that in normal circumstances, this is
401 * always called as a second level tlb miss for SW load or as a first
402 * level TLB miss for HW load, so we should be able to peek at the
403 * relevant informations in the first exception frame in the PACA.
404 *
405 * However, we do need to double check that, because we may just hit
406 * a stray kernel pointer or a userland attack trying to hit those
407 * areas. If that is the case, we do a data fault. (We can't get here
408 * from an instruction tlb miss anyway).
409 *
410 * Note also that when going to a fault, we must unwind the previous
411 * level as well. Since we are doing that, we don't need to clear or
412 * restore the TLB reservation neither.
413 */
414 subf r10,r13,r12
415 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
416 bne- virt_page_table_tlb_miss_whacko_fault
418 /* We dig the original DEAR and ESR from slot 0 */
419 ld r15,EX_TLB_DEAR+PACA_EXTLB(r13)
420 ld r16,EX_TLB_ESR+PACA_EXTLB(r13)
422 /* We check for the "special" ESR value for instruction faults */
423 cmpdi cr0,r16,-1
424 beq 1f
425 mtspr SPRN_DEAR,r15
426 mtspr SPRN_ESR,r16
427 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT);
428 TLB_MISS_EPILOG_ERROR
429 b exc_data_storage_book3e
430 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT);
431 TLB_MISS_EPILOG_ERROR
432 b exc_instruction_storage_book3e
434 virt_page_table_tlb_miss_whacko_fault:
435 /* The linear fault will restart everything so ESR and DEAR will
436 * not have been clobbered, let's just fault with what we have
437 */
438 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_FAULT);
439 TLB_MISS_EPILOG_ERROR
440 b exc_data_storage_book3e
443 /**************************************************************
444 * *
445 * TLB miss handling for Book3E with hw page table support *
446 * *
447 **************************************************************/
450 /* Data TLB miss */
451 START_EXCEPTION(data_tlb_miss_htw)
452 TLB_MISS_PROLOG
454 /* Now we handle the fault proper. We only save DEAR in normal
455 * fault case since that's the only interesting values here.
456 * We could probably also optimize by not saving SRR0/1 in the
457 * linear mapping case but I'll leave that for later
458 */
459 mfspr r14,SPRN_ESR
460 mfspr r16,SPRN_DEAR /* get faulting address */
461 srdi r11,r16,60 /* get region */
462 cmpldi cr0,r11,0xc /* linear mapping ? */
463 TLB_MISS_STATS_SAVE_INFO
464 beq tlb_load_linear /* yes -> go to linear map load */
466 /* We do the user/kernel test for the PID here along with the RW test
467 */
468 cmpldi cr0,r11,0 /* Check for user region */
469 ld r15,PACAPGD(r13) /* Load user pgdir */
470 beq htw_tlb_miss
472 1: mfspr r10,SPRN_MAS1
473 cmpldi cr0,r11,8 /* Check for vmalloc region */
474 rlwinm r10,r10,0,16,1 /* Clear TID */
475 mtspr SPRN_MAS1,r10
476 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
477 beq+ htw_tlb_miss
479 /* We got a crappy address, just fault with whatever DEAR and ESR
480 * are here
481 */
482 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
483 TLB_MISS_EPILOG_ERROR
484 b exc_data_storage_book3e
486 /* Instruction TLB miss */
487 START_EXCEPTION(instruction_tlb_miss_htw)
488 TLB_MISS_PROLOG
490 /* If we take a recursive fault, the second level handler may need
491 * to know whether we are handling a data or instruction fault in
492 * order to get to the right store fault handler. We provide that
493 * info by keeping a crazy value for ESR in r14
494 */
495 li r14,-1 /* store to exception frame is done later */
497 /* Now we handle the fault proper. We only save DEAR in the non
498 * linear mapping case since we know the linear mapping case will
499 * not re-enter. We could indeed optimize and also not save SRR0/1
500 * in the linear mapping case but I'll leave that for later
501 *
502 * Faulting address is SRR0 which is already in r16
503 */
504 srdi r11,r16,60 /* get region */
505 cmpldi cr0,r11,0xc /* linear mapping ? */
506 TLB_MISS_STATS_SAVE_INFO
507 beq tlb_load_linear /* yes -> go to linear map load */
509 /* We do the user/kernel test for the PID here along with the RW test
510 */
511 cmpldi cr0,r11,0 /* Check for user region */
512 ld r15,PACAPGD(r13) /* Load user pgdir */
513 beq htw_tlb_miss
515 1: mfspr r10,SPRN_MAS1
516 cmpldi cr0,r11,8 /* Check for vmalloc region */
517 rlwinm r10,r10,0,16,1 /* Clear TID */
518 mtspr SPRN_MAS1,r10
519 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
520 beq+ htw_tlb_miss
522 /* We got a crappy address, just fault */
523 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
524 TLB_MISS_EPILOG_ERROR
525 b exc_instruction_storage_book3e
528 /*
529 * This is the guts of the second-level TLB miss handler for direct
530 * misses. We are entered with:
531 *
532 * r16 = virtual page table faulting address
533 * r15 = PGD pointer
534 * r14 = ESR
535 * r13 = PACA
536 * r12 = TLB exception frame in PACA
537 * r11 = crap (free to use)
538 * r10 = crap (free to use)
539 *
540 * It can be re-entered by the linear mapping miss handler. However, to
541 * avoid too much complication, it will save/restore things for us
542 */
543 htw_tlb_miss:
544 /* Search if we already have a TLB entry for that virtual address, and
545 * if we do, bail out.
546 *
547 * MAS1:IND should be already set based on MAS4
548 */
549 PPC_TLBSRX_DOT(0,r16)
550 beq htw_tlb_miss_done
552 /* Now, we need to walk the page tables. First check if we are in
553 * range.
554 */
555 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
556 bne- htw_tlb_miss_fault
558 /* Get the PGD pointer */
559 cmpldi cr0,r15,0
560 beq- htw_tlb_miss_fault
562 /* Get to PGD entry */
563 rldicl r11,r16,64-(PGDIR_SHIFT-3),64-PGD_INDEX_SIZE-3
564 clrrdi r10,r11,3
565 ldx r15,r10,r15
566 cmpldi cr0,r15,0
567 beq htw_tlb_miss_fault
569 #ifndef CONFIG_PPC_64K_PAGES
570 /* Get to PUD entry */
571 rldicl r11,r16,64-(PUD_SHIFT-3),64-PUD_INDEX_SIZE-3
572 clrrdi r10,r11,3
573 ldx r15,r10,r15
574 cmpldi cr0,r15,0
575 beq htw_tlb_miss_fault
576 #endif /* CONFIG_PPC_64K_PAGES */
578 /* Get to PMD entry */
579 rldicl r11,r16,64-(PMD_SHIFT-3),64-PMD_INDEX_SIZE-3
580 clrrdi r10,r11,3
581 ldx r15,r10,r15
582 cmpldi cr0,r15,0
583 beq htw_tlb_miss_fault
585 /* Ok, we're all right, we can now create an indirect entry for
586 * a 1M or 256M page.
587 *
588 * The last trick is now that because we use "half" pages for
589 * the HTW (1M IND is 2K and 256M IND is 32K) we need to account
590 * for an added LSB bit to the RPN. For 64K pages, there is no
591 * problem as we already use 32K arrays (half PTE pages), but for
592 * 4K page we need to extract a bit from the virtual address and
593 * insert it into the "PA52" bit of the RPN.
594 */
595 #ifndef CONFIG_PPC_64K_PAGES
596 rlwimi r15,r16,32-9,20,20
597 #endif
598 /* Now we build the MAS:
599 *
600 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
601 * MAS 1 : Almost fully setup
602 * - PID already updated by caller if necessary
603 * - TSIZE for now is base ind page size always
604 * MAS 2 : Use defaults
605 * MAS 3+7 : Needs to be done
606 */
607 #ifdef CONFIG_PPC_64K_PAGES
608 ori r10,r15,(BOOK3E_PAGESZ_64K << MAS3_SPSIZE_SHIFT)
609 #else
610 ori r10,r15,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
611 #endif
613 BEGIN_MMU_FTR_SECTION
614 srdi r16,r10,32
615 mtspr SPRN_MAS3,r10
616 mtspr SPRN_MAS7,r16
617 MMU_FTR_SECTION_ELSE
618 mtspr SPRN_MAS7_MAS3,r10
619 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
621 tlbwe
623 htw_tlb_miss_done:
624 /* We don't bother with restoring DEAR or ESR since we know we are
625 * level 0 and just going back to userland. They are only needed
626 * if you are going to take an access fault
627 */
628 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK)
629 TLB_MISS_EPILOG_SUCCESS
630 rfi
632 htw_tlb_miss_fault:
633 /* We need to check if it was an instruction miss. We know this
634 * though because r14 would contain -1
635 */
636 cmpdi cr0,r14,-1
637 beq 1f
638 mtspr SPRN_DEAR,r16
639 mtspr SPRN_ESR,r14
640 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT)
641 TLB_MISS_EPILOG_ERROR
642 b exc_data_storage_book3e
643 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT)
644 TLB_MISS_EPILOG_ERROR
645 b exc_instruction_storage_book3e
647 /*
648 * This is the guts of "any" level TLB miss handler for kernel linear
649 * mapping misses. We are entered with:
650 *
651 *
652 * r16 = faulting address
653 * r15 = crap (free to use)
654 * r14 = ESR (data) or -1 (instruction)
655 * r13 = PACA
656 * r12 = TLB exception frame in PACA
657 * r11 = crap (free to use)
658 * r10 = crap (free to use)
659 *
660 * In addition we know that we will not re-enter, so in theory, we could
661 * use a simpler epilog not restoring SRR0/1 etc.. but we'll do that later.
662 *
663 * We also need to be careful about MAS registers here & TLB reservation,
664 * as we know we'll have clobbered them if we interrupt the main TLB miss
665 * handlers in which case we probably want to do a full restart at level
666 * 0 rather than saving / restoring the MAS.
667 *
668 * Note: If we care about performance of that core, we can easily shuffle
669 * a few things around
670 */
671 tlb_load_linear:
672 /* For now, we assume the linear mapping is contiguous and stops at
673 * linear_map_top. We also assume the size is a multiple of 1G, thus
674 * we only use 1G pages for now. That might have to be changed in a
675 * final implementation, especially when dealing with hypervisors
676 */
677 ld r11,PACATOC(r13)
678 ld r11,linear_map_top@got(r11)
679 ld r10,0(r11)
680 cmpld cr0,r10,r16
681 bge tlb_load_linear_fault
683 /* MAS1 need whole new setup. */
684 li r15,(BOOK3E_PAGESZ_1GB<<MAS1_TSIZE_SHIFT)
685 oris r15,r15,MAS1_VALID@h /* MAS1 needs V and TSIZE */
686 mtspr SPRN_MAS1,r15
688 /* Already somebody there ? */
689 PPC_TLBSRX_DOT(0,r16)
690 beq tlb_load_linear_done
692 /* Now we build the remaining MAS. MAS0 and 2 should be fine
693 * with their defaults, which leaves us with MAS 3 and 7. The
694 * mapping is linear, so we just take the address, clear the
695 * region bits, and or in the permission bits which are currently
696 * hard wired
697 */
698 clrrdi r10,r16,30 /* 1G page index */
699 clrldi r10,r10,4 /* clear region bits */
700 ori r10,r10,MAS3_SR|MAS3_SW|MAS3_SX
702 BEGIN_MMU_FTR_SECTION
703 srdi r16,r10,32
704 mtspr SPRN_MAS3,r10
705 mtspr SPRN_MAS7,r16
706 MMU_FTR_SECTION_ELSE
707 mtspr SPRN_MAS7_MAS3,r10
708 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
710 tlbwe
712 tlb_load_linear_done:
713 /* We use the "error" epilog for success as we do want to
714 * restore to the initial faulting context, whatever it was.
715 * We do that because we can't resume a fault within a TLB
716 * miss handler, due to MAS and TLB reservation being clobbered.
717 */
718 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_LINEAR)
719 TLB_MISS_EPILOG_ERROR
720 rfi
722 tlb_load_linear_fault:
723 /* We keep the DEAR and ESR around, this shouldn't have happened */
724 cmpdi cr0,r14,-1
725 beq 1f
726 TLB_MISS_EPILOG_ERROR_SPECIAL
727 b exc_data_storage_book3e
728 1: TLB_MISS_EPILOG_ERROR_SPECIAL
729 b exc_instruction_storage_book3e
732 #ifdef CONFIG_BOOK3E_MMU_TLB_STATS
733 .tlb_stat_inc:
734 1: ldarx r8,0,r9
735 addi r8,r8,1
736 stdcx. r8,0,r9
737 bne- 1b
738 blr
739 #endif