release/src-rt-6.x.4708/linux/linux-2.6.36/arch/powerpc/boot/mv64x60.h

   1 /*
   2  * Author: Mark A. Greer <source@mvista.com>
   3  *
   4  * 2007 (c) MontaVista Software, Inc. This file is licensed under
   5  * the terms of the GNU General Public License version 2. This program
   6  * is licensed "as is" without any warranty of any kind, whether express
   7  * or implied.
   8  */
   9
  10 #ifndef _PPC_BOOT_MV64x60_H_
  11 #define _PPC_BOOT_MV64x60_H_
  12
  13 #define MV64x60_CPU_BAR_ENABLE                  0x0278
  14
  15 #define MV64x60_PCI_ACC_CNTL_ENABLE             (1<<0)
  16 #define MV64x60_PCI_ACC_CNTL_REQ64              (1<<1)
  17 #define MV64x60_PCI_ACC_CNTL_SNOOP_NONE         0x00000000
  18 #define MV64x60_PCI_ACC_CNTL_SNOOP_WT           0x00000004
  19 #define MV64x60_PCI_ACC_CNTL_SNOOP_WB           0x00000008
  20 #define MV64x60_PCI_ACC_CNTL_SNOOP_MASK         0x0000000c
  21 #define MV64x60_PCI_ACC_CNTL_ACCPROT            (1<<4)
  22 #define MV64x60_PCI_ACC_CNTL_WRPROT             (1<<5)
  23 #define MV64x60_PCI_ACC_CNTL_SWAP_BYTE          0x00000000
  24 #define MV64x60_PCI_ACC_CNTL_SWAP_NONE          0x00000040
  25 #define MV64x60_PCI_ACC_CNTL_SWAP_BYTE_WORD     0x00000080
  26 #define MV64x60_PCI_ACC_CNTL_SWAP_WORD          0x000000c0
  27 #define MV64x60_PCI_ACC_CNTL_SWAP_MASK          0x000000c0
  28 #define MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES    0x00000000
  29 #define MV64x60_PCI_ACC_CNTL_MBURST_64_BYTES    0x00000100
  30 #define MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES   0x00000200
  31 #define MV64x60_PCI_ACC_CNTL_MBURST_MASK        0x00000300
  32 #define MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES    0x00000000
  33 #define MV64x60_PCI_ACC_CNTL_RDSIZE_64_BYTES    0x00000400
  34 #define MV64x60_PCI_ACC_CNTL_RDSIZE_128_BYTES   0x00000800
  35 #define MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES   0x00000c00
  36 #define MV64x60_PCI_ACC_CNTL_RDSIZE_MASK        0x00000c00
  37
  38 struct mv64x60_cpu2pci_win {
  39         u32 lo;
  40         u32 size;
  41         u32 remap_hi;
  42         u32 remap_lo;
  43 };
  44
  45 extern struct mv64x60_cpu2pci_win mv64x60_cpu2pci_io[2];
  46 extern struct mv64x60_cpu2pci_win mv64x60_cpu2pci_mem[2];
  47
  48 u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn,
  49                 u8 offset);
  50 void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn,
  51                 u8 offset, u32 val);
  52
  53 void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase,
  54                 u8 is_coherent);
  55 void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose,
  56                 u8 bus, u32 mem_size, u32 acc_bits);
  57 void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi,
  58                 u32 pci_base_lo, u32 cpu_base, u32 size,
  59                 struct mv64x60_cpu2pci_win *offset_tbl);
  60 u32 mv64x60_get_mem_size(u8 *bridge_base);
  61 u8 *mv64x60_get_bridge_pbase(void);
  62 u8 *mv64x60_get_bridge_base(void);
  63 u8 mv64x60_is_coherent(void);
  64
  65 int mv64x60_i2c_open(void);
  66 int mv64x60_i2c_read(u32 devaddr, u8 *buf, u32 offset, u32 offset_size,
  67                 u32 count);
  68 void mv64x60_i2c_close(void);
  69
  70 #endif /* _PPC_BOOT_MV64x60_H_ */