| blob | 645a7c964e5fce7221e7ef12f04ec5423188df59 |
1 #ifndef _PPC_BOOT_DCR_H_
2 #define _PPC_BOOT_DCR_H_
4 #define mfdcr(rn) \
5 ({ \
6 unsigned long rval; \
8 rval; \
9 })
10 #define mtdcr(rn, val) \
13 /* 440GP/440GX SDRAM controller DCRs */
14 #define DCRN_SDRAM0_CFGADDR 0x010
15 #define DCRN_SDRAM0_CFGDATA 0x011
17 #define SDRAM0_READ(offset) ({\
18 mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
19 mfdcr(DCRN_SDRAM0_CFGDATA); })
20 #define SDRAM0_WRITE(offset, data) ({\
21 mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
22 mtdcr(DCRN_SDRAM0_CFGDATA, data); })
24 #define SDRAM0_B0CR 0x40
25 #define SDRAM0_B1CR 0x44
26 #define SDRAM0_B2CR 0x48
27 #define SDRAM0_B3CR 0x4c
32 #define SDRAM_CONFIG_BANK_ENABLE 0x00000001
33 #define SDRAM_CONFIG_SIZE_MASK 0x000e0000
34 #define SDRAM_CONFIG_BANK_SIZE(reg) \
35 (0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17))
37 /* 440GP External Bus Controller (EBC) */
38 #define DCRN_EBC0_CFGADDR 0x012
39 #define DCRN_EBC0_CFGDATA 0x013
40 #define EBC_NUM_BANKS 8
41 #define EBC_B0CR 0x00
42 #define EBC_B1CR 0x01
43 #define EBC_B2CR 0x02
44 #define EBC_B3CR 0x03
45 #define EBC_B4CR 0x04
46 #define EBC_B5CR 0x05
47 #define EBC_B6CR 0x06
48 #define EBC_B7CR 0x07
49 #define EBC_BXCR(n) (n)
50 #define EBC_BXCR_BAS 0xfff00000
51 #define EBC_BXCR_BS 0x000e0000
52 #define EBC_BXCR_BANK_SIZE(reg) \
53 (0x100000 << (((reg) & EBC_BXCR_BS) >> 17))
54 #define EBC_BXCR_BU 0x00018000
55 #define EBC_BXCR_BU_OFF 0x00000000
56 #define EBC_BXCR_BU_RO 0x00008000
57 #define EBC_BXCR_BU_WO 0x00010000
58 #define EBC_BXCR_BU_RW 0x00018000
59 #define EBC_BXCR_BW 0x00006000
60 #define EBC_B0AP 0x10
61 #define EBC_B1AP 0x11
62 #define EBC_B2AP 0x12
63 #define EBC_B3AP 0x13
64 #define EBC_B4AP 0x14
65 #define EBC_B5AP 0x15
66 #define EBC_B6AP 0x16
67 #define EBC_B7AP 0x17
68 #define EBC_BXAP(n) (0x10+(n))
69 #define EBC_BEAR 0x20
70 #define EBC_BESR 0x21
71 #define EBC_CFG 0x23
72 #define EBC_CID 0x24
74 /* 440GP Clock, PM, chip control */
75 #define DCRN_CPC0_SR 0x0b0
76 #define DCRN_CPC0_ER 0x0b1
77 #define DCRN_CPC0_FR 0x0b2
78 #define DCRN_CPC0_SYS0 0x0e0
79 #define CPC0_SYS0_TUNE 0xffc00000
80 #define CPC0_SYS0_FBDV_MASK 0x003c0000
81 #define CPC0_SYS0_FWDVA_MASK 0x00038000
82 #define CPC0_SYS0_FWDVB_MASK 0x00007000
83 #define CPC0_SYS0_OPDV_MASK 0x00000c00
84 #define CPC0_SYS0_EPDV_MASK 0x00000300
85 /* Helper macros to compute the actual clock divider values from the
86 * encodings in the CPC0 register */
87 #define CPC0_SYS0_FBDV(reg) \
88 ((((((reg) & CPC0_SYS0_FBDV_MASK) >> 18) - 1) & 0xf) + 1)
89 #define CPC0_SYS0_FWDVA(reg) \
90 (8 - (((reg) & CPC0_SYS0_FWDVA_MASK) >> 15))
91 #define CPC0_SYS0_FWDVB(reg) \
92 (8 - (((reg) & CPC0_SYS0_FWDVB_MASK) >> 12))
93 #define CPC0_SYS0_OPDV(reg) \
94 ((((reg) & CPC0_SYS0_OPDV_MASK) >> 10) + 1)
95 #define CPC0_SYS0_EPDV(reg) \
96 ((((reg) & CPC0_SYS0_EPDV_MASK) >> 8) + 1)
97 #define CPC0_SYS0_EXTSL 0x00000080
98 #define CPC0_SYS0_RW_MASK 0x00000060
99 #define CPC0_SYS0_RL 0x00000010
100 #define CPC0_SYS0_ZMIISL_MASK 0x0000000c
101 #define CPC0_SYS0_BYPASS 0x00000002
102 #define CPC0_SYS0_NTO1 0x00000001
103 #define DCRN_CPC0_SYS1 0x0e1
104 #define DCRN_CPC0_CUST0 0x0e2
105 #define DCRN_CPC0_CUST1 0x0e3
106 #define DCRN_CPC0_STRP0 0x0e4
107 #define DCRN_CPC0_STRP1 0x0e5
108 #define DCRN_CPC0_STRP2 0x0e6
109 #define DCRN_CPC0_STRP3 0x0e7
110 #define DCRN_CPC0_GPIO 0x0e8
111 #define DCRN_CPC0_PLB 0x0e9
112 #define DCRN_CPC0_CR1 0x0ea
113 #define DCRN_CPC0_CR0 0x0eb
114 #define CPC0_CR0_SWE 0x80000000
115 #define CPC0_CR0_CETE 0x40000000
116 #define CPC0_CR0_U1FCS 0x20000000
117 #define CPC0_CR0_U0DTE 0x10000000
118 #define CPC0_CR0_U0DRE 0x08000000
119 #define CPC0_CR0_U0DC 0x04000000
120 #define CPC0_CR0_U1DTE 0x02000000
121 #define CPC0_CR0_U1DRE 0x01000000
122 #define CPC0_CR0_U1DC 0x00800000
123 #define CPC0_CR0_U0EC 0x00400000
124 #define CPC0_CR0_U1EC 0x00200000
125 #define CPC0_CR0_UDIV_MASK 0x001f0000
126 #define CPC0_CR0_UDIV(reg) \
127 ((((reg) & CPC0_CR0_UDIV_MASK) >> 16) + 1)
128 #define DCRN_CPC0_MIRQ0 0x0ec
129 #define DCRN_CPC0_MIRQ1 0x0ed
130 #define DCRN_CPC0_JTAGID 0x0ef
132 #define DCRN_MAL0_CFG 0x180
133 #define MAL_RESET 0x80000000
135 /* 440EP Clock/Power-on Reset regs */
136 #define DCRN_CPR0_ADDR 0xc
137 #define DCRN_CPR0_DATA 0xd
138 #define CPR0_PLLD0 0x60
139 #define CPR0_OPBD0 0xc0
140 #define CPR0_PERD0 0xe0
141 #define CPR0_PRIMBD0 0xa0
142 #define CPR0_SCPID 0x120
143 #define CPR0_PLLC0 0x40
145 /* 405GP Clocking/Power Management/Chip Control regs */
146 #define DCRN_CPC0_PLLMR 0xb0
147 #define DCRN_405_CPC0_CR0 0xb1
148 #define DCRN_405_CPC0_CR1 0xb2
149 #define DCRN_405_CPC0_PSR 0xb4
151 /* 405EP Clocking/Power Management/Chip Control regs */
152 #define DCRN_CPC0_PLLMR0 0xf0
153 #define DCRN_CPC0_PLLMR1 0xf4
154 #define DCRN_CPC0_UCR 0xf5
156 /* 440GX/405EX Clock Control reg */
157 #define DCRN_CPR0_CLKUPD 0x020
158 #define DCRN_CPR0_PLLC 0x040
159 #define DCRN_CPR0_PLLD 0x060
160 #define DCRN_CPR0_PRIMAD 0x080
161 #define DCRN_CPR0_PRIMBD 0x0a0
162 #define DCRN_CPR0_OPBD 0x0c0
163 #define DCRN_CPR0_PERD 0x0e0
164 #define DCRN_CPR0_MALD 0x100
166 #define DCRN_SDR0_CONFIG_ADDR 0xe
167 #define DCRN_SDR0_CONFIG_DATA 0xf
169 /* SDR read/write helper macros */
170 #define SDR0_READ(offset) ({\
171 mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
172 mfdcr(DCRN_SDR0_CONFIG_DATA); })
173 #define SDR0_WRITE(offset, data) ({\
174 mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
175 mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
177 #define DCRN_SDR0_UART0 0x0120
178 #define DCRN_SDR0_UART1 0x0121
179 #define DCRN_SDR0_UART2 0x0122
180 #define DCRN_SDR0_UART3 0x0123
183 /* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */
185 #define DCRN_CPR0_CFGADDR 0xc
186 #define DCRN_CPR0_CFGDATA 0xd
188 #define CPR0_READ(offset) ({\
189 mtdcr(DCRN_CPR0_CFGADDR, offset); \
190 mfdcr(DCRN_CPR0_CFGDATA); })
191 #define CPR0_WRITE(offset, data) ({\
192 mtdcr(DCRN_CPR0_CFGADDR, offset); \
193 mtdcr(DCRN_CPR0_CFGDATA, data); })