release/src-rt-6.x.4708/linux/linux-2.6.36/arch/parisc/mm/fault.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  *
   7  * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle
   8  * Copyright 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
   9  * Copyright 1999 Hewlett Packard Co.
  10  *
  11  */
  12
  13 #include <linux/mm.h>
  14 #include <linux/ptrace.h>
  15 #include <linux/sched.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/module.h>
  18
  19 #include <asm/uaccess.h>
  20 #include <asm/traps.h>
  21
  22 #define PRINT_USER_FAULTS /* (turn this on if you want user faults to be */
  23                          /*  dumped to the console via printk)          */
  24
  25
  26 /* Various important other fields */
  27 #define bit22set(x)             (x & 0x00000200)
  28 #define bits23_25set(x)         (x & 0x000001c0)
  29 #define isGraphicsFlushRead(x)  ((x & 0xfc003fdf) == 0x04001a80)
  30                                 /* extended opcode is 0x6a */
  31
  32 #define BITSSET         0x1c0   /* for identifying LDCW */
  33
  34
  35 DEFINE_PER_CPU(struct exception_data, exception_data);
  36
  37 /*
  38  * parisc_acctyp(unsigned int inst) --
  39  *    Given a PA-RISC memory access instruction, determine if the
  40  *    the instruction would perform a memory read or memory write
  41  *    operation.
  42  *
  43  *    This function assumes that the given instruction is a memory access
  44  *    instruction (i.e. you should really only call it if you know that
  45  *    the instruction has generated some sort of a memory access fault).
  46  *
  47  * Returns:
  48  *   VM_READ  if read operation
  49  *   VM_WRITE if write operation
  50  *   VM_EXEC  if execute operation
  51  */
  52 static unsigned long
  53 parisc_acctyp(unsigned long code, unsigned int inst)
  54 {
  55         if (code == 6 || code == 16)
  56             return VM_EXEC;
  57
  58         switch (inst & 0xf0000000) {
  59         case 0x40000000: /* load */
  60         case 0x50000000: /* new load */
  61                 return VM_READ;
  62
  63         case 0x60000000: /* store */
  64         case 0x70000000: /* new store */
  65                 return VM_WRITE;
  66
  67         case 0x20000000: /* coproc */
  68         case 0x30000000: /* coproc2 */
  69                 if (bit22set(inst))
  70                         return VM_WRITE;
  71
  72         case 0x0: /* indexed/memory management */
  73                 if (bit22set(inst)) {
  74                         /*
  75                          * Check for the 'Graphics Flush Read' instruction.
  76                          * It resembles an FDC instruction, except for bits
  77                          * 20 and 21. Any combination other than zero will
  78                          * utilize the block mover functionality on some
  79                          * older PA-RISC platforms.  The case where a block
  80                          * move is performed from VM to graphics IO space
  81                          * should be treated as a READ.
  82                          *
  83                          * The significance of bits 20,21 in the FDC
  84                          * instruction is:
  85                          *
  86                          *   00  Flush data cache (normal instruction behavior)
  87                          *   01  Graphics flush write  (IO space -> VM)
  88                          *   10  Graphics flush read   (VM -> IO space)
  89                          *   11  Graphics flush read/write (VM <-> IO space)
  90                          */
  91                         if (isGraphicsFlushRead(inst))
  92                                 return VM_READ;
  93                         return VM_WRITE;
  94                 } else {
  95                         /*
  96                          * Check for LDCWX and LDCWS (semaphore instructions).
  97                          * If bits 23 through 25 are all 1's it is one of
  98                          * the above two instructions and is a write.
  99                          *
 100                          * Note: With the limited bits we are looking at,
 101                          * this will also catch PROBEW and PROBEWI. However,
 102                          * these should never get in here because they don't
 103                          * generate exceptions of the type:
 104                          *   Data TLB miss fault/data page fault
 105                          *   Data memory protection trap
 106                          */
 107                         if (bits23_25set(inst) == BITSSET)
 108                                 return VM_WRITE;
 109                 }
 110                 return VM_READ; /* Default */
 111         }
 112         return VM_READ; /* Default */
 113 }
 114
 115 #undef bit22set
 116 #undef bits23_25set
 117 #undef isGraphicsFlushRead
 118 #undef BITSSET
 119
 120
 121
 122 int fixup_exception(struct pt_regs *regs)
 123 {
 124         const struct exception_table_entry *fix;
 125
 126         fix = search_exception_tables(regs->iaoq[0]);
 127         if (fix) {
 128                 struct exception_data *d;
 129                 d = &__get_cpu_var(exception_data);
 130                 d->fault_ip = regs->iaoq[0];
 131                 d->fault_space = regs->isr;
 132                 d->fault_addr = regs->ior;
 133
 134                 regs->iaoq[0] = ((fix->fixup) & ~3);
 135                 /*
 136                  * NOTE: In some cases the faulting instruction
 137                  * may be in the delay slot of a branch. We
 138                  * don't want to take the branch, so we don't
 139                  * increment iaoq[1], instead we set it to be
 140                  * iaoq[0]+4, and clear the B bit in the PSW
 141                  */
 142                 regs->iaoq[1] = regs->iaoq[0] + 4;
 143                 regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */
 144
 145                 return 1;
 146         }
 147
 148         return 0;
 149 }
 150
 151 void do_page_fault(struct pt_regs *regs, unsigned long code,
 152                               unsigned long address)
 153 {
 154         struct vm_area_struct *vma, *prev_vma;
 155         struct task_struct *tsk = current;
 156         struct mm_struct *mm = tsk->mm;
 157         unsigned long acc_type;
 158         int fault;
 159
 160         if (in_atomic() || !mm)
 161                 goto no_context;
 162
 163         down_read(&mm->mmap_sem);
 164         vma = find_vma_prev(mm, address, &prev_vma);
 165         if (!vma || address < vma->vm_start)
 166                 goto check_expansion;
 167 /*
 168  * Ok, we have a good vm_area for this memory access. We still need to
 169  * check the access permissions.
 170  */
 171
 172 good_area:
 173
 174         acc_type = parisc_acctyp(code,regs->iir);
 175
 176         if ((vma->vm_flags & acc_type) != acc_type)
 177                 goto bad_area;
 178
 179         /*
 180          * If for any reason at all we couldn't handle the fault, make
 181          * sure we exit gracefully rather than endlessly redo the
 182          * fault.
 183          */
 184
 185         fault = handle_mm_fault(mm, vma, address, (acc_type & VM_WRITE) ? FAULT_FLAG_WRITE : 0);
 186         if (unlikely(fault & VM_FAULT_ERROR)) {
 187                 /*
 188                  * We hit a shared mapping outside of the file, or some
 189                  * other thing happened to us that made us unable to
 190                  * handle the page fault gracefully.
 191                  */
 192                 if (fault & VM_FAULT_OOM)
 193                         goto out_of_memory;
 194                 else if (fault & VM_FAULT_SIGBUS)
 195                         goto bad_area;
 196                 BUG();
 197         }
 198         if (fault & VM_FAULT_MAJOR)
 199                 current->maj_flt++;
 200         else
 201                 current->min_flt++;
 202         up_read(&mm->mmap_sem);
 203         return;
 204
 205 check_expansion:
 206         vma = prev_vma;
 207         if (vma && (expand_stack(vma, address) == 0))
 208                 goto good_area;
 209
 210 /*
 211  * Something tried to access memory that isn't in our memory map..
 212  */
 213 bad_area:
 214         up_read(&mm->mmap_sem);
 215
 216         if (user_mode(regs)) {
 217                 struct siginfo si;
 218
 219 #ifdef PRINT_USER_FAULTS
 220                 printk(KERN_DEBUG "\n");
 221                 printk(KERN_DEBUG "do_page_fault() pid=%d command='%s' type=%lu address=0x%08lx\n",
 222                     task_pid_nr(tsk), tsk->comm, code, address);
 223                 if (vma) {
 224                         printk(KERN_DEBUG "vm_start = 0x%08lx, vm_end = 0x%08lx\n",
 225                                         vma->vm_start, vma->vm_end);
 226                 }
 227                 show_regs(regs);
 228 #endif
 229                 si.si_signo = SIGSEGV;
 230                 si.si_errno = 0;
 231                 si.si_code = SEGV_MAPERR;
 232                 si.si_addr = (void __user *) address;
 233                 force_sig_info(SIGSEGV, &si, current);
 234                 return;
 235         }
 236
 237 no_context:
 238
 239         if (!user_mode(regs) && fixup_exception(regs)) {
 240                 return;
 241         }
 242
 243         parisc_terminate("Bad Address (null pointer deref?)", regs, code, address);
 244
 245   out_of_memory:
 246         up_read(&mm->mmap_sem);
 247         if (!user_mode(regs))
 248                 goto no_context;
 249         pagefault_out_of_memory();
 250 }