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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / mn10300 / mm / misalignment.c
blob34291f957a757ce03abde3a01b82ce8429f26620
1 /* MN10300 Misalignment fixup handler
2 *
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
10 */
11 #include <linux/module.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/errno.h>
16 #include <linux/ptrace.h>
17 #include <linux/timer.h>
18 #include <linux/mm.h>
19 #include <linux/smp.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/pci.h>
25 #include <asm/processor.h>
26 #include <asm/system.h>
27 #include <asm/uaccess.h>
28 #include <asm/io.h>
29 #include <asm/atomic.h>
30 #include <asm/smp.h>
31 #include <asm/pgalloc.h>
32 #include <asm/cpu-regs.h>
33 #include <asm/busctl-regs.h>
34 #include <asm/fpu.h>
35 #include <asm/gdb-stub.h>
36 #include <asm/asm-offsets.h>
37
38 #define kdebug(FMT, ...) do {} while (0)
39
40 static int misalignment_addr(unsigned long *registers, unsigned long sp,
41 unsigned params, unsigned opcode,
42 unsigned long disp,
43 void **_address, unsigned long **_postinc,
44 unsigned long *_inc);
45
46 static int misalignment_reg(unsigned long *registers, unsigned params,
47 unsigned opcode, unsigned long disp,
48 unsigned long **_register);
49
50 static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode);
51
52 static const unsigned Dreg_index[] = {
53 REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
54 };
55
56 static const unsigned Areg_index[] = {
57 REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2
58 };
59
60 static const unsigned Rreg_index[] = {
61 REG_E0 >> 2, REG_E1 >> 2, REG_E2 >> 2, REG_E3 >> 2,
62 REG_E4 >> 2, REG_E5 >> 2, REG_E6 >> 2, REG_E7 >> 2,
63 REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2,
64 REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
65 };
66
67 enum format_id {
68 FMT_S0,
69 FMT_S1,
70 FMT_S2,
71 FMT_S4,
72 FMT_D0,
73 FMT_D1,
74 FMT_D2,
75 FMT_D4,
76 FMT_D6,
77 FMT_D7,
78 FMT_D8,
79 FMT_D9,
80 FMT_D10,
81 };
82
83 static const struct {
84 u_int8_t opsz, dispsz;
85 } format_tbl[16] = {
86 [FMT_S0] = { 8, 0 },
87 [FMT_S1] = { 8, 8 },
88 [FMT_S2] = { 8, 16 },
89 [FMT_S4] = { 8, 32 },
90 [FMT_D0] = { 16, 0 },
91 [FMT_D1] = { 16, 8 },
92 [FMT_D2] = { 16, 16 },
93 [FMT_D4] = { 16, 32 },
94 [FMT_D6] = { 24, 0 },
95 [FMT_D7] = { 24, 8 },
96 [FMT_D8] = { 24, 24 },
97 [FMT_D9] = { 24, 32 },
98 [FMT_D10] = { 32, 0 },
99 };
100
101 enum value_id {
102 DM0, /* data reg in opcode in bits 0-1 */
103 DM1, /* data reg in opcode in bits 2-3 */
104 DM2, /* data reg in opcode in bits 4-5 */
105 AM0, /* addr reg in opcode in bits 0-1 */
106 AM1, /* addr reg in opcode in bits 2-3 */
107 AM2, /* addr reg in opcode in bits 4-5 */
108 RM0, /* reg in opcode in bits 0-3 */
109 RM1, /* reg in opcode in bits 2-5 */
110 RM2, /* reg in opcode in bits 4-7 */
111 RM4, /* reg in opcode in bits 8-11 */
112 RM6, /* reg in opcode in bits 12-15 */
113
114 RD0, /* reg in displacement in bits 0-3 */
115 RD2, /* reg in displacement in bits 4-7 */
116
117 SP, /* stack pointer */
118
119 SD8, /* 8-bit signed displacement */
120 SD16, /* 16-bit signed displacement */
121 SD24, /* 24-bit signed displacement */
122 SIMM4_2, /* 4-bit signed displacement in opcode bits 4-7 */
123 SIMM8, /* 8-bit signed immediate */
124 IMM8, /* 8-bit unsigned immediate */
125 IMM16, /* 16-bit unsigned immediate */
126 IMM24, /* 24-bit unsigned immediate */
127 IMM32, /* 32-bit unsigned immediate */
128 IMM32_HIGH8, /* 32-bit unsigned immediate, LSB in opcode */
129
130 IMM32_MEM, /* 32-bit unsigned displacement */
131 IMM32_HIGH8_MEM, /* 32-bit unsigned displacement, LSB in opcode */
132
133 DN0 = DM0,
134 DN1 = DM1,
135 DN2 = DM2,
136 AN0 = AM0,
137 AN1 = AM1,
138 AN2 = AM2,
139 RN0 = RM0,
140 RN1 = RM1,
141 RN2 = RM2,
142 RN4 = RM4,
143 RN6 = RM6,
144 DI = DM1,
145 RI = RM2,
146
147 };
148
149 struct mn10300_opcode {
150 const char name[8];
151 u_int32_t opcode;
152 u_int32_t opmask;
153 unsigned exclusion;
154
155 enum format_id format;
156
157 unsigned cpu_mask;
158 #define AM33 330
159
160 unsigned params[2];
161 #define MEM(ADDR) (0x80000000 | (ADDR))
162 #define MEM2(ADDR1, ADDR2) (0x80000000 | (ADDR1) << 8 | (ADDR2))
163 #define MEMINC(ADDR) (0x81000000 | (ADDR))
164 #define MEMINC2(ADDR, INC) (0x81000000 | (ADDR) << 8 | (INC))
165 };
166
167 /* LIBOPCODES EXCERPT
168 Assemble Matsushita MN10300 instructions.
169 Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
170
171 This program is free software; you can redistribute it and/or modify
172 it under the terms of the GNU General Public Licence as published by
173 the Free Software Foundation; either version 2 of the Licence, or
174 (at your option) any later version.
175
176 This program is distributed in the hope that it will be useful,
177 but WITHOUT ANY WARRANTY; without even the implied warranty of
178 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
179 GNU General Public Licence for more details.
180
181 You should have received a copy of the GNU General Public Licence
182 along with this program; if not, write to the Free Software
183 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
184 */
185 static const struct mn10300_opcode mn10300_opcodes[] = {
186 { "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}},
187 { "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}},
188 { "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}},
189 { "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}},
190 { "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}},
191 { "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}},
192 { "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}},
193 { "mov", 0xf010, 0xfff0, 0, FMT_D0, 0, {AM1, MEM(AN0)}},
194 { "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
195 { "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
196 { "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}},
197 { "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}},
198 { "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
199 { "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
200 { "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
201 { "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}},
202 { "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
203 { "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
204 { "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
205 { "mov", 0xf97a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
206 { "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
207 { "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
208 { "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
209 { "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}},
210 { "mov", 0xfa900000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}},
211 { "mov", 0xfa910000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
212 { "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), AN0}},
213 { "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
214 { "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
215 { "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
216 { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
217 { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
218 { "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
219 { "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
220 { "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
221 { "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
222 { "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
223 { "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
224 { "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}},
225 { "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}},
226 { "mov", 0xfc800000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}},
227 { "mov", 0xfc810000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
228 { "mov", 0xfc900000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}},
229 { "mov", 0xfc910000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
230 { "mov", 0xfca00000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), AN0}},
231 { "mov", 0xfca40000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
232 { "mov", 0xfcb00000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), AN0}},
233 { "mov", 0xfcb40000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
234 { "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
235 { "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
236 { "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
237 { "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
238 { "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
239 { "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
240 { "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
241 { "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
242 { "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
243 { "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
244 { "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
245 { "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
246 { "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
247 { "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
248 { "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}},
249 { "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
250
251 { "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}},
252 { "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
253 { "movhu", 0xf480, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
254 { "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
255 { "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
256 { "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
257 { "movhu", 0xf89300, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}},
258 { "movhu", 0xf8bc00, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}},
259 { "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
260 { "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
261 { "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
262 { "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
263 { "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
264 { "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
265 { "movhu", 0xfa930000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
266 { "movhu", 0xfabc0000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
267 { "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
268 { "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
269 { "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
270 { "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
271 { "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
272 { "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
273 { "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
274 { "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
275 { "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
276 { "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
277 { "movhu", 0xfc830000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
278 { "movhu", 0xfc930000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
279 { "movhu", 0xfcac0000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
280 { "movhu", 0xfcbc0000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
281 { "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
282 { "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
283 { "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
284 { "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
285 { "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
286 { "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
287 { "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
288 { "movhu", 0xfe4e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
289 { "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
290 { "movhu", 0xfe5e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
291 { "movhu", 0xfeca0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}},
292 { "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
293 { "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
294 { "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
295
296 { "mov_llt", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
297 { "mov_lgt", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
298 { "mov_lge", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
299 { "mov_lle", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
300 { "mov_lcs", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
301 { "mov_lhi", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
302 { "mov_lcc", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
303 { "mov_lls", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
304 { "mov_leq", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
305 { "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
306 { "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
307
308 { "", 0, 0, 0, 0, 0, {0}},
309 };
310
311 /*
312 * fix up misalignment problems where possible
313 */
314 asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code)
315 {
316 const struct exception_table_entry *fixup;
317 const struct mn10300_opcode *pop;
318 unsigned long *registers = (unsigned long *) regs;
319 unsigned long data, *store, *postinc, disp, inc, sp;
320 mm_segment_t seg;
321 siginfo_t info;
322 uint32_t opcode, noc, xo, xm;
323 uint8_t *pc, byte, datasz;
324 void *address;
325 unsigned tmp, npop, dispsz, loop;
326
327 /* we don't fix up userspace misalignment faults */
328 if (user_mode(regs))
329 goto bus_error;
330
331 sp = (unsigned long) regs + sizeof(*regs);
332
333 kdebug("==>misalignment({pc=%lx,sp=%lx})", regs->pc, sp);
334
335 if (regs->epsw & EPSW_IE)
336 asm volatile("or %0,epsw" : : "i"(EPSW_IE));
337
338 seg = get_fs();
339 set_fs(KERNEL_DS);
340
341 fixup = search_exception_tables(regs->pc);
342
343 /* first thing to do is to match the opcode */
344 pc = (u_int8_t *) regs->pc;
345
346 if (__get_user(byte, pc) != 0)
347 goto fetch_error;
348 opcode = byte;
349 noc = 8;
350
351 for (pop = mn10300_opcodes; pop->name[0]; pop++) {
352 npop = ilog2(pop->opcode | pop->opmask);
353 if (npop <= 0 || npop > 31)
354 continue;
355 npop = (npop + 8) & ~7;
356
357 got_more_bits:
358 if (npop == noc) {
359 if ((opcode & pop->opmask) == pop->opcode)
360 goto found_opcode;
361 } else if (npop > noc) {
362 xo = pop->opcode >> (npop - noc);
363 xm = pop->opmask >> (npop - noc);
364
365 if ((opcode & xm) != xo)
366 continue;
367
368 /* we've got a partial match (an exact match on the
369 * first N bytes), so we need to get some more data */
370 pc++;
371 if (__get_user(byte, pc) != 0)
372 goto fetch_error;
373 opcode = opcode << 8 | byte;
374 noc += 8;
375 goto got_more_bits;
376 } else {
377 /* there's already been a partial match as long as the
378 * complete match we're now considering, so this one
379 * should't match */
380 continue;
381 }
382 }
383
384 /* didn't manage to find a fixup */
385 printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n",
386 regs->pc, opcode);
387
388 failed:
389 set_fs(seg);
390 if (die_if_no_fixup("misalignment error", regs, code))
391 return;
392
393 bus_error:
394 info.si_signo = SIGBUS;
395 info.si_errno = 0;
396 info.si_code = BUS_ADRALN;
397 info.si_addr = (void *) regs->pc;
398 force_sig_info(SIGBUS, &info, current);
399 return;
400
401 /* error reading opcodes */
402 fetch_error:
403 printk(KERN_CRIT
404 "MISALIGN: %p: fault whilst reading instruction data\n",
405 pc);
406 goto failed;
407
408 bad_addr_mode:
409 printk(KERN_CRIT
410 "MISALIGN: %lx: unsupported addressing mode %x\n",
411 regs->pc, opcode);
412 goto failed;
413
414 bad_reg_mode:
415 printk(KERN_CRIT
416 "MISALIGN: %lx: unsupported register mode %x\n",
417 regs->pc, opcode);
418 goto failed;
419
420 unsupported_instruction:
421 printk(KERN_CRIT
422 "MISALIGN: %lx: unsupported instruction %x (%s)\n",
423 regs->pc, opcode, pop->name);
424 goto failed;
425
426 transfer_failed:
427 set_fs(seg);
428 if (fixup) {
429 regs->pc = fixup->fixup;
430 return;
431 }
432 if (die_if_no_fixup("misalignment fixup", regs, code))
433 return;
434
435 info.si_signo = SIGSEGV;
436 info.si_errno = 0;
437 info.si_code = 0;
438 info.si_addr = (void *) regs->pc;
439 force_sig_info(SIGSEGV, &info, current);
440 return;
441
442 /* we matched the opcode */
443 found_opcode:
444 kdebug("%lx: %x==%x { %x, %x }",
445 regs->pc, opcode, pop->opcode, pop->params[0], pop->params[1]);
446
447 tmp = format_tbl[pop->format].opsz;
448 if (tmp > noc)
449 BUG(); /* match was less complete than it ought to have been */
450
451 if (tmp < noc) {
452 tmp = noc - tmp;
453 opcode >>= tmp;
454 pc -= tmp >> 3;
455 }
456
457 /* grab the extra displacement (note it's LSB first) */
458 disp = 0;
459 dispsz = format_tbl[pop->format].dispsz;
460 for (loop = 0; loop < dispsz; loop += 8) {
461 pc++;
462 if (__get_user(byte, pc) != 0)
463 goto fetch_error;
464 disp |= byte << loop;
465 kdebug("{%p} disp[%02x]=%02x", pc, loop, byte);
466 }
467
468 kdebug("disp=%lx", disp);
469
470 set_fs(KERNEL_XDS);
471 if (fixup)
472 set_fs(seg);
473
474 tmp = (pop->params[0] ^ pop->params[1]) & 0x80000000;
475 if (!tmp) {
476 printk(KERN_CRIT
477 "MISALIGN: %lx: insn not move to/from memory %x\n",
478 regs->pc, opcode);
479 goto failed;
480 }
481
482 /* determine the data transfer size of the move */
483 if (pop->name[3] == 0 || /* "mov" */
484 pop->name[4] == 'l') /* mov_lcc */
485 inc = datasz = 4;
486 else if (pop->name[3] == 'h') /* movhu */
487 inc = datasz = 2;
488 else
489 goto unsupported_instruction;
490
491 if (pop->params[0] & 0x80000000) {
492 /* move memory to register */
493 if (!misalignment_addr(registers, sp,
494 pop->params[0], opcode, disp,
495 &address, &postinc, &inc))
496 goto bad_addr_mode;
497
498 if (!misalignment_reg(registers, pop->params[1], opcode, disp,
499 &store))
500 goto bad_reg_mode;
501
502 kdebug("mov%u (%p),DARn", datasz, address);
503 if (copy_from_user(&data, (void *) address, datasz) != 0)
504 goto transfer_failed;
505 if (pop->params[0] & 0x1000000) {
506 kdebug("inc=%lx", inc);
507 *postinc += inc;
508 }
509
510 *store = data;
511 kdebug("loaded %lx", data);
512 } else {
513 /* move register to memory */
514 if (!misalignment_reg(registers, pop->params[0], opcode, disp,
515 &store))
516 goto bad_reg_mode;
517
518 if (!misalignment_addr(registers, sp,
519 pop->params[1], opcode, disp,
520 &address, &postinc, &inc))
521 goto bad_addr_mode;
522
523 data = *store;
524
525 kdebug("mov%u %lx,(%p)", datasz, data, address);
526 if (copy_to_user((void *) address, &data, datasz) != 0)
527 goto transfer_failed;
528 if (pop->params[1] & 0x1000000)
529 *postinc += inc;
530 }
531
532 tmp = format_tbl[pop->format].opsz + format_tbl[pop->format].dispsz;
533 regs->pc += tmp >> 3;
534
535 /* handle MOV_Lcc, which are currently the only FMT_D10 insns that
536 * access memory */
537 if (pop->format == FMT_D10)
538 misalignment_MOV_Lcc(regs, opcode);
539
540 set_fs(seg);
541 }
542
543 /*
544 * determine the address that was being accessed
545 */
546 static int misalignment_addr(unsigned long *registers, unsigned long sp,
547 unsigned params, unsigned opcode,
548 unsigned long disp,
549 void **_address, unsigned long **_postinc,
550 unsigned long *_inc)
551 {
552 unsigned long *postinc = NULL, address = 0, tmp;
553
554 if (!(params & 0x1000000)) {
555 kdebug("noinc");
556 *_inc = 0;
557 _inc = NULL;
558 }
559
560 params &= 0x00ffffff;
561
562 do {
563 switch (params & 0xff) {
564 case DM0:
565 postinc = &registers[Dreg_index[opcode & 0x03]];
566 address += *postinc;
567 break;
568 case DM1:
569 postinc = &registers[Dreg_index[opcode >> 2 & 0x03]];
570 address += *postinc;
571 break;
572 case DM2:
573 postinc = &registers[Dreg_index[opcode >> 4 & 0x03]];
574 address += *postinc;
575 break;
576 case AM0:
577 postinc = &registers[Areg_index[opcode & 0x03]];
578 address += *postinc;
579 break;
580 case AM1:
581 postinc = &registers[Areg_index[opcode >> 2 & 0x03]];
582 address += *postinc;
583 break;
584 case AM2:
585 postinc = &registers[Areg_index[opcode >> 4 & 0x03]];
586 address += *postinc;
587 break;
588 case RM0:
589 postinc = &registers[Rreg_index[opcode & 0x0f]];
590 address += *postinc;
591 break;
592 case RM1:
593 postinc = &registers[Rreg_index[opcode >> 2 & 0x0f]];
594 address += *postinc;
595 break;
596 case RM2:
597 postinc = &registers[Rreg_index[opcode >> 4 & 0x0f]];
598 address += *postinc;
599 break;
600 case RM4:
601 postinc = &registers[Rreg_index[opcode >> 8 & 0x0f]];
602 address += *postinc;
603 break;
604 case RM6:
605 postinc = &registers[Rreg_index[opcode >> 12 & 0x0f]];
606 address += *postinc;
607 break;
608 case RD0:
609 postinc = &registers[Rreg_index[disp & 0x0f]];
610 address += *postinc;
611 break;
612 case RD2:
613 postinc = &registers[Rreg_index[disp >> 4 & 0x0f]];
614 address += *postinc;
615 break;
616 case SP:
617 address += sp;
618 break;
619
620 /* displacements are either to be added to the address
621 * before use, or, in the case of post-inc addressing,
622 * to be added into the base register after use */
623 case SD8:
624 case SIMM8:
625 disp = (long) (int8_t) (disp & 0xff);
626 goto displace_or_inc;
627 case SD16:
628 disp = (long) (int16_t) (disp & 0xffff);
629 goto displace_or_inc;
630 case SD24:
631 tmp = disp << 8;
632 asm("asr 8,%0" : "=r"(tmp) : "0"(tmp) : "cc");
633 disp = (long) tmp;
634 goto displace_or_inc;
635 case SIMM4_2:
636 tmp = opcode >> 4 & 0x0f;
637 tmp <<= 28;
638 asm("asr 28,%0" : "=r"(tmp) : "0"(tmp) : "cc");
639 disp = (long) tmp;
640 goto displace_or_inc;
641 case IMM8:
642 disp &= 0x000000ff;
643 goto displace_or_inc;
644 case IMM16:
645 disp &= 0x0000ffff;
646 goto displace_or_inc;
647 case IMM24:
648 disp &= 0x00ffffff;
649 goto displace_or_inc;
650 case IMM32:
651 case IMM32_MEM:
652 case IMM32_HIGH8:
653 case IMM32_HIGH8_MEM:
654 displace_or_inc:
655 kdebug("%s %lx", _inc ? "incr" : "disp", disp);
656 if (!_inc)
657 address += disp;
658 else
659 *_inc = disp;
660 break;
661 default:
662 BUG();
663 return 0;
664 }
665 } while ((params >>= 8));
666
667 *_address = (void *) address;
668 *_postinc = postinc;
669 return 1;
670 }
671
672 /*
673 * determine the register that is acting as source/dest
674 */
675 static int misalignment_reg(unsigned long *registers, unsigned params,
676 unsigned opcode, unsigned long disp,
677 unsigned long **_register)
678 {
679 params &= 0x7fffffff;
680
681 if (params & 0xffffff00)
682 return 0;
683
684 switch (params & 0xff) {
685 case DM0:
686 *_register = &registers[Dreg_index[opcode & 0x03]];
687 break;
688 case DM1:
689 *_register = &registers[Dreg_index[opcode >> 2 & 0x03]];
690 break;
691 case DM2:
692 *_register = &registers[Dreg_index[opcode >> 4 & 0x03]];
693 break;
694 case AM0:
695 *_register = &registers[Areg_index[opcode & 0x03]];
696 break;
697 case AM1:
698 *_register = &registers[Areg_index[opcode >> 2 & 0x03]];
699 break;
700 case AM2:
701 *_register = &registers[Areg_index[opcode >> 4 & 0x03]];
702 break;
703 case RM0:
704 *_register = &registers[Rreg_index[opcode & 0x0f]];
705 break;
706 case RM1:
707 *_register = &registers[Rreg_index[opcode >> 2 & 0x0f]];
708 break;
709 case RM2:
710 *_register = &registers[Rreg_index[opcode >> 4 & 0x0f]];
711 break;
712 case RM4:
713 *_register = &registers[Rreg_index[opcode >> 8 & 0x0f]];
714 break;
715 case RM6:
716 *_register = &registers[Rreg_index[opcode >> 12 & 0x0f]];
717 break;
718 case RD0:
719 *_register = &registers[Rreg_index[disp & 0x0f]];
720 break;
721 case RD2:
722 *_register = &registers[Rreg_index[disp >> 4 & 0x0f]];
723 break;
724 case SP:
725 *_register = &registers[REG_SP >> 2];
726 break;
727
728 default:
729 BUG();
730 return 0;
731 }
732
733 return 1;
734 }
735
736 /*
737 * handle the conditional loop part of the move-and-loop instructions
738 */
739 static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode)
740 {
741 unsigned long epsw = regs->epsw;
742 unsigned long NxorV;
743
744 kdebug("MOV_Lcc %x [flags=%lx]", opcode, epsw & 0xf);
745
746 /* calculate N^V and shift onto the same bit position as Z */
747 NxorV = ((epsw >> 3) ^ epsw >> 1) & 1;
748
749 switch (opcode & 0xf) {
750 case 0x0: /* MOV_LLT: N^V */
751 if (NxorV)
752 goto take_the_loop;
753 return;
754 case 0x1: /* MOV_LGT: ~(Z or (N^V))*/
755 if (!((epsw & EPSW_FLAG_Z) | NxorV))
756 goto take_the_loop;
757 return;
758 case 0x2: /* MOV_LGE: ~(N^V) */
759 if (!NxorV)
760 goto take_the_loop;
761 return;
762 case 0x3: /* MOV_LLE: Z or (N^V) */
763 if ((epsw & EPSW_FLAG_Z) | NxorV)
764 goto take_the_loop;
765 return;
766
767 case 0x4: /* MOV_LCS: C */
768 if (epsw & EPSW_FLAG_C)
769 goto take_the_loop;
770 return;
771 case 0x5: /* MOV_LHI: ~(C or Z) */
772 if (!(epsw & (EPSW_FLAG_C | EPSW_FLAG_Z)))
773 goto take_the_loop;
774 return;
775 case 0x6: /* MOV_LCC: ~C */
776 if (!(epsw & EPSW_FLAG_C))
777 goto take_the_loop;
778 return;
779 case 0x7: /* MOV_LLS: C or Z */
780 if (epsw & (EPSW_FLAG_C | EPSW_FLAG_Z))
781 goto take_the_loop;
782 return;
783
784 case 0x8: /* MOV_LEQ: Z */
785 if (epsw & EPSW_FLAG_Z)
786 goto take_the_loop;
787 return;
788 case 0x9: /* MOV_LNE: ~Z */
789 if (!(epsw & EPSW_FLAG_Z))
790 goto take_the_loop;
791 return;
792 case 0xa: /* MOV_LRA: always */
793 goto take_the_loop;
794
795 default:
796 BUG();
797 }
798
799 take_the_loop:
800 /* wind the PC back to just after the SETLB insn */
801 kdebug("loop LAR=%lx", regs->lar);
802 regs->pc = regs->lar - 4;
803 }
804
805 /*
806 * misalignment handler tests
807 */
808 #ifdef CONFIG_TEST_MISALIGNMENT_HANDLER
809 static u8 __initdata testbuf[512] __attribute__((aligned(16))) = {
810 [257] = 0x11,
811 [258] = 0x22,
812 [259] = 0x33,
813 [260] = 0x44,
814 };
815
816 #define ASSERTCMP(X, OP, Y) \
817 do { \
818 if (unlikely(!((X) OP (Y)))) { \
819 printk(KERN_ERR "\n"); \
820 printk(KERN_ERR "MISALIGN: Assertion failed at line %u\n", \
821 __LINE__); \
822 printk(KERN_ERR "0x%lx " #OP " 0x%lx is false\n", \
823 (unsigned long)(X), (unsigned long)(Y)); \
824 BUG(); \
825 } \
826 } while(0)
827
828 static int __init test_misalignment(void)
829 {
830 register void *r asm("e0");
831 register u32 y asm("e1");
832 void *p = testbuf, *q;
833 u32 tmp, tmp2, x;
834
835 printk(KERN_NOTICE "==>test_misalignment() [testbuf=%p]\n", p);
836 p++;
837
838 printk(KERN_NOTICE "___ MOV (Am),Dn ___\n");
839 q = p + 256;
840 asm volatile("mov (%0),%1" : "+a"(q), "=d"(x));
841 ASSERTCMP(q, ==, p + 256);
842 ASSERTCMP(x, ==, 0x44332211);
843
844 printk(KERN_NOTICE "___ MOV (256,Am),Dn ___\n");
845 q = p;
846 asm volatile("mov (256,%0),%1" : "+a"(q), "=d"(x));
847 ASSERTCMP(q, ==, p);
848 ASSERTCMP(x, ==, 0x44332211);
849
850 printk(KERN_NOTICE "___ MOV (Di,Am),Dn ___\n");
851 tmp = 256;
852 q = p;
853 asm volatile("mov (%2,%0),%1" : "+a"(q), "=d"(x), "+d"(tmp));
854 ASSERTCMP(q, ==, p);
855 ASSERTCMP(x, ==, 0x44332211);
856 ASSERTCMP(tmp, ==, 256);
857
858 printk(KERN_NOTICE "___ MOV (256,Rm),Rn ___\n");
859 r = p;
860 asm volatile("mov (256,%0),%1" : "+r"(r), "=r"(y));
861 ASSERTCMP(r, ==, p);
862 ASSERTCMP(y, ==, 0x44332211);
863
864 printk(KERN_NOTICE "___ MOV (Rm+),Rn ___\n");
865 r = p + 256;
866 asm volatile("mov (%0+),%1" : "+r"(r), "=r"(y));
867 ASSERTCMP(r, ==, p + 256 + 4);
868 ASSERTCMP(y, ==, 0x44332211);
869
870 printk(KERN_NOTICE "___ MOV (Rm+,8),Rn ___\n");
871 r = p + 256;
872 asm volatile("mov (%0+,8),%1" : "+r"(r), "=r"(y));
873 ASSERTCMP(r, ==, p + 256 + 8);
874 ASSERTCMP(y, ==, 0x44332211);
875
876 printk(KERN_NOTICE "___ MOV (7,SP),Rn ___\n");
877 asm volatile(
878 "add -16,sp \n"
879 "mov +0x11,%0 \n"
880 "movbu %0,(7,sp) \n"
881 "mov +0x22,%0 \n"
882 "movbu %0,(8,sp) \n"
883 "mov +0x33,%0 \n"
884 "movbu %0,(9,sp) \n"
885 "mov +0x44,%0 \n"
886 "movbu %0,(10,sp) \n"
887 "mov (7,sp),%1 \n"
888 "add +16,sp \n"
889 : "+a"(q), "=d"(x));
890 ASSERTCMP(x, ==, 0x44332211);
891
892 printk(KERN_NOTICE "___ MOV (259,SP),Rn ___\n");
893 asm volatile(
894 "add -264,sp \n"
895 "mov +0x11,%0 \n"
896 "movbu %0,(259,sp) \n"
897 "mov +0x22,%0 \n"
898 "movbu %0,(260,sp) \n"
899 "mov +0x33,%0 \n"
900 "movbu %0,(261,sp) \n"
901 "mov +0x55,%0 \n"
902 "movbu %0,(262,sp) \n"
903 "mov (259,sp),%1 \n"
904 "add +264,sp \n"
905 : "+d"(tmp), "=d"(x));
906 ASSERTCMP(x, ==, 0x55332211);
907
908 printk(KERN_NOTICE "___ MOV (260,SP),Rn ___\n");
909 asm volatile(
910 "add -264,sp \n"
911 "mov +0x11,%0 \n"
912 "movbu %0,(260,sp) \n"
913 "mov +0x22,%0 \n"
914 "movbu %0,(261,sp) \n"
915 "mov +0x33,%0 \n"
916 "movbu %0,(262,sp) \n"
917 "mov +0x55,%0 \n"
918 "movbu %0,(263,sp) \n"
919 "mov (260,sp),%1 \n"
920 "add +264,sp \n"
921 : "+d"(tmp), "=d"(x));
922 ASSERTCMP(x, ==, 0x55332211);
923
924
925 printk(KERN_NOTICE "___ MOV_LNE ___\n");
926 tmp = 1;
927 tmp2 = 2;
928 q = p + 256;
929 asm volatile(
930 "setlb \n"
931 "mov %2,%3 \n"
932 "mov %1,%2 \n"
933 "cmp +0,%1 \n"
934 "mov_lne (%0+,4),%1"
935 : "+r"(q), "+d"(tmp), "+d"(tmp2), "=d"(x)
936 :
937 : "cc");
938 ASSERTCMP(q, ==, p + 256 + 12);
939 ASSERTCMP(x, ==, 0x44332211);
940
941 printk(KERN_NOTICE "___ MOV in SETLB ___\n");
942 tmp = 1;
943 tmp2 = 2;
944 q = p + 256;
945 asm volatile(
946 "setlb \n"
947 "mov %1,%3 \n"
948 "mov (%0+),%1 \n"
949 "cmp +0,%1 \n"
950 "lne "
951 : "+a"(q), "+d"(tmp), "+d"(tmp2), "=d"(x)
952 :
953 : "cc");
954
955 ASSERTCMP(q, ==, p + 256 + 8);
956 ASSERTCMP(x, ==, 0x44332211);
957
958 printk(KERN_NOTICE "<==test_misalignment()\n");
959 return 0;
960 }
961
962 arch_initcall(test_misalignment);
963
964 #endif /* CONFIG_TEST_MISALIGNMENT_HANDLER */
Tomato firmware and modifications.