2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
16 * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
17 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
18 * Copyright (C) 2007 MIPS Technologies, Inc.
19 * written by Ralf Baechle <ralf@linux-mips.org>
24 #include <linux/device.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/vmalloc.h>
32 #include <linux/errno.h>
33 #include <linux/wait.h>
35 #include <asm/sibyte/sb1250.h>
37 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
38 #include <asm/sibyte/bcm1480_regs.h>
39 #include <asm/sibyte/bcm1480_scd.h>
40 #include <asm/sibyte/bcm1480_int.h>
41 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
42 #include <asm/sibyte/sb1250_regs.h>
43 #include <asm/sibyte/sb1250_scd.h>
44 #include <asm/sibyte/sb1250_int.h>
46 #error invalid SiByte UART configuation
49 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
50 #undef K_INT_TRACE_FREEZE
51 #define K_INT_TRACE_FREEZE K_BCM1480_INT_TRACE_FREEZE
53 #define K_INT_PERF_CNT K_BCM1480_INT_PERF_CNT
56 #include <asm/system.h>
57 #include <asm/uaccess.h>
59 #define SBPROF_TB_MAJOR 240
61 typedef u64 tb_sample_t
[6*256];
70 wait_queue_head_t tb_sync
;
71 wait_queue_head_t tb_read
;
73 enum open_status open
;
74 tb_sample_t
*sbprof_tbbuf
;
77 volatile int tb_enable
;
78 volatile int tb_armed
;
82 static struct sbprof_tb sbp
;
84 #define MAX_SAMPLE_BYTES (24*1024*1024)
85 #define MAX_TBSAMPLE_BYTES (12*1024*1024)
87 #define MAX_SAMPLES (MAX_SAMPLE_BYTES/sizeof(u_int32_t))
88 #define TB_SAMPLE_SIZE (sizeof(tb_sample_t))
89 #define MAX_TB_SAMPLES (MAX_TBSAMPLE_BYTES/TB_SAMPLE_SIZE)
92 #define SBPROF_ZBSTART _IOW('s', 0, int)
93 #define SBPROF_ZBSTOP _IOW('s', 1, int)
94 #define SBPROF_ZBWAITFULL _IOW('s', 2, int)
97 * Routines for using 40-bit SCD cycle counter
99 * Client responsible for either handling interrupts or making sure
100 * the cycles counter never saturates, e.g., by doing
101 * zclk_timer_init(0) at least every 2^40 - 1 ZCLKs.
105 * Configures SCD counter 0 to count ZCLKs starting from val;
106 * Configures SCD counters1,2,3 to count nothing.
107 * Must not be called while gathering ZBbus profiles.
110 #define zclk_timer_init(val) \
111 __asm__ __volatile__ (".set push;" \
113 "la $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
114 "sd %0, 0x10($8);" /* write val to counter0 */ \
115 "sd %1, 0($8);" /* config counter0 for zclks*/ \
118 /* enable, counter0 */ \
119 : /* inputs */ "r"(val), "r" ((1ULL << 33) | 1ULL) \
120 : /* modifies */ "$8" )
123 /* Reads SCD counter 0 and puts result in value
124 unsigned long long val; */
125 #define zclk_get(val) \
126 __asm__ __volatile__ (".set push;" \
128 "la $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
129 "ld %0, 0x10($8);" /* write val to counter0 */ \
131 : /* outputs */ "=r"(val) \
133 : /* modifies */ "$8" )
135 #define DEVNAME "sb_tbprof"
137 #define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES)
140 * Support for ZBbus sampling using the trace buffer
142 * We use the SCD performance counter interrupt, caused by a Zclk counter
143 * overflow, to trigger the start of tracing.
145 * We set the trace buffer to sample everything and freeze on
148 * We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
152 static u64 tb_period
;
154 static void arm_tb(void)
157 u64 next
= (1ULL << 40) - tb_period
;
158 u64 tb_options
= M_SCD_TRACE_CFG_FREEZE_FULL
;
160 __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1
));
161 scdperfcnt
= __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG
));
164 * Unfortunately, in Pass 2 we must clear all counters to knock down
165 * a previous interrupt request. This means that bus profiling
166 * requires ALL of the SCD perf counters.
168 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
169 __raw_writeq((scdperfcnt
& ~M_SPC_CFG_SRC1
) |
170 /* keep counters 0,2,3,4,5,6,7 as is */
171 V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */
172 IOADDR(A_BCM1480_SCD_PERF_CNT_CFG0
));
174 M_SPC_CFG_ENABLE
| /* enable counting */
175 M_SPC_CFG_CLEAR
| /* clear all counters */
176 V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */
177 IOADDR(A_BCM1480_SCD_PERF_CNT_CFG1
));
179 __raw_writeq((scdperfcnt
& ~M_SPC_CFG_SRC1
) |
180 /* keep counters 0,2,3 as is */
181 M_SPC_CFG_ENABLE
| /* enable counting */
182 M_SPC_CFG_CLEAR
| /* clear all counters */
183 V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */
184 IOADDR(A_SCD_PERF_CNT_CFG
));
186 __raw_writeq(next
, IOADDR(A_SCD_PERF_CNT_1
));
187 /* Reset the trace buffer */
188 __raw_writeq(M_SCD_TRACE_CFG_RESET
, IOADDR(A_SCD_TRACE_CFG
));
189 __raw_writeq(tb_options
, IOADDR(A_SCD_TRACE_CFG
));
193 static irqreturn_t
sbprof_tb_intr(int irq
, void *dev_id
)
197 pr_debug(DEVNAME
": tb_intr\n");
199 if (sbp
.next_tb_sample
< MAX_TB_SAMPLES
) {
200 u64
*p
= sbp
.sbprof_tbbuf
[sbp
.next_tb_sample
++];
202 __raw_writeq(M_SCD_TRACE_CFG_START_READ
,
203 IOADDR(A_SCD_TRACE_CFG
));
204 __asm__
__volatile__ ("sync" : : : "memory");
205 /* Loop runs backwards because bundles are read out in reverse order */
206 for (i
= 256 * 6; i
> 0; i
-= 6) {
207 /* Subscripts decrease to put bundle in the order */
208 /* t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi */
209 p
[i
- 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ
));
211 p
[i
- 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ
));
213 p
[i
- 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ
));
215 p
[i
- 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ
));
217 p
[i
- 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ
));
219 p
[i
- 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ
));
222 if (!sbp
.tb_enable
) {
223 pr_debug(DEVNAME
": tb_intr shutdown\n");
224 __raw_writeq(M_SCD_TRACE_CFG_RESET
,
225 IOADDR(A_SCD_TRACE_CFG
));
227 wake_up_interruptible(&sbp
.tb_sync
);
229 /* knock down current interrupt and get another one later */
233 /* No more trace buffer samples */
234 pr_debug(DEVNAME
": tb_intr full\n");
235 __raw_writeq(M_SCD_TRACE_CFG_RESET
, IOADDR(A_SCD_TRACE_CFG
));
238 wake_up_interruptible(&sbp
.tb_sync
);
239 wake_up_interruptible(&sbp
.tb_read
);
244 static irqreturn_t
sbprof_pc_intr(int irq
, void *dev_id
)
246 printk(DEVNAME
": unexpected pc_intr");
251 * Requires: Already called zclk_timer_init with a value that won't
252 * saturate 40 bits. No subsequent use of SCD performance counters
256 static int sbprof_zbprof_start(struct file
*filp
)
261 if (xchg(&sbp
.tb_enable
, 1))
264 pr_debug(DEVNAME
": starting\n");
266 sbp
.next_tb_sample
= 0;
269 err
= request_irq(K_INT_TRACE_FREEZE
, sbprof_tb_intr
, 0,
270 DEVNAME
" trace freeze", &sbp
);
274 /* Make sure there isn't a perf-cnt interrupt waiting */
275 scdperfcnt
= __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG
));
276 /* Disable and clear counters, override SRC_1 */
277 __raw_writeq((scdperfcnt
& ~(M_SPC_CFG_SRC1
| M_SPC_CFG_ENABLE
)) |
278 M_SPC_CFG_ENABLE
| M_SPC_CFG_CLEAR
| V_SPC_CFG_SRC1(1),
279 IOADDR(A_SCD_PERF_CNT_CFG
));
282 * We grab this interrupt to prevent others from trying to use
283 * it, even though we don't want to service the interrupts
284 * (they only feed into the trace-on-interrupt mechanism)
286 if (request_irq(K_INT_PERF_CNT
, sbprof_pc_intr
, 0, DEVNAME
" scd perfcnt", &sbp
)) {
287 free_irq(K_INT_TRACE_FREEZE
, &sbp
);
292 * I need the core to mask these, but the interrupt mapper to
293 * pass them through. I am exploiting my knowledge that
294 * cp0_status masks out IP[5]. krw
296 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
297 __raw_writeq(K_BCM1480_INT_MAP_I3
,
298 IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_L
) +
299 ((K_BCM1480_INT_PERF_CNT
& 0x3f) << 3)));
301 __raw_writeq(K_INT_MAP_I3
,
302 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE
) +
303 (K_INT_PERF_CNT
<< 3)));
306 /* Initialize address traps */
307 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0
));
308 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1
));
309 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2
));
310 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3
));
312 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0
));
313 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1
));
314 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2
));
315 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3
));
317 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0
));
318 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1
));
319 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2
));
320 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3
));
322 /* Initialize Trace Event 0-7 */
324 __raw_writeq(M_SCD_TREVT_INTERRUPT
, IOADDR(A_SCD_TRACE_EVENT_0
));
325 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1
));
326 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2
));
327 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3
));
328 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4
));
329 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5
));
330 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6
));
331 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7
));
333 /* Initialize Trace Sequence 0-7 */
334 /* Start on event 0 (interrupt) */
335 __raw_writeq(V_SCD_TRSEQ_FUNC_START
| 0x0fff,
336 IOADDR(A_SCD_TRACE_SEQUENCE_0
));
337 /* dsamp when d used | asamp when a used */
338 __raw_writeq(M_SCD_TRSEQ_ASAMPLE
| M_SCD_TRSEQ_DSAMPLE
|
339 K_SCD_TRSEQ_TRIGGER_ALL
,
340 IOADDR(A_SCD_TRACE_SEQUENCE_1
));
341 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2
));
342 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3
));
343 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4
));
344 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5
));
345 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6
));
346 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7
));
348 /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
349 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
350 __raw_writeq(1ULL << (K_BCM1480_INT_PERF_CNT
& 0x3f),
351 IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_TRACE_L
)));
353 __raw_writeq(1ULL << K_INT_PERF_CNT
,
354 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE
)));
358 pr_debug(DEVNAME
": done starting\n");
363 static int sbprof_zbprof_stop(void)
367 pr_debug(DEVNAME
": stopping\n");
371 * XXXKW there is a window here where the intr handler may run,
372 * see the disable, and do the wake_up before this sleep
375 pr_debug(DEVNAME
": wait for disarm\n");
376 err
= wait_event_interruptible(sbp
.tb_sync
, !sbp
.tb_armed
);
377 pr_debug(DEVNAME
": disarm complete, stat %d\n", err
);
383 free_irq(K_INT_TRACE_FREEZE
, &sbp
);
384 free_irq(K_INT_PERF_CNT
, &sbp
);
387 pr_debug(DEVNAME
": done stopping\n");
392 static int sbprof_tb_open(struct inode
*inode
, struct file
*filp
)
396 minor
= iminor(inode
);
400 if (xchg(&sbp
.open
, SB_OPENING
) != SB_CLOSED
)
403 memset(&sbp
, 0, sizeof(struct sbprof_tb
));
404 sbp
.sbprof_tbbuf
= vmalloc(MAX_TBSAMPLE_BYTES
);
405 if (!sbp
.sbprof_tbbuf
) {
406 sbp
.open
= SB_CLOSED
;
411 memset(sbp
.sbprof_tbbuf
, 0, MAX_TBSAMPLE_BYTES
);
412 init_waitqueue_head(&sbp
.tb_sync
);
413 init_waitqueue_head(&sbp
.tb_read
);
414 mutex_init(&sbp
.lock
);
422 static int sbprof_tb_release(struct inode
*inode
, struct file
*filp
)
426 minor
= iminor(inode
);
427 if (minor
!= 0 || sbp
.open
!= SB_CLOSED
)
430 mutex_lock(&sbp
.lock
);
432 if (sbp
.tb_armed
|| sbp
.tb_enable
)
433 sbprof_zbprof_stop();
435 vfree(sbp
.sbprof_tbbuf
);
436 sbp
.open
= SB_CLOSED
;
439 mutex_unlock(&sbp
.lock
);
444 static ssize_t
sbprof_tb_read(struct file
*filp
, char *buf
,
445 size_t size
, loff_t
*offp
)
447 int cur_sample
, sample_off
, cur_count
, sample_left
;
451 long cur_off
= *offp
;
453 if (!access_ok(VERIFY_WRITE
, buf
, size
))
456 mutex_lock(&sbp
.lock
);
459 cur_sample
= cur_off
/ TB_SAMPLE_SIZE
;
460 sample_off
= cur_off
% TB_SAMPLE_SIZE
;
461 sample_left
= TB_SAMPLE_SIZE
- sample_off
;
463 while (size
&& (cur_sample
< sbp
.next_tb_sample
)) {
466 cur_count
= size
< sample_left
? size
: sample_left
;
467 src
= (char *)(((long)sbp
.sbprof_tbbuf
[cur_sample
])+sample_off
);
468 err
= __copy_to_user(dest
, src
, cur_count
);
470 *offp
= cur_off
+ cur_count
- err
;
471 mutex_unlock(&sbp
.lock
);
474 pr_debug(DEVNAME
": read from sample %d, %d bytes\n",
475 cur_sample
, cur_count
);
477 sample_left
-= cur_count
;
481 sample_left
= TB_SAMPLE_SIZE
;
483 sample_off
+= cur_count
;
485 cur_off
+= cur_count
;
490 mutex_unlock(&sbp
.lock
);
495 static long sbprof_tb_ioctl(struct file
*filp
,
496 unsigned int command
,
503 mutex_lock(&sbp
.lock
);
504 err
= sbprof_zbprof_start(filp
);
505 mutex_unlock(&sbp
.lock
);
509 mutex_lock(&sbp
.lock
);
510 err
= sbprof_zbprof_stop();
511 mutex_unlock(&sbp
.lock
);
514 case SBPROF_ZBWAITFULL
: {
515 err
= wait_event_interruptible(sbp
.tb_read
, TB_FULL
);
519 err
= put_user(TB_FULL
, (int *) arg
);
531 static const struct file_operations sbprof_tb_fops
= {
532 .owner
= THIS_MODULE
,
533 .open
= sbprof_tb_open
,
534 .release
= sbprof_tb_release
,
535 .read
= sbprof_tb_read
,
536 .unlocked_ioctl
= sbprof_tb_ioctl
,
537 .compat_ioctl
= sbprof_tb_ioctl
,
541 static struct class *tb_class
;
542 static struct device
*tb_dev
;
544 static int __init
sbprof_tb_init(void)
550 if (register_chrdev(SBPROF_TB_MAJOR
, DEVNAME
, &sbprof_tb_fops
)) {
551 printk(KERN_WARNING DEVNAME
": initialization failed (dev %d)\n",
556 tbc
= class_create(THIS_MODULE
, "sb_tracebuffer");
564 dev
= device_create(tbc
, NULL
, MKDEV(SBPROF_TB_MAJOR
, 0), NULL
, "tb");
571 sbp
.open
= SB_CLOSED
;
573 tb_period
= zbbus_mhz
* 10000LL;
574 pr_info(DEVNAME
": initialized - tb_period = %lld\n",
575 (long long) tb_period
);
579 class_destroy(tb_class
);
581 unregister_chrdev(SBPROF_TB_MAJOR
, DEVNAME
);
586 static void __exit
sbprof_tb_cleanup(void)
588 device_destroy(tb_class
, MKDEV(SBPROF_TB_MAJOR
, 0));
589 unregister_chrdev(SBPROF_TB_MAJOR
, DEVNAME
);
590 class_destroy(tb_class
);
593 module_init(sbprof_tb_init
);
594 module_exit(sbprof_tb_cleanup
);
596 MODULE_ALIAS_CHARDEV_MAJOR(SBPROF_TB_MAJOR
);
597 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
598 MODULE_LICENSE("GPL");