2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2007, 2008 Cavium Networks
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/interrupt.h>
12 #include <linux/time.h>
13 #include <linux/delay.h>
15 #include <asm/octeon/octeon.h>
16 #include <asm/octeon/cvmx-npei-defs.h>
17 #include <asm/octeon/cvmx-pciercx-defs.h>
18 #include <asm/octeon/cvmx-pescx-defs.h>
19 #include <asm/octeon/cvmx-pexp-defs.h>
20 #include <asm/octeon/cvmx-helper-errata.h>
21 #include <asm/octeon/pci-octeon.h>
23 union cvmx_pcie_address
{
26 uint64_t upper
:2; /* Normally 2 for XKPHYS */
27 uint64_t reserved_49_61
:13; /* Must be zero */
28 uint64_t io
:1; /* 1 for IO space access */
29 uint64_t did
:5; /* PCIe DID = 3 */
30 uint64_t subdid
:3; /* PCIe SubDID = 1 */
31 uint64_t reserved_36_39
:4; /* Must be zero */
32 uint64_t es
:2; /* Endian swap = 1 */
33 uint64_t port
:2; /* PCIe port 0,1 */
34 uint64_t reserved_29_31
:3; /* Must be zero */
36 * Selects the type of the configuration request (0 = type 0,
40 /* Target bus number sent in the ID in the request. */
43 * Target device number sent in the ID in the
44 * request. Note that Dev must be zero for type 0
45 * configuration requests.
48 /* Target function number sent in the ID in the request. */
51 * Selects a register in the configuration space of
57 uint64_t upper
:2; /* Normally 2 for XKPHYS */
58 uint64_t reserved_49_61
:13; /* Must be zero */
59 uint64_t io
:1; /* 1 for IO space access */
60 uint64_t did
:5; /* PCIe DID = 3 */
61 uint64_t subdid
:3; /* PCIe SubDID = 2 */
62 uint64_t reserved_36_39
:4; /* Must be zero */
63 uint64_t es
:2; /* Endian swap = 1 */
64 uint64_t port
:2; /* PCIe port 0,1 */
65 uint64_t address
:32; /* PCIe IO address */
68 uint64_t upper
:2; /* Normally 2 for XKPHYS */
69 uint64_t reserved_49_61
:13; /* Must be zero */
70 uint64_t io
:1; /* 1 for IO space access */
71 uint64_t did
:5; /* PCIe DID = 3 */
72 uint64_t subdid
:3; /* PCIe SubDID = 3-6 */
73 uint64_t reserved_36_39
:4; /* Must be zero */
74 uint64_t address
:36; /* PCIe Mem address */
79 * Return the Core virtual base address for PCIe IO access. IOs are
80 * read/written as an offset from this address.
82 * @pcie_port: PCIe port the IO is for
84 * Returns 64bit Octeon IO base address for read/write
86 static inline uint64_t cvmx_pcie_get_io_base_address(int pcie_port
)
88 union cvmx_pcie_address pcie_addr
;
90 pcie_addr
.io
.upper
= 0;
93 pcie_addr
.io
.subdid
= 2;
95 pcie_addr
.io
.port
= pcie_port
;
100 * Size of the IO address region returned at address
101 * cvmx_pcie_get_io_base_address()
103 * @pcie_port: PCIe port the IO is for
105 * Returns Size of the IO window
107 static inline uint64_t cvmx_pcie_get_io_size(int pcie_port
)
113 * Return the Core virtual base address for PCIe MEM access. Memory is
114 * read/written as an offset from this address.
116 * @pcie_port: PCIe port the IO is for
118 * Returns 64bit Octeon IO base address for read/write
120 static inline uint64_t cvmx_pcie_get_mem_base_address(int pcie_port
)
122 union cvmx_pcie_address pcie_addr
;
124 pcie_addr
.mem
.upper
= 0;
125 pcie_addr
.mem
.io
= 1;
126 pcie_addr
.mem
.did
= 3;
127 pcie_addr
.mem
.subdid
= 3 + pcie_port
;
128 return pcie_addr
.u64
;
132 * Size of the Mem address region returned at address
133 * cvmx_pcie_get_mem_base_address()
135 * @pcie_port: PCIe port the IO is for
137 * Returns Size of the Mem window
139 static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port
)
145 * Read a PCIe config space register indirectly. This is used for
146 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
148 * @pcie_port: PCIe port to read from
149 * @cfg_offset: Address to read
153 static uint32_t cvmx_pcie_cfgx_read(int pcie_port
, uint32_t cfg_offset
)
155 union cvmx_pescx_cfg_rd pescx_cfg_rd
;
156 pescx_cfg_rd
.u64
= 0;
157 pescx_cfg_rd
.s
.addr
= cfg_offset
;
158 cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port
), pescx_cfg_rd
.u64
);
159 pescx_cfg_rd
.u64
= cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port
));
160 return pescx_cfg_rd
.s
.data
;
164 * Write a PCIe config space register indirectly. This is used for
165 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
167 * @pcie_port: PCIe port to write to
168 * @cfg_offset: Address to write
169 * @val: Value to write
171 static void cvmx_pcie_cfgx_write(int pcie_port
, uint32_t cfg_offset
,
174 union cvmx_pescx_cfg_wr pescx_cfg_wr
;
175 pescx_cfg_wr
.u64
= 0;
176 pescx_cfg_wr
.s
.addr
= cfg_offset
;
177 pescx_cfg_wr
.s
.data
= val
;
178 cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port
), pescx_cfg_wr
.u64
);
182 * Build a PCIe config space request address for a device
184 * @pcie_port: PCIe port to access
187 * @fn: Device sub function
188 * @reg: Register to access
190 * Returns 64bit Octeon IO address
192 static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port
, int bus
,
193 int dev
, int fn
, int reg
)
195 union cvmx_pcie_address pcie_addr
;
196 union cvmx_pciercx_cfg006 pciercx_cfg006
;
199 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG006(pcie_port
));
200 if ((bus
<= pciercx_cfg006
.s
.pbnum
) && (dev
!= 0))
204 pcie_addr
.config
.upper
= 2;
205 pcie_addr
.config
.io
= 1;
206 pcie_addr
.config
.did
= 3;
207 pcie_addr
.config
.subdid
= 1;
208 pcie_addr
.config
.es
= 1;
209 pcie_addr
.config
.port
= pcie_port
;
210 pcie_addr
.config
.ty
= (bus
> pciercx_cfg006
.s
.pbnum
);
211 pcie_addr
.config
.bus
= bus
;
212 pcie_addr
.config
.dev
= dev
;
213 pcie_addr
.config
.func
= fn
;
214 pcie_addr
.config
.reg
= reg
;
215 return pcie_addr
.u64
;
219 * Read 8bits from a Device's config space
221 * @pcie_port: PCIe port the device is on
224 * @fn: Device sub function
225 * @reg: Register to access
227 * Returns Result of the read
229 static uint8_t cvmx_pcie_config_read8(int pcie_port
, int bus
, int dev
,
233 __cvmx_pcie_build_config_addr(pcie_port
, bus
, dev
, fn
, reg
);
235 return cvmx_read64_uint8(address
);
241 * Read 16bits from a Device's config space
243 * @pcie_port: PCIe port the device is on
246 * @fn: Device sub function
247 * @reg: Register to access
249 * Returns Result of the read
251 static uint16_t cvmx_pcie_config_read16(int pcie_port
, int bus
, int dev
,
255 __cvmx_pcie_build_config_addr(pcie_port
, bus
, dev
, fn
, reg
);
257 return le16_to_cpu(cvmx_read64_uint16(address
));
263 * Read 32bits from a Device's config space
265 * @pcie_port: PCIe port the device is on
268 * @fn: Device sub function
269 * @reg: Register to access
271 * Returns Result of the read
273 static uint32_t cvmx_pcie_config_read32(int pcie_port
, int bus
, int dev
,
277 __cvmx_pcie_build_config_addr(pcie_port
, bus
, dev
, fn
, reg
);
279 return le32_to_cpu(cvmx_read64_uint32(address
));
285 * Write 8bits to a Device's config space
287 * @pcie_port: PCIe port the device is on
290 * @fn: Device sub function
291 * @reg: Register to access
292 * @val: Value to write
294 static void cvmx_pcie_config_write8(int pcie_port
, int bus
, int dev
, int fn
,
295 int reg
, uint8_t val
)
298 __cvmx_pcie_build_config_addr(pcie_port
, bus
, dev
, fn
, reg
);
300 cvmx_write64_uint8(address
, val
);
304 * Write 16bits to a Device's config space
306 * @pcie_port: PCIe port the device is on
309 * @fn: Device sub function
310 * @reg: Register to access
311 * @val: Value to write
313 static void cvmx_pcie_config_write16(int pcie_port
, int bus
, int dev
, int fn
,
314 int reg
, uint16_t val
)
317 __cvmx_pcie_build_config_addr(pcie_port
, bus
, dev
, fn
, reg
);
319 cvmx_write64_uint16(address
, cpu_to_le16(val
));
323 * Write 32bits to a Device's config space
325 * @pcie_port: PCIe port the device is on
328 * @fn: Device sub function
329 * @reg: Register to access
330 * @val: Value to write
332 static void cvmx_pcie_config_write32(int pcie_port
, int bus
, int dev
, int fn
,
333 int reg
, uint32_t val
)
336 __cvmx_pcie_build_config_addr(pcie_port
, bus
, dev
, fn
, reg
);
338 cvmx_write64_uint32(address
, cpu_to_le32(val
));
342 * Initialize the RC config space CSRs
344 * @pcie_port: PCIe port to initialize
346 static void __cvmx_pcie_rc_initialize_config_space(int pcie_port
)
348 union cvmx_pciercx_cfg030 pciercx_cfg030
;
349 union cvmx_npei_ctl_status2 npei_ctl_status2
;
350 union cvmx_pciercx_cfg070 pciercx_cfg070
;
351 union cvmx_pciercx_cfg001 pciercx_cfg001
;
352 union cvmx_pciercx_cfg032 pciercx_cfg032
;
353 union cvmx_pciercx_cfg006 pciercx_cfg006
;
354 union cvmx_pciercx_cfg008 pciercx_cfg008
;
355 union cvmx_pciercx_cfg009 pciercx_cfg009
;
356 union cvmx_pciercx_cfg010 pciercx_cfg010
;
357 union cvmx_pciercx_cfg011 pciercx_cfg011
;
358 union cvmx_pciercx_cfg035 pciercx_cfg035
;
359 union cvmx_pciercx_cfg075 pciercx_cfg075
;
360 union cvmx_pciercx_cfg034 pciercx_cfg034
;
362 /* Max Payload Size (PCIE*_CFG030[MPS]) */
363 /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
364 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
365 /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
367 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG030(pcie_port
));
369 * Max payload size = 128 bytes for best Octeon DMA
372 pciercx_cfg030
.s
.mps
= 0;
374 * Max read request size = 128 bytes for best Octeon DMA
377 pciercx_cfg030
.s
.mrrs
= 0;
378 /* Enable relaxed ordering. */
379 pciercx_cfg030
.s
.ro_en
= 1;
380 /* Enable no snoop. */
381 pciercx_cfg030
.s
.ns_en
= 1;
382 /* Correctable error reporting enable. */
383 pciercx_cfg030
.s
.ce_en
= 1;
384 /* Non-fatal error reporting enable. */
385 pciercx_cfg030
.s
.nfe_en
= 1;
386 /* Fatal error reporting enable. */
387 pciercx_cfg030
.s
.fe_en
= 1;
388 /* Unsupported request reporting enable. */
389 pciercx_cfg030
.s
.ur_en
= 1;
390 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG030(pcie_port
),
394 * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
397 * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not
398 * exceed PCIE*_CFG030[MRRS].
400 npei_ctl_status2
.u64
= cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2
);
401 /* Max payload size = 128 bytes for best Octeon DMA performance */
402 npei_ctl_status2
.s
.mps
= 0;
403 /* Max read request size = 128 bytes for best Octeon DMA performance */
404 npei_ctl_status2
.s
.mrrs
= 0;
406 npei_ctl_status2
.s
.c1_b1_s
= 3; /* Port1 BAR1 Size 256MB */
408 npei_ctl_status2
.s
.c0_b1_s
= 3; /* Port0 BAR1 Size 256MB */
409 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2
, npei_ctl_status2
.u64
);
411 /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
413 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG070(pcie_port
));
414 pciercx_cfg070
.s
.ge
= 1; /* ECRC generation enable. */
415 pciercx_cfg070
.s
.ce
= 1; /* ECRC check enable. */
416 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG070(pcie_port
),
420 * Access Enables (PCIE*_CFG001[MSAE,ME]) ME and MSAE should
423 * Interrupt Disable (PCIE*_CFG001[I_DIS]) System Error
424 * Message Enable (PCIE*_CFG001[SEE])
427 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG001(pcie_port
));
428 pciercx_cfg001
.s
.msae
= 1; /* Memory space enable. */
429 pciercx_cfg001
.s
.me
= 1; /* Bus master enable. */
430 pciercx_cfg001
.s
.i_dis
= 1; /* INTx assertion disable. */
431 pciercx_cfg001
.s
.see
= 1; /* SERR# enable */
432 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG001(pcie_port
),
435 /* Advanced Error Recovery Message Enables */
436 /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
437 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG066(pcie_port
), 0);
438 /* Use CVMX_PCIERCX_CFG067 hardware default */
439 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG069(pcie_port
), 0);
441 /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
443 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG032(pcie_port
));
444 pciercx_cfg032
.s
.aslpc
= 0; /* Active state Link PM control. */
445 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG032(pcie_port
),
448 /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */
451 * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
452 * cvmx_pcie_rc_initialize_link()
454 * Primary Bus Number (PCIERCn_CFG006[PBNUM])
456 * We set the primary bus number to 1 so IDT bridges are
457 * happy. They don't like zero.
459 pciercx_cfg006
.u32
= 0;
460 pciercx_cfg006
.s
.pbnum
= 1;
461 pciercx_cfg006
.s
.sbnum
= 1;
462 pciercx_cfg006
.s
.subbnum
= 1;
463 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG006(pcie_port
),
467 * Memory-mapped I/O BAR (PCIERCn_CFG008)
468 * Most applications should disable the memory-mapped I/O BAR by
469 * setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR]
471 pciercx_cfg008
.u32
= 0;
472 pciercx_cfg008
.s
.mb_addr
= 0x100;
473 pciercx_cfg008
.s
.ml_addr
= 0;
474 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG008(pcie_port
),
478 * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
479 * Most applications should disable the prefetchable BAR by setting
480 * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
481 * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
484 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG009(pcie_port
));
486 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG010(pcie_port
));
488 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG011(pcie_port
));
489 pciercx_cfg009
.s
.lmem_base
= 0x100;
490 pciercx_cfg009
.s
.lmem_limit
= 0;
491 pciercx_cfg010
.s
.umem_base
= 0x100;
492 pciercx_cfg011
.s
.umem_limit
= 0;
493 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG009(pcie_port
),
495 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG010(pcie_port
),
497 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG011(pcie_port
),
501 * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
502 * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
505 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG035(pcie_port
));
506 /* System error on correctable error enable. */
507 pciercx_cfg035
.s
.secee
= 1;
508 /* System error on fatal error enable. */
509 pciercx_cfg035
.s
.sefee
= 1;
510 /* System error on non-fatal error enable. */
511 pciercx_cfg035
.s
.senfee
= 1;
512 /* PME interrupt enable. */
513 pciercx_cfg035
.s
.pmeie
= 1;
514 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG035(pcie_port
),
518 * Advanced Error Recovery Interrupt Enables
519 * (PCIERCn_CFG075[CERE,NFERE,FERE])
522 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG075(pcie_port
));
523 /* Correctable error reporting enable. */
524 pciercx_cfg075
.s
.cere
= 1;
525 /* Non-fatal error reporting enable. */
526 pciercx_cfg075
.s
.nfere
= 1;
527 /* Fatal error reporting enable. */
528 pciercx_cfg075
.s
.fere
= 1;
529 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG075(pcie_port
),
532 /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
533 * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
536 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG034(pcie_port
));
537 /* Hot-plug interrupt enable. */
538 pciercx_cfg034
.s
.hpint_en
= 1;
539 /* Data Link Layer state changed enable */
540 pciercx_cfg034
.s
.dlls_en
= 1;
541 /* Command completed interrupt enable. */
542 pciercx_cfg034
.s
.ccint_en
= 1;
543 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG034(pcie_port
),
548 * Initialize a host mode PCIe link. This function takes a PCIe
549 * port from reset to a link up state. Software can then begin
550 * configuring the rest of the link.
552 * @pcie_port: PCIe port to initialize
554 * Returns Zero on success
556 static int __cvmx_pcie_rc_initialize_link(int pcie_port
)
558 uint64_t start_cycle
;
559 union cvmx_pescx_ctl_status pescx_ctl_status
;
560 union cvmx_pciercx_cfg452 pciercx_cfg452
;
561 union cvmx_pciercx_cfg032 pciercx_cfg032
;
562 union cvmx_pciercx_cfg448 pciercx_cfg448
;
564 /* Set the lane width */
566 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG452(pcie_port
));
567 pescx_ctl_status
.u64
= cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port
));
568 if (pescx_ctl_status
.s
.qlm_cfg
== 0) {
569 /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
570 pciercx_cfg452
.s
.lme
= 0xf;
572 /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
573 pciercx_cfg452
.s
.lme
= 0x7;
575 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG452(pcie_port
),
579 * CN52XX pass 1.x has an errata where length mismatches on UR
580 * responses can cause bus errors on 64bit memory
581 * reads. Turning off length error checking fixes this.
583 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X
)) {
584 union cvmx_pciercx_cfg455 pciercx_cfg455
;
586 cvmx_pcie_cfgx_read(pcie_port
,
587 CVMX_PCIERCX_CFG455(pcie_port
));
588 pciercx_cfg455
.s
.m_cpl_len_err
= 1;
589 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG455(pcie_port
),
593 /* Lane swap needs to be manually enabled for CN52XX */
594 if (OCTEON_IS_MODEL(OCTEON_CN52XX
) && (pcie_port
== 1)) {
595 pescx_ctl_status
.s
.lane_swp
= 1;
596 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port
),
597 pescx_ctl_status
.u64
);
600 /* Bring up the link */
601 pescx_ctl_status
.u64
= cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port
));
602 pescx_ctl_status
.s
.lnk_enb
= 1;
603 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port
), pescx_ctl_status
.u64
);
606 * CN52XX pass 1.0: Due to a bug in 2nd order CDR, it needs to
609 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0
))
610 __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
612 /* Wait for the link to come up */
613 cvmx_dprintf("PCIe: Waiting for port %d link\n", pcie_port
);
614 start_cycle
= cvmx_get_cycle();
616 if (cvmx_get_cycle() - start_cycle
>
617 2 * cvmx_sysinfo_get()->cpu_clock_hz
) {
618 cvmx_dprintf("PCIe: Port %d link timeout\n",
624 cvmx_pcie_cfgx_read(pcie_port
,
625 CVMX_PCIERCX_CFG032(pcie_port
));
626 } while (pciercx_cfg032
.s
.dlla
== 0);
628 /* Display the link status */
629 cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port
,
630 pciercx_cfg032
.s
.nlw
);
633 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG448(pcie_port
));
634 switch (pciercx_cfg032
.s
.nlw
) {
636 pciercx_cfg448
.s
.rtl
= 1677;
638 case 2: /* 2 lanes */
639 pciercx_cfg448
.s
.rtl
= 867;
641 case 4: /* 4 lanes */
642 pciercx_cfg448
.s
.rtl
= 462;
644 case 8: /* 8 lanes */
645 pciercx_cfg448
.s
.rtl
= 258;
648 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG448(pcie_port
),
655 * Initialize a PCIe port for use in host(RC) mode. It doesn't
658 * @pcie_port: PCIe port to initialize
660 * Returns Zero on success
662 static int cvmx_pcie_rc_initialize(int pcie_port
)
667 union cvmx_ciu_soft_prst ciu_soft_prst
;
668 union cvmx_pescx_bist_status pescx_bist_status
;
669 union cvmx_pescx_bist_status2 pescx_bist_status2
;
670 union cvmx_npei_ctl_status npei_ctl_status
;
671 union cvmx_npei_mem_access_ctl npei_mem_access_ctl
;
672 union cvmx_npei_mem_access_subidx mem_access_subid
;
673 union cvmx_npei_dbg_data npei_dbg_data
;
674 union cvmx_pescx_ctl_status2 pescx_ctl_status2
;
675 union cvmx_npei_bar1_indexx bar1_index
;
678 * Make sure we aren't trying to setup a target mode interface
681 npei_ctl_status
.u64
= cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS
);
682 if ((pcie_port
== 0) && !npei_ctl_status
.s
.host_mode
) {
683 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called "
684 "on port0, but port0 is not in host mode\n");
689 * Make sure a CN52XX isn't trying to bring up port 1 when it
692 if (OCTEON_IS_MODEL(OCTEON_CN52XX
)) {
693 npei_dbg_data
.u64
= cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA
);
694 if ((pcie_port
== 1) && npei_dbg_data
.cn52xx
.qlm0_link_width
) {
695 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() "
696 "called on port1, but port1 is "
703 * PCIe switch arbitration mode. '0' == fixed priority NPEI,
704 * PCIe0, then PCIe1. '1' == round robin.
706 npei_ctl_status
.s
.arb
= 1;
707 /* Allow up to 0x20 config retries */
708 npei_ctl_status
.s
.cfg_rtry
= 0x20;
710 * CN52XX pass1.x has an errata where P0_NTAGS and P1_NTAGS
713 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X
)) {
714 npei_ctl_status
.s
.p0_ntags
= 0x20;
715 npei_ctl_status
.s
.p1_ntags
= 0x20;
717 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS
, npei_ctl_status
.u64
);
719 /* Bring the PCIe out of reset */
720 if (cvmx_sysinfo_get()->board_type
== CVMX_BOARD_TYPE_EBH5200
) {
721 if (pcie_port
== 0) {
722 ciu_soft_prst
.u64
= cvmx_read_csr(CVMX_CIU_SOFT_PRST
);
724 * After a chip reset the PCIe will also be in
725 * reset. If it isn't, most likely someone is
726 * trying to init it again without a proper
729 if (ciu_soft_prst
.s
.soft_prst
== 0) {
730 /* Reset the ports */
731 ciu_soft_prst
.s
.soft_prst
= 1;
732 cvmx_write_csr(CVMX_CIU_SOFT_PRST
,
735 cvmx_read_csr(CVMX_CIU_SOFT_PRST1
);
736 ciu_soft_prst
.s
.soft_prst
= 1;
737 cvmx_write_csr(CVMX_CIU_SOFT_PRST1
,
739 /* Wait until pcie resets the ports. */
742 ciu_soft_prst
.u64
= cvmx_read_csr(CVMX_CIU_SOFT_PRST1
);
743 ciu_soft_prst
.s
.soft_prst
= 0;
744 cvmx_write_csr(CVMX_CIU_SOFT_PRST1
, ciu_soft_prst
.u64
);
745 ciu_soft_prst
.u64
= cvmx_read_csr(CVMX_CIU_SOFT_PRST
);
746 ciu_soft_prst
.s
.soft_prst
= 0;
747 cvmx_write_csr(CVMX_CIU_SOFT_PRST
, ciu_soft_prst
.u64
);
751 * The normal case: The PCIe ports are completely
752 * separate and can be brought out of reset
756 ciu_soft_prst
.u64
= cvmx_read_csr(CVMX_CIU_SOFT_PRST1
);
758 ciu_soft_prst
.u64
= cvmx_read_csr(CVMX_CIU_SOFT_PRST
);
760 * After a chip reset the PCIe will also be in
761 * reset. If it isn't, most likely someone is trying
762 * to init it again without a proper PCIe reset.
764 if (ciu_soft_prst
.s
.soft_prst
== 0) {
766 ciu_soft_prst
.s
.soft_prst
= 1;
768 cvmx_write_csr(CVMX_CIU_SOFT_PRST1
,
771 cvmx_write_csr(CVMX_CIU_SOFT_PRST
,
773 /* Wait until pcie resets the ports. */
777 ciu_soft_prst
.u64
= cvmx_read_csr(CVMX_CIU_SOFT_PRST1
);
778 ciu_soft_prst
.s
.soft_prst
= 0;
779 cvmx_write_csr(CVMX_CIU_SOFT_PRST1
, ciu_soft_prst
.u64
);
781 ciu_soft_prst
.u64
= cvmx_read_csr(CVMX_CIU_SOFT_PRST
);
782 ciu_soft_prst
.s
.soft_prst
= 0;
783 cvmx_write_csr(CVMX_CIU_SOFT_PRST
, ciu_soft_prst
.u64
);
788 * Wait for PCIe reset to complete. Due to errata PCIE-700, we
789 * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
790 * fixed number of cycles.
794 /* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of CN56XX and
795 CN52XX, so we only probe it on newer chips */
796 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X
)
797 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X
)) {
798 /* Clear PCLK_RUN so we can check if the clock is running */
799 pescx_ctl_status2
.u64
=
800 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port
));
801 pescx_ctl_status2
.s
.pclk_run
= 1;
802 cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port
),
803 pescx_ctl_status2
.u64
);
805 * Now that we cleared PCLK_RUN, wait for it to be set
806 * again telling us the clock is running.
808 if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port
),
809 union cvmx_pescx_ctl_status2
,
810 pclk_run
, ==, 1, 10000)) {
811 cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n",
818 * Check and make sure PCIe came out of reset. If it doesn't
819 * the board probably hasn't wired the clocks up and the
820 * interface should be skipped.
822 pescx_ctl_status2
.u64
=
823 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port
));
824 if (pescx_ctl_status2
.s
.pcierst
) {
825 cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n",
831 * Check BIST2 status. If any bits are set skip this interface. This
832 * is an attempt to catch PCIE-813 on pass 1 parts.
834 pescx_bist_status2
.u64
=
835 cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port
));
836 if (pescx_bist_status2
.u64
) {
837 cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this "
838 "port isn't hooked up, skipping.\n",
843 /* Check BIST status */
844 pescx_bist_status
.u64
=
845 cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port
));
846 if (pescx_bist_status
.u64
)
847 cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
848 pcie_port
, CAST64(pescx_bist_status
.u64
));
850 /* Initialize the config space CSRs */
851 __cvmx_pcie_rc_initialize_config_space(pcie_port
);
853 /* Bring the link up */
854 if (__cvmx_pcie_rc_initialize_link(pcie_port
)) {
856 ("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n");
860 /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
861 npei_mem_access_ctl
.u64
= cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL
);
862 /* Allow 16 words to combine */
863 npei_mem_access_ctl
.s
.max_word
= 0;
864 /* Wait up to 127 cycles for more data */
865 npei_mem_access_ctl
.s
.timer
= 127;
866 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL
, npei_mem_access_ctl
.u64
);
868 /* Setup Mem access SubDIDs */
869 mem_access_subid
.u64
= 0;
870 /* Port the request is sent to. */
871 mem_access_subid
.s
.port
= pcie_port
;
872 /* Due to an errata on pass 1 chips, no merging is allowed. */
873 mem_access_subid
.s
.nmerge
= 1;
874 /* Endian-swap for Reads. */
875 mem_access_subid
.s
.esr
= 1;
876 /* Endian-swap for Writes. */
877 mem_access_subid
.s
.esw
= 1;
878 /* No Snoop for Reads. */
879 mem_access_subid
.s
.nsr
= 1;
880 /* No Snoop for Writes. */
881 mem_access_subid
.s
.nsw
= 1;
882 /* Disable Relaxed Ordering for Reads. */
883 mem_access_subid
.s
.ror
= 0;
884 /* Disable Relaxed Ordering for Writes. */
885 mem_access_subid
.s
.row
= 0;
886 /* PCIe Adddress Bits <63:34>. */
887 mem_access_subid
.s
.ba
= 0;
890 * Setup mem access 12-15 for port 0, 16-19 for port 1,
891 * supplying 36 bits of address space.
893 for (i
= 12 + pcie_port
* 4; i
< 16 + pcie_port
* 4; i
++) {
894 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i
),
895 mem_access_subid
.u64
);
896 /* Set each SUBID to extend the addressable range */
897 mem_access_subid
.s
.ba
+= 1;
901 * Disable the peer to peer forwarding register. This must be
902 * setup by the OS after it enumerates the bus and assigns
903 * addresses to the PCIe busses.
905 for (i
= 0; i
< 4; i
++) {
906 cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i
, pcie_port
), -1);
907 cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i
, pcie_port
), -1);
910 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
911 cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port
), 0);
913 /* BAR1 follows BAR2 with a gap. */
914 cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port
), CVMX_PCIE_BAR1_RC_BASE
);
917 bar1_index
.s
.addr_idx
= (CVMX_PCIE_BAR1_PHYS_BASE
>> 22);
918 bar1_index
.s
.ca
= 1; /* Not Cached */
919 bar1_index
.s
.end_swp
= 1; /* Endian Swap mode */
920 bar1_index
.s
.addr_v
= 1; /* Valid entry */
922 base
= pcie_port
? 16 : 0;
924 /* Big endian swizzle for 32-bit PEXP_NCB register. */
930 for (i
= 0; i
< 16; i
++) {
931 cvmx_write64_uint32((CVMX_PEXP_NPEI_BAR1_INDEXX(base
) ^ addr_swizzle
),
934 /* 256MB / 16 >> 22 == 4 */
935 bar1_index
.s
.addr_idx
+= (((1ull << 28) / 16ull) >> 22);
939 * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
940 * precedence where they overlap. It also overlaps with the
941 * device addresses, so make sure the peer to peer forwarding
944 cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port
), 0);
947 * Setup BAR2 attributes
949 * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
950 * - PTLP_RO,CTLP_RO should normally be set (except for debug).
951 * - WAIT_COM=0 will likely work for all applications.
953 * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]).
956 union cvmx_npei_ctl_port1 npei_ctl_port
;
957 npei_ctl_port
.u64
= cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1
);
958 npei_ctl_port
.s
.bar2_enb
= 1;
959 npei_ctl_port
.s
.bar2_esx
= 1;
960 npei_ctl_port
.s
.bar2_cax
= 0;
961 npei_ctl_port
.s
.ptlp_ro
= 1;
962 npei_ctl_port
.s
.ctlp_ro
= 1;
963 npei_ctl_port
.s
.wait_com
= 0;
964 npei_ctl_port
.s
.waitl_com
= 0;
965 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1
, npei_ctl_port
.u64
);
967 union cvmx_npei_ctl_port0 npei_ctl_port
;
968 npei_ctl_port
.u64
= cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0
);
969 npei_ctl_port
.s
.bar2_enb
= 1;
970 npei_ctl_port
.s
.bar2_esx
= 1;
971 npei_ctl_port
.s
.bar2_cax
= 0;
972 npei_ctl_port
.s
.ptlp_ro
= 1;
973 npei_ctl_port
.s
.ctlp_ro
= 1;
974 npei_ctl_port
.s
.wait_com
= 0;
975 npei_ctl_port
.s
.waitl_com
= 0;
976 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0
, npei_ctl_port
.u64
);
982 /* Above was cvmx-pcie.c, below original pcie.c */
986 * Map a PCI device to the appropriate interrupt line
988 * @dev: The Linux PCI device structure for the device to map
989 * @slot: The slot number for this device on __BUS 0__. Linux
990 * enumerates through all the bridges and figures out the
991 * slot on Bus 0 where this device eventually hooks to.
992 * @pin: The PCI interrupt pin read from the device, then swizzled
993 * as it goes through each bridge.
994 * Returns Interrupt number for the device
996 int __init
octeon_pcie_pcibios_map_irq(const struct pci_dev
*dev
,
1000 * The EBH5600 board with the PCI to PCIe bridge mistakenly
1001 * wires the first slot for both device id 2 and interrupt
1002 * A. According to the PCI spec, device id 2 should be C. The
1003 * following kludge attempts to fix this.
1005 if (strstr(octeon_board_type_string(), "EBH5600") &&
1006 dev
->bus
&& dev
->bus
->parent
) {
1008 * Iterate all the way up the device chain and find
1011 while (dev
->bus
&& dev
->bus
->parent
)
1012 dev
= to_pci_dev(dev
->bus
->bridge
);
1013 /* If the root bus is number 0 and the PEX 8114 is the
1014 * root, assume we are behind the miswired bus. We
1015 * need to correct the swizzle level by two. Yuck.
1017 if ((dev
->bus
->number
== 0) &&
1018 (dev
->vendor
== 0x10b5) && (dev
->device
== 0x8114)) {
1020 * The pin field is one based, not zero. We
1021 * need to swizzle it by minus two.
1023 pin
= ((pin
- 3) & 3) + 1;
1027 * The -1 is because pin starts with one, not zero. It might
1028 * be that this equation needs to include the slot number, but
1029 * I don't have hardware to check that against.
1031 return pin
- 1 + OCTEON_IRQ_PCI_INT0
;
1035 * Read a value from configuration space
1044 static inline int octeon_pcie_read_config(int pcie_port
, struct pci_bus
*bus
,
1045 unsigned int devfn
, int reg
, int size
,
1048 union octeon_cvmemctl cvmmemctl
;
1049 union octeon_cvmemctl cvmmemctl_save
;
1050 int bus_number
= bus
->number
;
1053 * For the top level bus make sure our hardware bus number
1054 * matches the software one.
1056 if (bus
->parent
== NULL
) {
1057 union cvmx_pciercx_cfg006 pciercx_cfg006
;
1058 pciercx_cfg006
.u32
= cvmx_pcie_cfgx_read(pcie_port
,
1059 CVMX_PCIERCX_CFG006(pcie_port
));
1060 if (pciercx_cfg006
.s
.pbnum
!= bus_number
) {
1061 pciercx_cfg006
.s
.pbnum
= bus_number
;
1062 pciercx_cfg006
.s
.sbnum
= bus_number
;
1063 pciercx_cfg006
.s
.subbnum
= bus_number
;
1064 cvmx_pcie_cfgx_write(pcie_port
,
1065 CVMX_PCIERCX_CFG006(pcie_port
),
1066 pciercx_cfg006
.u32
);
1071 * PCIe only has a single device connected to Octeon. It is
1072 * always device ID 0. Don't bother doing reads for other
1073 * device IDs on the first segment.
1075 if ((bus
->parent
== NULL
) && (devfn
>> 3 != 0))
1076 return PCIBIOS_FUNC_NOT_SUPPORTED
;
1078 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1
) ||
1079 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1
)) {
1081 * For our EBH5600 board, port 0 has a bridge with two
1082 * PCI-X slots. We need a new special checks to make
1083 * sure we only probe valid stuff. The PCIe->PCI-X
1084 * bridge only respondes to device ID 0, function
1087 if ((bus
->parent
== NULL
) && (devfn
>= 2))
1088 return PCIBIOS_FUNC_NOT_SUPPORTED
;
1090 * The PCI-X slots are device ID 2,3. Choose one of
1091 * the below "if" blocks based on what is plugged into
1094 /* Use this option if you aren't using either slot */
1095 if (bus_number
== 1)
1096 return PCIBIOS_FUNC_NOT_SUPPORTED
;
1099 * Shorten the DID timeout so bus errors for PCIe
1100 * config reads from non existent devices happen
1101 * faster. This allows us to continue booting even if
1102 * the above "if" checks are wrong. Once one of these
1103 * errors happens, the PCIe port is dead.
1105 cvmmemctl_save
.u64
= __read_64bit_c0_register($
11, 7);
1106 cvmmemctl
.u64
= cvmmemctl_save
.u64
;
1107 cvmmemctl
.s
.didtto
= 2;
1108 __write_64bit_c0_register($
11, 7, cvmmemctl
.u64
);
1113 *val
= cvmx_pcie_config_read32(pcie_port
, bus_number
,
1114 devfn
>> 3, devfn
& 0x7, reg
);
1117 *val
= cvmx_pcie_config_read16(pcie_port
, bus_number
,
1118 devfn
>> 3, devfn
& 0x7, reg
);
1121 *val
= cvmx_pcie_config_read8(pcie_port
, bus_number
, devfn
>> 3,
1125 return PCIBIOS_FUNC_NOT_SUPPORTED
;
1128 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1
) ||
1129 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1
))
1130 __write_64bit_c0_register($
11, 7, cvmmemctl_save
.u64
);
1131 return PCIBIOS_SUCCESSFUL
;
1134 static int octeon_pcie0_read_config(struct pci_bus
*bus
, unsigned int devfn
,
1135 int reg
, int size
, u32
*val
)
1137 return octeon_pcie_read_config(0, bus
, devfn
, reg
, size
, val
);
1140 static int octeon_pcie1_read_config(struct pci_bus
*bus
, unsigned int devfn
,
1141 int reg
, int size
, u32
*val
)
1143 return octeon_pcie_read_config(1, bus
, devfn
, reg
, size
, val
);
1149 * Write a value to PCI configuration space
1158 static inline int octeon_pcie_write_config(int pcie_port
, struct pci_bus
*bus
,
1159 unsigned int devfn
, int reg
,
1162 int bus_number
= bus
->number
;
1166 cvmx_pcie_config_write32(pcie_port
, bus_number
, devfn
>> 3,
1167 devfn
& 0x7, reg
, val
);
1168 return PCIBIOS_SUCCESSFUL
;
1170 cvmx_pcie_config_write16(pcie_port
, bus_number
, devfn
>> 3,
1171 devfn
& 0x7, reg
, val
);
1172 return PCIBIOS_SUCCESSFUL
;
1174 cvmx_pcie_config_write8(pcie_port
, bus_number
, devfn
>> 3,
1175 devfn
& 0x7, reg
, val
);
1176 return PCIBIOS_SUCCESSFUL
;
1178 #if PCI_CONFIG_SPACE_DELAY
1179 udelay(PCI_CONFIG_SPACE_DELAY
);
1181 return PCIBIOS_FUNC_NOT_SUPPORTED
;
1184 static int octeon_pcie0_write_config(struct pci_bus
*bus
, unsigned int devfn
,
1185 int reg
, int size
, u32 val
)
1187 return octeon_pcie_write_config(0, bus
, devfn
, reg
, size
, val
);
1190 static int octeon_pcie1_write_config(struct pci_bus
*bus
, unsigned int devfn
,
1191 int reg
, int size
, u32 val
)
1193 return octeon_pcie_write_config(1, bus
, devfn
, reg
, size
, val
);
1196 static struct pci_ops octeon_pcie0_ops
= {
1197 octeon_pcie0_read_config
,
1198 octeon_pcie0_write_config
,
1201 static struct resource octeon_pcie0_mem_resource
= {
1202 .name
= "Octeon PCIe0 MEM",
1203 .flags
= IORESOURCE_MEM
,
1206 static struct resource octeon_pcie0_io_resource
= {
1207 .name
= "Octeon PCIe0 IO",
1208 .flags
= IORESOURCE_IO
,
1211 static struct pci_controller octeon_pcie0_controller
= {
1212 .pci_ops
= &octeon_pcie0_ops
,
1213 .mem_resource
= &octeon_pcie0_mem_resource
,
1214 .io_resource
= &octeon_pcie0_io_resource
,
1217 static struct pci_ops octeon_pcie1_ops
= {
1218 octeon_pcie1_read_config
,
1219 octeon_pcie1_write_config
,
1222 static struct resource octeon_pcie1_mem_resource
= {
1223 .name
= "Octeon PCIe1 MEM",
1224 .flags
= IORESOURCE_MEM
,
1227 static struct resource octeon_pcie1_io_resource
= {
1228 .name
= "Octeon PCIe1 IO",
1229 .flags
= IORESOURCE_IO
,
1232 static struct pci_controller octeon_pcie1_controller
= {
1233 .pci_ops
= &octeon_pcie1_ops
,
1234 .mem_resource
= &octeon_pcie1_mem_resource
,
1235 .io_resource
= &octeon_pcie1_io_resource
,
1240 * Initialize the Octeon PCIe controllers
1244 static int __init
octeon_pcie_setup(void)
1246 union cvmx_npei_ctl_status npei_ctl_status
;
1249 /* These chips don't have PCIe */
1250 if (!octeon_has_feature(OCTEON_FEATURE_PCIE
))
1253 /* Point pcibios_map_irq() to the PCIe version of it */
1254 octeon_pcibios_map_irq
= octeon_pcie_pcibios_map_irq
;
1256 /* Use the PCIe based DMA mappings */
1257 octeon_dma_bar_type
= OCTEON_DMA_BAR_TYPE_PCIE
;
1260 * PCIe I/O range. It is based on port 0 but includes up until
1263 set_io_port_base(CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0)));
1264 ioport_resource
.start
= 0;
1265 ioport_resource
.end
=
1266 cvmx_pcie_get_io_base_address(1) -
1267 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
1269 npei_ctl_status
.u64
= cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS
);
1270 if (npei_ctl_status
.s
.host_mode
) {
1271 pr_notice("PCIe: Initializing port 0\n");
1272 result
= cvmx_pcie_rc_initialize(0);
1274 /* Memory offsets are physical addresses */
1275 octeon_pcie0_controller
.mem_offset
=
1276 cvmx_pcie_get_mem_base_address(0);
1277 /* IO offsets are Mips virtual addresses */
1278 octeon_pcie0_controller
.io_map_base
=
1279 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address
1281 octeon_pcie0_controller
.io_offset
= 0;
1283 * To keep things similar to PCI, we start
1284 * device addresses at the same place as PCI
1285 * uisng big bar support. This normally
1286 * translates to 4GB-256MB, which is the same
1289 octeon_pcie0_controller
.mem_resource
->start
=
1290 cvmx_pcie_get_mem_base_address(0) +
1291 (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE
<< 20);
1292 octeon_pcie0_controller
.mem_resource
->end
=
1293 cvmx_pcie_get_mem_base_address(0) +
1294 cvmx_pcie_get_mem_size(0) - 1;
1296 * Ports must be above 16KB for the ISA bus
1297 * filtering in the PCI-X to PCI bridge.
1299 octeon_pcie0_controller
.io_resource
->start
= 4 << 10;
1300 octeon_pcie0_controller
.io_resource
->end
=
1301 cvmx_pcie_get_io_size(0) - 1;
1302 register_pci_controller(&octeon_pcie0_controller
);
1305 pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
1308 /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
1309 if (OCTEON_IS_MODEL(OCTEON_CN52XX
)) {
1310 union cvmx_npei_dbg_data npei_dbg_data
;
1311 npei_dbg_data
.u64
= cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA
);
1312 if (npei_dbg_data
.cn52xx
.qlm0_link_width
)
1316 pr_notice("PCIe: Initializing port 1\n");
1317 result
= cvmx_pcie_rc_initialize(1);
1319 /* Memory offsets are physical addresses */
1320 octeon_pcie1_controller
.mem_offset
=
1321 cvmx_pcie_get_mem_base_address(1);
1322 /* IO offsets are Mips virtual addresses */
1323 octeon_pcie1_controller
.io_map_base
=
1324 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(1));
1325 octeon_pcie1_controller
.io_offset
=
1326 cvmx_pcie_get_io_base_address(1) -
1327 cvmx_pcie_get_io_base_address(0);
1329 * To keep things similar to PCI, we start device
1330 * addresses at the same place as PCI uisng big bar
1331 * support. This normally translates to 4GB-256MB,
1332 * which is the same as most x86 PCs.
1334 octeon_pcie1_controller
.mem_resource
->start
=
1335 cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
1336 (OCTEON_PCI_BAR1_HOLE_SIZE
<< 20);
1337 octeon_pcie1_controller
.mem_resource
->end
=
1338 cvmx_pcie_get_mem_base_address(1) +
1339 cvmx_pcie_get_mem_size(1) - 1;
1341 * Ports must be above 16KB for the ISA bus filtering
1342 * in the PCI-X to PCI bridge.
1344 octeon_pcie1_controller
.io_resource
->start
=
1345 cvmx_pcie_get_io_base_address(1) -
1346 cvmx_pcie_get_io_base_address(0);
1347 octeon_pcie1_controller
.io_resource
->end
=
1348 octeon_pcie1_controller
.io_resource
->start
+
1349 cvmx_pcie_get_io_size(1) - 1;
1350 register_pci_controller(&octeon_pcie1_controller
);
1355 arch_initcall(octeon_pcie_setup
);