release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/pci/pci.c

   1 /* Modified by Broadcom Corp. Portions Copyright (c) Broadcom Corp, 2011. */
   2 /*
   3  * This program is free software; you can redistribute  it and/or modify it
   4  * under  the terms of  the GNU General  Public License as published by the
   5  * Free Software Foundation;  either version 2 of the  License, or (at your
   6  * option) any later version.
   7  *
   8  * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
   9  */
  10 #include <linux/kernel.h>
  11 #include <linux/mm.h>
  12 #include <linux/bootmem.h>
  13 #include <linux/init.h>
  14 #include <linux/types.h>
  15 #include <linux/pci.h>
  16
  17
  18
  19 /*
  20  * Indicate whether we respect the PCI setup left by the firmware.
  21  *
  22  * Make this long-lived  so that we know when shutting down
  23  * whether we probed only or not.
  24  */
  25 int pci_probe_only;
  26
  27 #define PCI_ASSIGN_ALL_BUSSES   1
  28
  29 unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
  30
  31 /*
  32  * The PCI controller list.
  33  */
  34
  35 static struct pci_controller *hose_head, **hose_tail = &hose_head;
  36
  37 unsigned long PCIBIOS_MIN_IO;
  38 unsigned long PCIBIOS_MIN_MEM;
  39
  40 static int pci_initialized;
  41
  42 /*
  43  * We need to avoid collisions with `mirrored' VGA ports
  44  * and other strange ISA hardware, so we always want the
  45  * addresses to be allocated in the 0x000-0x0ff region
  46  * modulo 0x400.
  47  *
  48  * Why? Because some silly external IO cards only decode
  49  * the low 10 bits of the IO address. The 0x00-0xff region
  50  * is reserved for motherboard devices that decode all 16
  51  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  52  * but we want to try to avoid allocating at 0x2900-0x2bff
  53  * which might have be mirrored at 0x0100-0x03ff..
  54  */
  55 resource_size_t
  56 pcibios_align_resource(void *data, const struct resource *res,
  57                        resource_size_t size, resource_size_t align)
  58 {
  59         struct pci_dev *dev = data;
  60         struct pci_controller *hose = dev->sysdata;
  61         resource_size_t start = res->start;
  62
  63         if (res->flags & IORESOURCE_IO) {
  64                 /* Make sure we start at our min on all hoses */
  65                 if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
  66                         start = PCIBIOS_MIN_IO + hose->io_resource->start;
  67
  68                 /*
  69                  * Put everything into 0x00-0xff region modulo 0x400
  70                  */
  71                 if (start & 0x300)
  72                         start = (start + 0x3ff) & ~0x3ff;
  73         } else if (res->flags & IORESOURCE_MEM) {
  74                 /* Make sure we start at our min on all hoses */
  75                 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
  76                         start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
  77         }
  78
  79         return start;
  80 }
  81
  82 static void __devinit pcibios_scanbus(struct pci_controller *hose)
  83 {
  84         static int next_busno;
  85         static int need_domain_info;
  86         struct pci_bus *bus;
  87
  88         if (!hose->iommu)
  89                 PCI_DMA_BUS_IS_PHYS = 1;
  90
  91         if (hose->get_busno && pci_probe_only)
  92                 next_busno = (*hose->get_busno)();
  93
  94         bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
  95         hose->bus = bus;
  96
  97         need_domain_info = need_domain_info || hose->index;
  98         hose->need_domain_info = need_domain_info;
  99         if (bus) {
 100                 next_busno = bus->subordinate + 1;
 101                 /* Don't allow 8-bit bus number overflow inside the hose -
 102                    reserve some space for bridges. */
 103                 if (next_busno > 224) {
 104                         next_busno = 0;
 105                         need_domain_info = 1;
 106                 }
 107
 108                 if (!pci_probe_only) {
 109                         pci_bus_size_bridges(bus);
 110                         pci_bus_assign_resources(bus);
 111                         pci_enable_bridges(bus);
 112                 }
 113         }
 114 }
 115
 116 static DEFINE_MUTEX(pci_scan_mutex);
 117
 118 void __devinit register_pci_controller(struct pci_controller *hose)
 119 {
 120         if (request_resource(&iomem_resource, hose->mem_resource) < 0)
 121                 goto out;
 122         if (request_resource(&ioport_resource, hose->io_resource) < 0) {
 123                 release_resource(hose->mem_resource);
 124                 goto out;
 125         }
 126
 127         *hose_tail = hose;
 128         hose_tail = &hose->next;
 129
 130         /*
 131          * Do not panic here but later - this might hapen before console init.
 132          */
 133         if (!hose->io_map_base) {
 134                 printk(KERN_WARNING
 135                        "registering PCI controller with io_map_base unset\n");
 136         }
 137
 138         /*
 139          * Scan the bus if it is register after the PCI subsystem
 140          * initialization.
 141          */
 142         if (pci_initialized) {
 143                 mutex_lock(&pci_scan_mutex);
 144                 pcibios_scanbus(hose);
 145                 mutex_unlock(&pci_scan_mutex);
 146         }
 147
 148         return;
 149
 150 out:
 151         printk(KERN_WARNING
 152                "Skipping PCI bus scan due to resource conflict\n");
 153 }
 154
 155 extern int __init pcibios_init(void);
 156
 157 subsys_initcall(pcibios_init);
 158
 159
 160 /*
 161  *  If we set up a device for bus mastering, we need to check the latency
 162  *  timer as certain crappy BIOSes forget to set it properly.
 163  */
 164 static unsigned int pcibios_max_latency = 255;
 165
 166 void pcibios_set_master(struct pci_dev *dev)
 167 {
 168         u8 lat;
 169         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 170         if (lat < 16)
 171                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
 172         else if (lat > pcibios_max_latency)
 173                 lat = pcibios_max_latency;
 174         else
 175                 return;
 176         printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
 177                pci_name(dev), lat);
 178         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 179 }
 180
 181 unsigned int pcibios_assign_all_busses(void)
 182 {
 183         return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
 184 }
 185
 186
 187 void __init
 188 pcibios_update_irq(struct pci_dev *dev, int irq)
 189 {
 190         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 191 }
 192
 193 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 194                          struct resource *res)
 195 {
 196         struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
 197         unsigned long offset = 0;
 198
 199         if (res->flags & IORESOURCE_IO)
 200                 offset = hose->io_offset;
 201         else if (res->flags & IORESOURCE_MEM)
 202                 offset = hose->mem_offset;
 203
 204         region->start = res->start - offset;
 205         region->end = res->end - offset;
 206 }
 207
 208 void __devinit
 209 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 210                         struct pci_bus_region *region)
 211 {
 212         struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
 213         unsigned long offset = 0;
 214
 215         if (res->flags & IORESOURCE_IO)
 216                 offset = hose->io_offset;
 217         else if (res->flags & IORESOURCE_MEM)
 218                 offset = hose->mem_offset;
 219
 220         res->start = region->start + offset;
 221         res->end = region->end + offset;
 222 }
 223
 224 #ifdef CONFIG_HOTPLUG
 225 EXPORT_SYMBOL(pcibios_resource_to_bus);
 226 EXPORT_SYMBOL(pcibios_bus_to_resource);
 227 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
 228 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
 229 #endif
 230
 231 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 232                         enum pci_mmap_state mmap_state, int write_combine)
 233 {
 234         unsigned long prot;
 235
 236         /*
 237          * I/O space can be accessed via normal processor loads and stores on
 238          * this platform but for now we elect not to do this and portable
 239          * drivers should not do this anyway.
 240          */
 241         if (mmap_state == pci_mmap_io)
 242                 return -EINVAL;
 243
 244         /*
 245          * Ignore write-combine; for now only return uncached mappings.
 246          */
 247         prot = pgprot_val(vma->vm_page_prot);
 248         prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
 249         vma->vm_page_prot = __pgprot(prot);
 250
 251         return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 252                 vma->vm_end - vma->vm_start, vma->vm_page_prot);
 253 }
 254
 255 char * (*pcibios_plat_setup)(char *str) __devinitdata;