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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / mips / include / asm / octeon / cvmx-npi-defs.h
blob4e03cd8561e312e6a9ace37db08db04b448935a5
1 /***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28 #ifndef __CVMX_NPI_DEFS_H__
29 #define __CVMX_NPI_DEFS_H__
30
31 #define CVMX_NPI_BASE_ADDR_INPUT0 \
32 CVMX_ADD_IO_SEG(0x00011F0000000070ull)
33 #define CVMX_NPI_BASE_ADDR_INPUT1 \
34 CVMX_ADD_IO_SEG(0x00011F0000000080ull)
35 #define CVMX_NPI_BASE_ADDR_INPUT2 \
36 CVMX_ADD_IO_SEG(0x00011F0000000090ull)
37 #define CVMX_NPI_BASE_ADDR_INPUT3 \
38 CVMX_ADD_IO_SEG(0x00011F00000000A0ull)
39 #define CVMX_NPI_BASE_ADDR_INPUTX(offset) \
40 CVMX_ADD_IO_SEG(0x00011F0000000070ull + (((offset) & 3) * 16))
41 #define CVMX_NPI_BASE_ADDR_OUTPUT0 \
42 CVMX_ADD_IO_SEG(0x00011F00000000B8ull)
43 #define CVMX_NPI_BASE_ADDR_OUTPUT1 \
44 CVMX_ADD_IO_SEG(0x00011F00000000C0ull)
45 #define CVMX_NPI_BASE_ADDR_OUTPUT2 \
46 CVMX_ADD_IO_SEG(0x00011F00000000C8ull)
47 #define CVMX_NPI_BASE_ADDR_OUTPUT3 \
48 CVMX_ADD_IO_SEG(0x00011F00000000D0ull)
49 #define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) \
50 CVMX_ADD_IO_SEG(0x00011F00000000B8ull + (((offset) & 3) * 8))
51 #define CVMX_NPI_BIST_STATUS \
52 CVMX_ADD_IO_SEG(0x00011F00000003F8ull)
53 #define CVMX_NPI_BUFF_SIZE_OUTPUT0 \
54 CVMX_ADD_IO_SEG(0x00011F00000000E0ull)
55 #define CVMX_NPI_BUFF_SIZE_OUTPUT1 \
56 CVMX_ADD_IO_SEG(0x00011F00000000E8ull)
57 #define CVMX_NPI_BUFF_SIZE_OUTPUT2 \
58 CVMX_ADD_IO_SEG(0x00011F00000000F0ull)
59 #define CVMX_NPI_BUFF_SIZE_OUTPUT3 \
60 CVMX_ADD_IO_SEG(0x00011F00000000F8ull)
61 #define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) \
62 CVMX_ADD_IO_SEG(0x00011F00000000E0ull + (((offset) & 3) * 8))
63 #define CVMX_NPI_COMP_CTL \
64 CVMX_ADD_IO_SEG(0x00011F0000000218ull)
65 #define CVMX_NPI_CTL_STATUS \
66 CVMX_ADD_IO_SEG(0x00011F0000000010ull)
67 #define CVMX_NPI_DBG_SELECT \
68 CVMX_ADD_IO_SEG(0x00011F0000000008ull)
69 #define CVMX_NPI_DMA_CONTROL \
70 CVMX_ADD_IO_SEG(0x00011F0000000128ull)
71 #define CVMX_NPI_DMA_HIGHP_COUNTS \
72 CVMX_ADD_IO_SEG(0x00011F0000000148ull)
73 #define CVMX_NPI_DMA_HIGHP_NADDR \
74 CVMX_ADD_IO_SEG(0x00011F0000000158ull)
75 #define CVMX_NPI_DMA_LOWP_COUNTS \
76 CVMX_ADD_IO_SEG(0x00011F0000000140ull)
77 #define CVMX_NPI_DMA_LOWP_NADDR \
78 CVMX_ADD_IO_SEG(0x00011F0000000150ull)
79 #define CVMX_NPI_HIGHP_DBELL \
80 CVMX_ADD_IO_SEG(0x00011F0000000120ull)
81 #define CVMX_NPI_HIGHP_IBUFF_SADDR \
82 CVMX_ADD_IO_SEG(0x00011F0000000110ull)
83 #define CVMX_NPI_INPUT_CONTROL \
84 CVMX_ADD_IO_SEG(0x00011F0000000138ull)
85 #define CVMX_NPI_INT_ENB \
86 CVMX_ADD_IO_SEG(0x00011F0000000020ull)
87 #define CVMX_NPI_INT_SUM \
88 CVMX_ADD_IO_SEG(0x00011F0000000018ull)
89 #define CVMX_NPI_LOWP_DBELL \
90 CVMX_ADD_IO_SEG(0x00011F0000000118ull)
91 #define CVMX_NPI_LOWP_IBUFF_SADDR \
92 CVMX_ADD_IO_SEG(0x00011F0000000108ull)
93 #define CVMX_NPI_MEM_ACCESS_SUBID3 \
94 CVMX_ADD_IO_SEG(0x00011F0000000028ull)
95 #define CVMX_NPI_MEM_ACCESS_SUBID4 \
96 CVMX_ADD_IO_SEG(0x00011F0000000030ull)
97 #define CVMX_NPI_MEM_ACCESS_SUBID5 \
98 CVMX_ADD_IO_SEG(0x00011F0000000038ull)
99 #define CVMX_NPI_MEM_ACCESS_SUBID6 \
100 CVMX_ADD_IO_SEG(0x00011F0000000040ull)
101 #define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) \
102 CVMX_ADD_IO_SEG(0x00011F0000000028ull + (((offset) & 7) * 8) - 8 * 3)
103 #define CVMX_NPI_MSI_RCV \
104 (0x0000000000000190ull)
105 #define CVMX_NPI_NPI_MSI_RCV \
106 CVMX_ADD_IO_SEG(0x00011F0000001190ull)
107 #define CVMX_NPI_NUM_DESC_OUTPUT0 \
108 CVMX_ADD_IO_SEG(0x00011F0000000050ull)
109 #define CVMX_NPI_NUM_DESC_OUTPUT1 \
110 CVMX_ADD_IO_SEG(0x00011F0000000058ull)
111 #define CVMX_NPI_NUM_DESC_OUTPUT2 \
112 CVMX_ADD_IO_SEG(0x00011F0000000060ull)
113 #define CVMX_NPI_NUM_DESC_OUTPUT3 \
114 CVMX_ADD_IO_SEG(0x00011F0000000068ull)
115 #define CVMX_NPI_NUM_DESC_OUTPUTX(offset) \
116 CVMX_ADD_IO_SEG(0x00011F0000000050ull + (((offset) & 3) * 8))
117 #define CVMX_NPI_OUTPUT_CONTROL \
118 CVMX_ADD_IO_SEG(0x00011F0000000100ull)
119 #define CVMX_NPI_P0_DBPAIR_ADDR \
120 CVMX_ADD_IO_SEG(0x00011F0000000180ull)
121 #define CVMX_NPI_P0_INSTR_ADDR \
122 CVMX_ADD_IO_SEG(0x00011F00000001C0ull)
123 #define CVMX_NPI_P0_INSTR_CNTS \
124 CVMX_ADD_IO_SEG(0x00011F00000001A0ull)
125 #define CVMX_NPI_P0_PAIR_CNTS \
126 CVMX_ADD_IO_SEG(0x00011F0000000160ull)
127 #define CVMX_NPI_P1_DBPAIR_ADDR \
128 CVMX_ADD_IO_SEG(0x00011F0000000188ull)
129 #define CVMX_NPI_P1_INSTR_ADDR \
130 CVMX_ADD_IO_SEG(0x00011F00000001C8ull)
131 #define CVMX_NPI_P1_INSTR_CNTS \
132 CVMX_ADD_IO_SEG(0x00011F00000001A8ull)
133 #define CVMX_NPI_P1_PAIR_CNTS \
134 CVMX_ADD_IO_SEG(0x00011F0000000168ull)
135 #define CVMX_NPI_P2_DBPAIR_ADDR \
136 CVMX_ADD_IO_SEG(0x00011F0000000190ull)
137 #define CVMX_NPI_P2_INSTR_ADDR \
138 CVMX_ADD_IO_SEG(0x00011F00000001D0ull)
139 #define CVMX_NPI_P2_INSTR_CNTS \
140 CVMX_ADD_IO_SEG(0x00011F00000001B0ull)
141 #define CVMX_NPI_P2_PAIR_CNTS \
142 CVMX_ADD_IO_SEG(0x00011F0000000170ull)
143 #define CVMX_NPI_P3_DBPAIR_ADDR \
144 CVMX_ADD_IO_SEG(0x00011F0000000198ull)
145 #define CVMX_NPI_P3_INSTR_ADDR \
146 CVMX_ADD_IO_SEG(0x00011F00000001D8ull)
147 #define CVMX_NPI_P3_INSTR_CNTS \
148 CVMX_ADD_IO_SEG(0x00011F00000001B8ull)
149 #define CVMX_NPI_P3_PAIR_CNTS \
150 CVMX_ADD_IO_SEG(0x00011F0000000178ull)
151 #define CVMX_NPI_PCI_BAR1_INDEXX(offset) \
152 CVMX_ADD_IO_SEG(0x00011F0000001100ull + (((offset) & 31) * 4))
153 #define CVMX_NPI_PCI_BIST_REG \
154 CVMX_ADD_IO_SEG(0x00011F00000011C0ull)
155 #define CVMX_NPI_PCI_BURST_SIZE \
156 CVMX_ADD_IO_SEG(0x00011F00000000D8ull)
157 #define CVMX_NPI_PCI_CFG00 \
158 CVMX_ADD_IO_SEG(0x00011F0000001800ull)
159 #define CVMX_NPI_PCI_CFG01 \
160 CVMX_ADD_IO_SEG(0x00011F0000001804ull)
161 #define CVMX_NPI_PCI_CFG02 \
162 CVMX_ADD_IO_SEG(0x00011F0000001808ull)
163 #define CVMX_NPI_PCI_CFG03 \
164 CVMX_ADD_IO_SEG(0x00011F000000180Cull)
165 #define CVMX_NPI_PCI_CFG04 \
166 CVMX_ADD_IO_SEG(0x00011F0000001810ull)
167 #define CVMX_NPI_PCI_CFG05 \
168 CVMX_ADD_IO_SEG(0x00011F0000001814ull)
169 #define CVMX_NPI_PCI_CFG06 \
170 CVMX_ADD_IO_SEG(0x00011F0000001818ull)
171 #define CVMX_NPI_PCI_CFG07 \
172 CVMX_ADD_IO_SEG(0x00011F000000181Cull)
173 #define CVMX_NPI_PCI_CFG08 \
174 CVMX_ADD_IO_SEG(0x00011F0000001820ull)
175 #define CVMX_NPI_PCI_CFG09 \
176 CVMX_ADD_IO_SEG(0x00011F0000001824ull)
177 #define CVMX_NPI_PCI_CFG10 \
178 CVMX_ADD_IO_SEG(0x00011F0000001828ull)
179 #define CVMX_NPI_PCI_CFG11 \
180 CVMX_ADD_IO_SEG(0x00011F000000182Cull)
181 #define CVMX_NPI_PCI_CFG12 \
182 CVMX_ADD_IO_SEG(0x00011F0000001830ull)
183 #define CVMX_NPI_PCI_CFG13 \
184 CVMX_ADD_IO_SEG(0x00011F0000001834ull)
185 #define CVMX_NPI_PCI_CFG15 \
186 CVMX_ADD_IO_SEG(0x00011F000000183Cull)
187 #define CVMX_NPI_PCI_CFG16 \
188 CVMX_ADD_IO_SEG(0x00011F0000001840ull)
189 #define CVMX_NPI_PCI_CFG17 \
190 CVMX_ADD_IO_SEG(0x00011F0000001844ull)
191 #define CVMX_NPI_PCI_CFG18 \
192 CVMX_ADD_IO_SEG(0x00011F0000001848ull)
193 #define CVMX_NPI_PCI_CFG19 \
194 CVMX_ADD_IO_SEG(0x00011F000000184Cull)
195 #define CVMX_NPI_PCI_CFG20 \
196 CVMX_ADD_IO_SEG(0x00011F0000001850ull)
197 #define CVMX_NPI_PCI_CFG21 \
198 CVMX_ADD_IO_SEG(0x00011F0000001854ull)
199 #define CVMX_NPI_PCI_CFG22 \
200 CVMX_ADD_IO_SEG(0x00011F0000001858ull)
201 #define CVMX_NPI_PCI_CFG56 \
202 CVMX_ADD_IO_SEG(0x00011F00000018E0ull)
203 #define CVMX_NPI_PCI_CFG57 \
204 CVMX_ADD_IO_SEG(0x00011F00000018E4ull)
205 #define CVMX_NPI_PCI_CFG58 \
206 CVMX_ADD_IO_SEG(0x00011F00000018E8ull)
207 #define CVMX_NPI_PCI_CFG59 \
208 CVMX_ADD_IO_SEG(0x00011F00000018ECull)
209 #define CVMX_NPI_PCI_CFG60 \
210 CVMX_ADD_IO_SEG(0x00011F00000018F0ull)
211 #define CVMX_NPI_PCI_CFG61 \
212 CVMX_ADD_IO_SEG(0x00011F00000018F4ull)
213 #define CVMX_NPI_PCI_CFG62 \
214 CVMX_ADD_IO_SEG(0x00011F00000018F8ull)
215 #define CVMX_NPI_PCI_CFG63 \
216 CVMX_ADD_IO_SEG(0x00011F00000018FCull)
217 #define CVMX_NPI_PCI_CNT_REG \
218 CVMX_ADD_IO_SEG(0x00011F00000011B8ull)
219 #define CVMX_NPI_PCI_CTL_STATUS_2 \
220 CVMX_ADD_IO_SEG(0x00011F000000118Cull)
221 #define CVMX_NPI_PCI_INT_ARB_CFG \
222 CVMX_ADD_IO_SEG(0x00011F0000000130ull)
223 #define CVMX_NPI_PCI_INT_ENB2 \
224 CVMX_ADD_IO_SEG(0x00011F00000011A0ull)
225 #define CVMX_NPI_PCI_INT_SUM2 \
226 CVMX_ADD_IO_SEG(0x00011F0000001198ull)
227 #define CVMX_NPI_PCI_READ_CMD \
228 CVMX_ADD_IO_SEG(0x00011F0000000048ull)
229 #define CVMX_NPI_PCI_READ_CMD_6 \
230 CVMX_ADD_IO_SEG(0x00011F0000001180ull)
231 #define CVMX_NPI_PCI_READ_CMD_C \
232 CVMX_ADD_IO_SEG(0x00011F0000001184ull)
233 #define CVMX_NPI_PCI_READ_CMD_E \
234 CVMX_ADD_IO_SEG(0x00011F0000001188ull)
235 #define CVMX_NPI_PCI_SCM_REG \
236 CVMX_ADD_IO_SEG(0x00011F00000011A8ull)
237 #define CVMX_NPI_PCI_TSR_REG \
238 CVMX_ADD_IO_SEG(0x00011F00000011B0ull)
239 #define CVMX_NPI_PORT32_INSTR_HDR \
240 CVMX_ADD_IO_SEG(0x00011F00000001F8ull)
241 #define CVMX_NPI_PORT33_INSTR_HDR \
242 CVMX_ADD_IO_SEG(0x00011F0000000200ull)
243 #define CVMX_NPI_PORT34_INSTR_HDR \
244 CVMX_ADD_IO_SEG(0x00011F0000000208ull)
245 #define CVMX_NPI_PORT35_INSTR_HDR \
246 CVMX_ADD_IO_SEG(0x00011F0000000210ull)
247 #define CVMX_NPI_PORT_BP_CONTROL \
248 CVMX_ADD_IO_SEG(0x00011F00000001F0ull)
249 #define CVMX_NPI_PX_DBPAIR_ADDR(offset) \
250 CVMX_ADD_IO_SEG(0x00011F0000000180ull + (((offset) & 3) * 8))
251 #define CVMX_NPI_PX_INSTR_ADDR(offset) \
252 CVMX_ADD_IO_SEG(0x00011F00000001C0ull + (((offset) & 3) * 8))
253 #define CVMX_NPI_PX_INSTR_CNTS(offset) \
254 CVMX_ADD_IO_SEG(0x00011F00000001A0ull + (((offset) & 3) * 8))
255 #define CVMX_NPI_PX_PAIR_CNTS(offset) \
256 CVMX_ADD_IO_SEG(0x00011F0000000160ull + (((offset) & 3) * 8))
257 #define CVMX_NPI_RSL_INT_BLOCKS \
258 CVMX_ADD_IO_SEG(0x00011F0000000000ull)
259 #define CVMX_NPI_SIZE_INPUT0 \
260 CVMX_ADD_IO_SEG(0x00011F0000000078ull)
261 #define CVMX_NPI_SIZE_INPUT1 \
262 CVMX_ADD_IO_SEG(0x00011F0000000088ull)
263 #define CVMX_NPI_SIZE_INPUT2 \
264 CVMX_ADD_IO_SEG(0x00011F0000000098ull)
265 #define CVMX_NPI_SIZE_INPUT3 \
266 CVMX_ADD_IO_SEG(0x00011F00000000A8ull)
267 #define CVMX_NPI_SIZE_INPUTX(offset) \
268 CVMX_ADD_IO_SEG(0x00011F0000000078ull + (((offset) & 3) * 16))
269 #define CVMX_NPI_WIN_READ_TO \
270 CVMX_ADD_IO_SEG(0x00011F00000001E0ull)
271
272 union cvmx_npi_base_addr_inputx {
273 uint64_t u64;
274 struct cvmx_npi_base_addr_inputx_s {
275 uint64_t baddr:61;
276 uint64_t reserved_0_2:3;
277 } s;
278 struct cvmx_npi_base_addr_inputx_s cn30xx;
279 struct cvmx_npi_base_addr_inputx_s cn31xx;
280 struct cvmx_npi_base_addr_inputx_s cn38xx;
281 struct cvmx_npi_base_addr_inputx_s cn38xxp2;
282 struct cvmx_npi_base_addr_inputx_s cn50xx;
283 struct cvmx_npi_base_addr_inputx_s cn58xx;
284 struct cvmx_npi_base_addr_inputx_s cn58xxp1;
285 };
286
287 union cvmx_npi_base_addr_outputx {
288 uint64_t u64;
289 struct cvmx_npi_base_addr_outputx_s {
290 uint64_t baddr:61;
291 uint64_t reserved_0_2:3;
292 } s;
293 struct cvmx_npi_base_addr_outputx_s cn30xx;
294 struct cvmx_npi_base_addr_outputx_s cn31xx;
295 struct cvmx_npi_base_addr_outputx_s cn38xx;
296 struct cvmx_npi_base_addr_outputx_s cn38xxp2;
297 struct cvmx_npi_base_addr_outputx_s cn50xx;
298 struct cvmx_npi_base_addr_outputx_s cn58xx;
299 struct cvmx_npi_base_addr_outputx_s cn58xxp1;
300 };
301
302 union cvmx_npi_bist_status {
303 uint64_t u64;
304 struct cvmx_npi_bist_status_s {
305 uint64_t reserved_20_63:44;
306 uint64_t csr_bs:1;
307 uint64_t dif_bs:1;
308 uint64_t rdp_bs:1;
309 uint64_t pcnc_bs:1;
310 uint64_t pcn_bs:1;
311 uint64_t rdn_bs:1;
312 uint64_t pcac_bs:1;
313 uint64_t pcad_bs:1;
314 uint64_t rdnl_bs:1;
315 uint64_t pgf_bs:1;
316 uint64_t pig_bs:1;
317 uint64_t pof0_bs:1;
318 uint64_t pof1_bs:1;
319 uint64_t pof2_bs:1;
320 uint64_t pof3_bs:1;
321 uint64_t pos_bs:1;
322 uint64_t nus_bs:1;
323 uint64_t dob_bs:1;
324 uint64_t pdf_bs:1;
325 uint64_t dpi_bs:1;
326 } s;
327 struct cvmx_npi_bist_status_cn30xx {
328 uint64_t reserved_20_63:44;
329 uint64_t csr_bs:1;
330 uint64_t dif_bs:1;
331 uint64_t rdp_bs:1;
332 uint64_t pcnc_bs:1;
333 uint64_t pcn_bs:1;
334 uint64_t rdn_bs:1;
335 uint64_t pcac_bs:1;
336 uint64_t pcad_bs:1;
337 uint64_t rdnl_bs:1;
338 uint64_t pgf_bs:1;
339 uint64_t pig_bs:1;
340 uint64_t pof0_bs:1;
341 uint64_t reserved_5_7:3;
342 uint64_t pos_bs:1;
343 uint64_t nus_bs:1;
344 uint64_t dob_bs:1;
345 uint64_t pdf_bs:1;
346 uint64_t dpi_bs:1;
347 } cn30xx;
348 struct cvmx_npi_bist_status_s cn31xx;
349 struct cvmx_npi_bist_status_s cn38xx;
350 struct cvmx_npi_bist_status_s cn38xxp2;
351 struct cvmx_npi_bist_status_cn50xx {
352 uint64_t reserved_20_63:44;
353 uint64_t csr_bs:1;
354 uint64_t dif_bs:1;
355 uint64_t rdp_bs:1;
356 uint64_t pcnc_bs:1;
357 uint64_t pcn_bs:1;
358 uint64_t rdn_bs:1;
359 uint64_t pcac_bs:1;
360 uint64_t pcad_bs:1;
361 uint64_t rdnl_bs:1;
362 uint64_t pgf_bs:1;
363 uint64_t pig_bs:1;
364 uint64_t pof0_bs:1;
365 uint64_t pof1_bs:1;
366 uint64_t reserved_5_6:2;
367 uint64_t pos_bs:1;
368 uint64_t nus_bs:1;
369 uint64_t dob_bs:1;
370 uint64_t pdf_bs:1;
371 uint64_t dpi_bs:1;
372 } cn50xx;
373 struct cvmx_npi_bist_status_s cn58xx;
374 struct cvmx_npi_bist_status_s cn58xxp1;
375 };
376
377 union cvmx_npi_buff_size_outputx {
378 uint64_t u64;
379 struct cvmx_npi_buff_size_outputx_s {
380 uint64_t reserved_23_63:41;
381 uint64_t isize:7;
382 uint64_t bsize:16;
383 } s;
384 struct cvmx_npi_buff_size_outputx_s cn30xx;
385 struct cvmx_npi_buff_size_outputx_s cn31xx;
386 struct cvmx_npi_buff_size_outputx_s cn38xx;
387 struct cvmx_npi_buff_size_outputx_s cn38xxp2;
388 struct cvmx_npi_buff_size_outputx_s cn50xx;
389 struct cvmx_npi_buff_size_outputx_s cn58xx;
390 struct cvmx_npi_buff_size_outputx_s cn58xxp1;
391 };
392
393 union cvmx_npi_comp_ctl {
394 uint64_t u64;
395 struct cvmx_npi_comp_ctl_s {
396 uint64_t reserved_10_63:54;
397 uint64_t pctl:5;
398 uint64_t nctl:5;
399 } s;
400 struct cvmx_npi_comp_ctl_s cn50xx;
401 struct cvmx_npi_comp_ctl_s cn58xx;
402 struct cvmx_npi_comp_ctl_s cn58xxp1;
403 };
404
405 union cvmx_npi_ctl_status {
406 uint64_t u64;
407 struct cvmx_npi_ctl_status_s {
408 uint64_t reserved_63_63:1;
409 uint64_t chip_rev:8;
410 uint64_t dis_pniw:1;
411 uint64_t out3_enb:1;
412 uint64_t out2_enb:1;
413 uint64_t out1_enb:1;
414 uint64_t out0_enb:1;
415 uint64_t ins3_enb:1;
416 uint64_t ins2_enb:1;
417 uint64_t ins1_enb:1;
418 uint64_t ins0_enb:1;
419 uint64_t ins3_64b:1;
420 uint64_t ins2_64b:1;
421 uint64_t ins1_64b:1;
422 uint64_t ins0_64b:1;
423 uint64_t pci_wdis:1;
424 uint64_t wait_com:1;
425 uint64_t reserved_37_39:3;
426 uint64_t max_word:5;
427 uint64_t reserved_10_31:22;
428 uint64_t timer:10;
429 } s;
430 struct cvmx_npi_ctl_status_cn30xx {
431 uint64_t reserved_63_63:1;
432 uint64_t chip_rev:8;
433 uint64_t dis_pniw:1;
434 uint64_t reserved_51_53:3;
435 uint64_t out0_enb:1;
436 uint64_t reserved_47_49:3;
437 uint64_t ins0_enb:1;
438 uint64_t reserved_43_45:3;
439 uint64_t ins0_64b:1;
440 uint64_t pci_wdis:1;
441 uint64_t wait_com:1;
442 uint64_t reserved_37_39:3;
443 uint64_t max_word:5;
444 uint64_t reserved_10_31:22;
445 uint64_t timer:10;
446 } cn30xx;
447 struct cvmx_npi_ctl_status_cn31xx {
448 uint64_t reserved_63_63:1;
449 uint64_t chip_rev:8;
450 uint64_t dis_pniw:1;
451 uint64_t reserved_52_53:2;
452 uint64_t out1_enb:1;
453 uint64_t out0_enb:1;
454 uint64_t reserved_48_49:2;
455 uint64_t ins1_enb:1;
456 uint64_t ins0_enb:1;
457 uint64_t reserved_44_45:2;
458 uint64_t ins1_64b:1;
459 uint64_t ins0_64b:1;
460 uint64_t pci_wdis:1;
461 uint64_t wait_com:1;
462 uint64_t reserved_37_39:3;
463 uint64_t max_word:5;
464 uint64_t reserved_10_31:22;
465 uint64_t timer:10;
466 } cn31xx;
467 struct cvmx_npi_ctl_status_s cn38xx;
468 struct cvmx_npi_ctl_status_s cn38xxp2;
469 struct cvmx_npi_ctl_status_cn31xx cn50xx;
470 struct cvmx_npi_ctl_status_s cn58xx;
471 struct cvmx_npi_ctl_status_s cn58xxp1;
472 };
473
474 union cvmx_npi_dbg_select {
475 uint64_t u64;
476 struct cvmx_npi_dbg_select_s {
477 uint64_t reserved_16_63:48;
478 uint64_t dbg_sel:16;
479 } s;
480 struct cvmx_npi_dbg_select_s cn30xx;
481 struct cvmx_npi_dbg_select_s cn31xx;
482 struct cvmx_npi_dbg_select_s cn38xx;
483 struct cvmx_npi_dbg_select_s cn38xxp2;
484 struct cvmx_npi_dbg_select_s cn50xx;
485 struct cvmx_npi_dbg_select_s cn58xx;
486 struct cvmx_npi_dbg_select_s cn58xxp1;
487 };
488
489 union cvmx_npi_dma_control {
490 uint64_t u64;
491 struct cvmx_npi_dma_control_s {
492 uint64_t reserved_36_63:28;
493 uint64_t b0_lend:1;
494 uint64_t dwb_denb:1;
495 uint64_t dwb_ichk:9;
496 uint64_t fpa_que:3;
497 uint64_t o_add1:1;
498 uint64_t o_ro:1;
499 uint64_t o_ns:1;
500 uint64_t o_es:2;
501 uint64_t o_mode:1;
502 uint64_t hp_enb:1;
503 uint64_t lp_enb:1;
504 uint64_t csize:14;
505 } s;
506 struct cvmx_npi_dma_control_s cn30xx;
507 struct cvmx_npi_dma_control_s cn31xx;
508 struct cvmx_npi_dma_control_s cn38xx;
509 struct cvmx_npi_dma_control_s cn38xxp2;
510 struct cvmx_npi_dma_control_s cn50xx;
511 struct cvmx_npi_dma_control_s cn58xx;
512 struct cvmx_npi_dma_control_s cn58xxp1;
513 };
514
515 union cvmx_npi_dma_highp_counts {
516 uint64_t u64;
517 struct cvmx_npi_dma_highp_counts_s {
518 uint64_t reserved_39_63:25;
519 uint64_t fcnt:7;
520 uint64_t dbell:32;
521 } s;
522 struct cvmx_npi_dma_highp_counts_s cn30xx;
523 struct cvmx_npi_dma_highp_counts_s cn31xx;
524 struct cvmx_npi_dma_highp_counts_s cn38xx;
525 struct cvmx_npi_dma_highp_counts_s cn38xxp2;
526 struct cvmx_npi_dma_highp_counts_s cn50xx;
527 struct cvmx_npi_dma_highp_counts_s cn58xx;
528 struct cvmx_npi_dma_highp_counts_s cn58xxp1;
529 };
530
531 union cvmx_npi_dma_highp_naddr {
532 uint64_t u64;
533 struct cvmx_npi_dma_highp_naddr_s {
534 uint64_t reserved_40_63:24;
535 uint64_t state:4;
536 uint64_t addr:36;
537 } s;
538 struct cvmx_npi_dma_highp_naddr_s cn30xx;
539 struct cvmx_npi_dma_highp_naddr_s cn31xx;
540 struct cvmx_npi_dma_highp_naddr_s cn38xx;
541 struct cvmx_npi_dma_highp_naddr_s cn38xxp2;
542 struct cvmx_npi_dma_highp_naddr_s cn50xx;
543 struct cvmx_npi_dma_highp_naddr_s cn58xx;
544 struct cvmx_npi_dma_highp_naddr_s cn58xxp1;
545 };
546
547 union cvmx_npi_dma_lowp_counts {
548 uint64_t u64;
549 struct cvmx_npi_dma_lowp_counts_s {
550 uint64_t reserved_39_63:25;
551 uint64_t fcnt:7;
552 uint64_t dbell:32;
553 } s;
554 struct cvmx_npi_dma_lowp_counts_s cn30xx;
555 struct cvmx_npi_dma_lowp_counts_s cn31xx;
556 struct cvmx_npi_dma_lowp_counts_s cn38xx;
557 struct cvmx_npi_dma_lowp_counts_s cn38xxp2;
558 struct cvmx_npi_dma_lowp_counts_s cn50xx;
559 struct cvmx_npi_dma_lowp_counts_s cn58xx;
560 struct cvmx_npi_dma_lowp_counts_s cn58xxp1;
561 };
562
563 union cvmx_npi_dma_lowp_naddr {
564 uint64_t u64;
565 struct cvmx_npi_dma_lowp_naddr_s {
566 uint64_t reserved_40_63:24;
567 uint64_t state:4;
568 uint64_t addr:36;
569 } s;
570 struct cvmx_npi_dma_lowp_naddr_s cn30xx;
571 struct cvmx_npi_dma_lowp_naddr_s cn31xx;
572 struct cvmx_npi_dma_lowp_naddr_s cn38xx;
573 struct cvmx_npi_dma_lowp_naddr_s cn38xxp2;
574 struct cvmx_npi_dma_lowp_naddr_s cn50xx;
575 struct cvmx_npi_dma_lowp_naddr_s cn58xx;
576 struct cvmx_npi_dma_lowp_naddr_s cn58xxp1;
577 };
578
579 union cvmx_npi_highp_dbell {
580 uint64_t u64;
581 struct cvmx_npi_highp_dbell_s {
582 uint64_t reserved_16_63:48;
583 uint64_t dbell:16;
584 } s;
585 struct cvmx_npi_highp_dbell_s cn30xx;
586 struct cvmx_npi_highp_dbell_s cn31xx;
587 struct cvmx_npi_highp_dbell_s cn38xx;
588 struct cvmx_npi_highp_dbell_s cn38xxp2;
589 struct cvmx_npi_highp_dbell_s cn50xx;
590 struct cvmx_npi_highp_dbell_s cn58xx;
591 struct cvmx_npi_highp_dbell_s cn58xxp1;
592 };
593
594 union cvmx_npi_highp_ibuff_saddr {
595 uint64_t u64;
596 struct cvmx_npi_highp_ibuff_saddr_s {
597 uint64_t reserved_36_63:28;
598 uint64_t saddr:36;
599 } s;
600 struct cvmx_npi_highp_ibuff_saddr_s cn30xx;
601 struct cvmx_npi_highp_ibuff_saddr_s cn31xx;
602 struct cvmx_npi_highp_ibuff_saddr_s cn38xx;
603 struct cvmx_npi_highp_ibuff_saddr_s cn38xxp2;
604 struct cvmx_npi_highp_ibuff_saddr_s cn50xx;
605 struct cvmx_npi_highp_ibuff_saddr_s cn58xx;
606 struct cvmx_npi_highp_ibuff_saddr_s cn58xxp1;
607 };
608
609 union cvmx_npi_input_control {
610 uint64_t u64;
611 struct cvmx_npi_input_control_s {
612 uint64_t reserved_23_63:41;
613 uint64_t pkt_rr:1;
614 uint64_t pbp_dhi:13;
615 uint64_t d_nsr:1;
616 uint64_t d_esr:2;
617 uint64_t d_ror:1;
618 uint64_t use_csr:1;
619 uint64_t nsr:1;
620 uint64_t esr:2;
621 uint64_t ror:1;
622 } s;
623 struct cvmx_npi_input_control_cn30xx {
624 uint64_t reserved_22_63:42;
625 uint64_t pbp_dhi:13;
626 uint64_t d_nsr:1;
627 uint64_t d_esr:2;
628 uint64_t d_ror:1;
629 uint64_t use_csr:1;
630 uint64_t nsr:1;
631 uint64_t esr:2;
632 uint64_t ror:1;
633 } cn30xx;
634 struct cvmx_npi_input_control_cn30xx cn31xx;
635 struct cvmx_npi_input_control_s cn38xx;
636 struct cvmx_npi_input_control_cn30xx cn38xxp2;
637 struct cvmx_npi_input_control_s cn50xx;
638 struct cvmx_npi_input_control_s cn58xx;
639 struct cvmx_npi_input_control_s cn58xxp1;
640 };
641
642 union cvmx_npi_int_enb {
643 uint64_t u64;
644 struct cvmx_npi_int_enb_s {
645 uint64_t reserved_62_63:2;
646 uint64_t q1_a_f:1;
647 uint64_t q1_s_e:1;
648 uint64_t pdf_p_f:1;
649 uint64_t pdf_p_e:1;
650 uint64_t pcf_p_f:1;
651 uint64_t pcf_p_e:1;
652 uint64_t rdx_s_e:1;
653 uint64_t rwx_s_e:1;
654 uint64_t pnc_a_f:1;
655 uint64_t pnc_s_e:1;
656 uint64_t com_a_f:1;
657 uint64_t com_s_e:1;
658 uint64_t q3_a_f:1;
659 uint64_t q3_s_e:1;
660 uint64_t q2_a_f:1;
661 uint64_t q2_s_e:1;
662 uint64_t pcr_a_f:1;
663 uint64_t pcr_s_e:1;
664 uint64_t fcr_a_f:1;
665 uint64_t fcr_s_e:1;
666 uint64_t iobdma:1;
667 uint64_t p_dperr:1;
668 uint64_t win_rto:1;
669 uint64_t i3_pperr:1;
670 uint64_t i2_pperr:1;
671 uint64_t i1_pperr:1;
672 uint64_t i0_pperr:1;
673 uint64_t p3_ptout:1;
674 uint64_t p2_ptout:1;
675 uint64_t p1_ptout:1;
676 uint64_t p0_ptout:1;
677 uint64_t p3_pperr:1;
678 uint64_t p2_pperr:1;
679 uint64_t p1_pperr:1;
680 uint64_t p0_pperr:1;
681 uint64_t g3_rtout:1;
682 uint64_t g2_rtout:1;
683 uint64_t g1_rtout:1;
684 uint64_t g0_rtout:1;
685 uint64_t p3_perr:1;
686 uint64_t p2_perr:1;
687 uint64_t p1_perr:1;
688 uint64_t p0_perr:1;
689 uint64_t p3_rtout:1;
690 uint64_t p2_rtout:1;
691 uint64_t p1_rtout:1;
692 uint64_t p0_rtout:1;
693 uint64_t i3_overf:1;
694 uint64_t i2_overf:1;
695 uint64_t i1_overf:1;
696 uint64_t i0_overf:1;
697 uint64_t i3_rtout:1;
698 uint64_t i2_rtout:1;
699 uint64_t i1_rtout:1;
700 uint64_t i0_rtout:1;
701 uint64_t po3_2sml:1;
702 uint64_t po2_2sml:1;
703 uint64_t po1_2sml:1;
704 uint64_t po0_2sml:1;
705 uint64_t pci_rsl:1;
706 uint64_t rml_wto:1;
707 uint64_t rml_rto:1;
708 } s;
709 struct cvmx_npi_int_enb_cn30xx {
710 uint64_t reserved_62_63:2;
711 uint64_t q1_a_f:1;
712 uint64_t q1_s_e:1;
713 uint64_t pdf_p_f:1;
714 uint64_t pdf_p_e:1;
715 uint64_t pcf_p_f:1;
716 uint64_t pcf_p_e:1;
717 uint64_t rdx_s_e:1;
718 uint64_t rwx_s_e:1;
719 uint64_t pnc_a_f:1;
720 uint64_t pnc_s_e:1;
721 uint64_t com_a_f:1;
722 uint64_t com_s_e:1;
723 uint64_t q3_a_f:1;
724 uint64_t q3_s_e:1;
725 uint64_t q2_a_f:1;
726 uint64_t q2_s_e:1;
727 uint64_t pcr_a_f:1;
728 uint64_t pcr_s_e:1;
729 uint64_t fcr_a_f:1;
730 uint64_t fcr_s_e:1;
731 uint64_t iobdma:1;
732 uint64_t p_dperr:1;
733 uint64_t win_rto:1;
734 uint64_t reserved_36_38:3;
735 uint64_t i0_pperr:1;
736 uint64_t reserved_32_34:3;
737 uint64_t p0_ptout:1;
738 uint64_t reserved_28_30:3;
739 uint64_t p0_pperr:1;
740 uint64_t reserved_24_26:3;
741 uint64_t g0_rtout:1;
742 uint64_t reserved_20_22:3;
743 uint64_t p0_perr:1;
744 uint64_t reserved_16_18:3;
745 uint64_t p0_rtout:1;
746 uint64_t reserved_12_14:3;
747 uint64_t i0_overf:1;
748 uint64_t reserved_8_10:3;
749 uint64_t i0_rtout:1;
750 uint64_t reserved_4_6:3;
751 uint64_t po0_2sml:1;
752 uint64_t pci_rsl:1;
753 uint64_t rml_wto:1;
754 uint64_t rml_rto:1;
755 } cn30xx;
756 struct cvmx_npi_int_enb_cn31xx {
757 uint64_t reserved_62_63:2;
758 uint64_t q1_a_f:1;
759 uint64_t q1_s_e:1;
760 uint64_t pdf_p_f:1;
761 uint64_t pdf_p_e:1;
762 uint64_t pcf_p_f:1;
763 uint64_t pcf_p_e:1;
764 uint64_t rdx_s_e:1;
765 uint64_t rwx_s_e:1;
766 uint64_t pnc_a_f:1;
767 uint64_t pnc_s_e:1;
768 uint64_t com_a_f:1;
769 uint64_t com_s_e:1;
770 uint64_t q3_a_f:1;
771 uint64_t q3_s_e:1;
772 uint64_t q2_a_f:1;
773 uint64_t q2_s_e:1;
774 uint64_t pcr_a_f:1;
775 uint64_t pcr_s_e:1;
776 uint64_t fcr_a_f:1;
777 uint64_t fcr_s_e:1;
778 uint64_t iobdma:1;
779 uint64_t p_dperr:1;
780 uint64_t win_rto:1;
781 uint64_t reserved_37_38:2;
782 uint64_t i1_pperr:1;
783 uint64_t i0_pperr:1;
784 uint64_t reserved_33_34:2;
785 uint64_t p1_ptout:1;
786 uint64_t p0_ptout:1;
787 uint64_t reserved_29_30:2;
788 uint64_t p1_pperr:1;
789 uint64_t p0_pperr:1;
790 uint64_t reserved_25_26:2;
791 uint64_t g1_rtout:1;
792 uint64_t g0_rtout:1;
793 uint64_t reserved_21_22:2;
794 uint64_t p1_perr:1;
795 uint64_t p0_perr:1;
796 uint64_t reserved_17_18:2;
797 uint64_t p1_rtout:1;
798 uint64_t p0_rtout:1;
799 uint64_t reserved_13_14:2;
800 uint64_t i1_overf:1;
801 uint64_t i0_overf:1;
802 uint64_t reserved_9_10:2;
803 uint64_t i1_rtout:1;
804 uint64_t i0_rtout:1;
805 uint64_t reserved_5_6:2;
806 uint64_t po1_2sml:1;
807 uint64_t po0_2sml:1;
808 uint64_t pci_rsl:1;
809 uint64_t rml_wto:1;
810 uint64_t rml_rto:1;
811 } cn31xx;
812 struct cvmx_npi_int_enb_s cn38xx;
813 struct cvmx_npi_int_enb_cn38xxp2 {
814 uint64_t reserved_42_63:22;
815 uint64_t iobdma:1;
816 uint64_t p_dperr:1;
817 uint64_t win_rto:1;
818 uint64_t i3_pperr:1;
819 uint64_t i2_pperr:1;
820 uint64_t i1_pperr:1;
821 uint64_t i0_pperr:1;
822 uint64_t p3_ptout:1;
823 uint64_t p2_ptout:1;
824 uint64_t p1_ptout:1;
825 uint64_t p0_ptout:1;
826 uint64_t p3_pperr:1;
827 uint64_t p2_pperr:1;
828 uint64_t p1_pperr:1;
829 uint64_t p0_pperr:1;
830 uint64_t g3_rtout:1;
831 uint64_t g2_rtout:1;
832 uint64_t g1_rtout:1;
833 uint64_t g0_rtout:1;
834 uint64_t p3_perr:1;
835 uint64_t p2_perr:1;
836 uint64_t p1_perr:1;
837 uint64_t p0_perr:1;
838 uint64_t p3_rtout:1;
839 uint64_t p2_rtout:1;
840 uint64_t p1_rtout:1;
841 uint64_t p0_rtout:1;
842 uint64_t i3_overf:1;
843 uint64_t i2_overf:1;
844 uint64_t i1_overf:1;
845 uint64_t i0_overf:1;
846 uint64_t i3_rtout:1;
847 uint64_t i2_rtout:1;
848 uint64_t i1_rtout:1;
849 uint64_t i0_rtout:1;
850 uint64_t po3_2sml:1;
851 uint64_t po2_2sml:1;
852 uint64_t po1_2sml:1;
853 uint64_t po0_2sml:1;
854 uint64_t pci_rsl:1;
855 uint64_t rml_wto:1;
856 uint64_t rml_rto:1;
857 } cn38xxp2;
858 struct cvmx_npi_int_enb_cn31xx cn50xx;
859 struct cvmx_npi_int_enb_s cn58xx;
860 struct cvmx_npi_int_enb_s cn58xxp1;
861 };
862
863 union cvmx_npi_int_sum {
864 uint64_t u64;
865 struct cvmx_npi_int_sum_s {
866 uint64_t reserved_62_63:2;
867 uint64_t q1_a_f:1;
868 uint64_t q1_s_e:1;
869 uint64_t pdf_p_f:1;
870 uint64_t pdf_p_e:1;
871 uint64_t pcf_p_f:1;
872 uint64_t pcf_p_e:1;
873 uint64_t rdx_s_e:1;
874 uint64_t rwx_s_e:1;
875 uint64_t pnc_a_f:1;
876 uint64_t pnc_s_e:1;
877 uint64_t com_a_f:1;
878 uint64_t com_s_e:1;
879 uint64_t q3_a_f:1;
880 uint64_t q3_s_e:1;
881 uint64_t q2_a_f:1;
882 uint64_t q2_s_e:1;
883 uint64_t pcr_a_f:1;
884 uint64_t pcr_s_e:1;
885 uint64_t fcr_a_f:1;
886 uint64_t fcr_s_e:1;
887 uint64_t iobdma:1;
888 uint64_t p_dperr:1;
889 uint64_t win_rto:1;
890 uint64_t i3_pperr:1;
891 uint64_t i2_pperr:1;
892 uint64_t i1_pperr:1;
893 uint64_t i0_pperr:1;
894 uint64_t p3_ptout:1;
895 uint64_t p2_ptout:1;
896 uint64_t p1_ptout:1;
897 uint64_t p0_ptout:1;
898 uint64_t p3_pperr:1;
899 uint64_t p2_pperr:1;
900 uint64_t p1_pperr:1;
901 uint64_t p0_pperr:1;
902 uint64_t g3_rtout:1;
903 uint64_t g2_rtout:1;
904 uint64_t g1_rtout:1;
905 uint64_t g0_rtout:1;
906 uint64_t p3_perr:1;
907 uint64_t p2_perr:1;
908 uint64_t p1_perr:1;
909 uint64_t p0_perr:1;
910 uint64_t p3_rtout:1;
911 uint64_t p2_rtout:1;
912 uint64_t p1_rtout:1;
913 uint64_t p0_rtout:1;
914 uint64_t i3_overf:1;
915 uint64_t i2_overf:1;
916 uint64_t i1_overf:1;
917 uint64_t i0_overf:1;
918 uint64_t i3_rtout:1;
919 uint64_t i2_rtout:1;
920 uint64_t i1_rtout:1;
921 uint64_t i0_rtout:1;
922 uint64_t po3_2sml:1;
923 uint64_t po2_2sml:1;
924 uint64_t po1_2sml:1;
925 uint64_t po0_2sml:1;
926 uint64_t pci_rsl:1;
927 uint64_t rml_wto:1;
928 uint64_t rml_rto:1;
929 } s;
930 struct cvmx_npi_int_sum_cn30xx {
931 uint64_t reserved_62_63:2;
932 uint64_t q1_a_f:1;
933 uint64_t q1_s_e:1;
934 uint64_t pdf_p_f:1;
935 uint64_t pdf_p_e:1;
936 uint64_t pcf_p_f:1;
937 uint64_t pcf_p_e:1;
938 uint64_t rdx_s_e:1;
939 uint64_t rwx_s_e:1;
940 uint64_t pnc_a_f:1;
941 uint64_t pnc_s_e:1;
942 uint64_t com_a_f:1;
943 uint64_t com_s_e:1;
944 uint64_t q3_a_f:1;
945 uint64_t q3_s_e:1;
946 uint64_t q2_a_f:1;
947 uint64_t q2_s_e:1;
948 uint64_t pcr_a_f:1;
949 uint64_t pcr_s_e:1;
950 uint64_t fcr_a_f:1;
951 uint64_t fcr_s_e:1;
952 uint64_t iobdma:1;
953 uint64_t p_dperr:1;
954 uint64_t win_rto:1;
955 uint64_t reserved_36_38:3;
956 uint64_t i0_pperr:1;
957 uint64_t reserved_32_34:3;
958 uint64_t p0_ptout:1;
959 uint64_t reserved_28_30:3;
960 uint64_t p0_pperr:1;
961 uint64_t reserved_24_26:3;
962 uint64_t g0_rtout:1;
963 uint64_t reserved_20_22:3;
964 uint64_t p0_perr:1;
965 uint64_t reserved_16_18:3;
966 uint64_t p0_rtout:1;
967 uint64_t reserved_12_14:3;
968 uint64_t i0_overf:1;
969 uint64_t reserved_8_10:3;
970 uint64_t i0_rtout:1;
971 uint64_t reserved_4_6:3;
972 uint64_t po0_2sml:1;
973 uint64_t pci_rsl:1;
974 uint64_t rml_wto:1;
975 uint64_t rml_rto:1;
976 } cn30xx;
977 struct cvmx_npi_int_sum_cn31xx {
978 uint64_t reserved_62_63:2;
979 uint64_t q1_a_f:1;
980 uint64_t q1_s_e:1;
981 uint64_t pdf_p_f:1;
982 uint64_t pdf_p_e:1;
983 uint64_t pcf_p_f:1;
984 uint64_t pcf_p_e:1;
985 uint64_t rdx_s_e:1;
986 uint64_t rwx_s_e:1;
987 uint64_t pnc_a_f:1;
988 uint64_t pnc_s_e:1;
989 uint64_t com_a_f:1;
990 uint64_t com_s_e:1;
991 uint64_t q3_a_f:1;
992 uint64_t q3_s_e:1;
993 uint64_t q2_a_f:1;
994 uint64_t q2_s_e:1;
995 uint64_t pcr_a_f:1;
996 uint64_t pcr_s_e:1;
997 uint64_t fcr_a_f:1;
998 uint64_t fcr_s_e:1;
999 uint64_t iobdma:1;
1000 uint64_t p_dperr:1;
1001 uint64_t win_rto:1;
1002 uint64_t reserved_37_38:2;
1003 uint64_t i1_pperr:1;
1004 uint64_t i0_pperr:1;
1005 uint64_t reserved_33_34:2;
1006 uint64_t p1_ptout:1;
1007 uint64_t p0_ptout:1;
1008 uint64_t reserved_29_30:2;
1009 uint64_t p1_pperr:1;
1010 uint64_t p0_pperr:1;
1011 uint64_t reserved_25_26:2;
1012 uint64_t g1_rtout:1;
1013 uint64_t g0_rtout:1;
1014 uint64_t reserved_21_22:2;
1015 uint64_t p1_perr:1;
1016 uint64_t p0_perr:1;
1017 uint64_t reserved_17_18:2;
1018 uint64_t p1_rtout:1;
1019 uint64_t p0_rtout:1;
1020 uint64_t reserved_13_14:2;
1021 uint64_t i1_overf:1;
1022 uint64_t i0_overf:1;
1023 uint64_t reserved_9_10:2;
1024 uint64_t i1_rtout:1;
1025 uint64_t i0_rtout:1;
1026 uint64_t reserved_5_6:2;
1027 uint64_t po1_2sml:1;
1028 uint64_t po0_2sml:1;
1029 uint64_t pci_rsl:1;
1030 uint64_t rml_wto:1;
1031 uint64_t rml_rto:1;
1032 } cn31xx;
1033 struct cvmx_npi_int_sum_s cn38xx;
1034 struct cvmx_npi_int_sum_cn38xxp2 {
1035 uint64_t reserved_42_63:22;
1036 uint64_t iobdma:1;
1037 uint64_t p_dperr:1;
1038 uint64_t win_rto:1;
1039 uint64_t i3_pperr:1;
1040 uint64_t i2_pperr:1;
1041 uint64_t i1_pperr:1;
1042 uint64_t i0_pperr:1;
1043 uint64_t p3_ptout:1;
1044 uint64_t p2_ptout:1;
1045 uint64_t p1_ptout:1;
1046 uint64_t p0_ptout:1;
1047 uint64_t p3_pperr:1;
1048 uint64_t p2_pperr:1;
1049 uint64_t p1_pperr:1;
1050 uint64_t p0_pperr:1;
1051 uint64_t g3_rtout:1;
1052 uint64_t g2_rtout:1;
1053 uint64_t g1_rtout:1;
1054 uint64_t g0_rtout:1;
1055 uint64_t p3_perr:1;
1056 uint64_t p2_perr:1;
1057 uint64_t p1_perr:1;
1058 uint64_t p0_perr:1;
1059 uint64_t p3_rtout:1;
1060 uint64_t p2_rtout:1;
1061 uint64_t p1_rtout:1;
1062 uint64_t p0_rtout:1;
1063 uint64_t i3_overf:1;
1064 uint64_t i2_overf:1;
1065 uint64_t i1_overf:1;
1066 uint64_t i0_overf:1;
1067 uint64_t i3_rtout:1;
1068 uint64_t i2_rtout:1;
1069 uint64_t i1_rtout:1;
1070 uint64_t i0_rtout:1;
1071 uint64_t po3_2sml:1;
1072 uint64_t po2_2sml:1;
1073 uint64_t po1_2sml:1;
1074 uint64_t po0_2sml:1;
1075 uint64_t pci_rsl:1;
1076 uint64_t rml_wto:1;
1077 uint64_t rml_rto:1;
1078 } cn38xxp2;
1079 struct cvmx_npi_int_sum_cn31xx cn50xx;
1080 struct cvmx_npi_int_sum_s cn58xx;
1081 struct cvmx_npi_int_sum_s cn58xxp1;
1082 };
1083
1084 union cvmx_npi_lowp_dbell {
1085 uint64_t u64;
1086 struct cvmx_npi_lowp_dbell_s {
1087 uint64_t reserved_16_63:48;
1088 uint64_t dbell:16;
1089 } s;
1090 struct cvmx_npi_lowp_dbell_s cn30xx;
1091 struct cvmx_npi_lowp_dbell_s cn31xx;
1092 struct cvmx_npi_lowp_dbell_s cn38xx;
1093 struct cvmx_npi_lowp_dbell_s cn38xxp2;
1094 struct cvmx_npi_lowp_dbell_s cn50xx;
1095 struct cvmx_npi_lowp_dbell_s cn58xx;
1096 struct cvmx_npi_lowp_dbell_s cn58xxp1;
1097 };
1098
1099 union cvmx_npi_lowp_ibuff_saddr {
1100 uint64_t u64;
1101 struct cvmx_npi_lowp_ibuff_saddr_s {
1102 uint64_t reserved_36_63:28;
1103 uint64_t saddr:36;
1104 } s;
1105 struct cvmx_npi_lowp_ibuff_saddr_s cn30xx;
1106 struct cvmx_npi_lowp_ibuff_saddr_s cn31xx;
1107 struct cvmx_npi_lowp_ibuff_saddr_s cn38xx;
1108 struct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2;
1109 struct cvmx_npi_lowp_ibuff_saddr_s cn50xx;
1110 struct cvmx_npi_lowp_ibuff_saddr_s cn58xx;
1111 struct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1;
1112 };
1113
1114 union cvmx_npi_mem_access_subidx {
1115 uint64_t u64;
1116 struct cvmx_npi_mem_access_subidx_s {
1117 uint64_t reserved_38_63:26;
1118 uint64_t shortl:1;
1119 uint64_t nmerge:1;
1120 uint64_t esr:2;
1121 uint64_t esw:2;
1122 uint64_t nsr:1;
1123 uint64_t nsw:1;
1124 uint64_t ror:1;
1125 uint64_t row:1;
1126 uint64_t ba:28;
1127 } s;
1128 struct cvmx_npi_mem_access_subidx_s cn30xx;
1129 struct cvmx_npi_mem_access_subidx_cn31xx {
1130 uint64_t reserved_36_63:28;
1131 uint64_t esr:2;
1132 uint64_t esw:2;
1133 uint64_t nsr:1;
1134 uint64_t nsw:1;
1135 uint64_t ror:1;
1136 uint64_t row:1;
1137 uint64_t ba:28;
1138 } cn31xx;
1139 struct cvmx_npi_mem_access_subidx_s cn38xx;
1140 struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
1141 struct cvmx_npi_mem_access_subidx_s cn50xx;
1142 struct cvmx_npi_mem_access_subidx_s cn58xx;
1143 struct cvmx_npi_mem_access_subidx_s cn58xxp1;
1144 };
1145
1146 union cvmx_npi_msi_rcv {
1147 uint64_t u64;
1148 struct cvmx_npi_msi_rcv_s {
1149 uint64_t int_vec:64;
1150 } s;
1151 struct cvmx_npi_msi_rcv_s cn30xx;
1152 struct cvmx_npi_msi_rcv_s cn31xx;
1153 struct cvmx_npi_msi_rcv_s cn38xx;
1154 struct cvmx_npi_msi_rcv_s cn38xxp2;
1155 struct cvmx_npi_msi_rcv_s cn50xx;
1156 struct cvmx_npi_msi_rcv_s cn58xx;
1157 struct cvmx_npi_msi_rcv_s cn58xxp1;
1158 };
1159
1160 union cvmx_npi_num_desc_outputx {
1161 uint64_t u64;
1162 struct cvmx_npi_num_desc_outputx_s {
1163 uint64_t reserved_32_63:32;
1164 uint64_t size:32;
1165 } s;
1166 struct cvmx_npi_num_desc_outputx_s cn30xx;
1167 struct cvmx_npi_num_desc_outputx_s cn31xx;
1168 struct cvmx_npi_num_desc_outputx_s cn38xx;
1169 struct cvmx_npi_num_desc_outputx_s cn38xxp2;
1170 struct cvmx_npi_num_desc_outputx_s cn50xx;
1171 struct cvmx_npi_num_desc_outputx_s cn58xx;
1172 struct cvmx_npi_num_desc_outputx_s cn58xxp1;
1173 };
1174
1175 union cvmx_npi_output_control {
1176 uint64_t u64;
1177 struct cvmx_npi_output_control_s {
1178 uint64_t reserved_49_63:15;
1179 uint64_t pkt_rr:1;
1180 uint64_t p3_bmode:1;
1181 uint64_t p2_bmode:1;
1182 uint64_t p1_bmode:1;
1183 uint64_t p0_bmode:1;
1184 uint64_t o3_es:2;
1185 uint64_t o3_ns:1;
1186 uint64_t o3_ro:1;
1187 uint64_t o2_es:2;
1188 uint64_t o2_ns:1;
1189 uint64_t o2_ro:1;
1190 uint64_t o1_es:2;
1191 uint64_t o1_ns:1;
1192 uint64_t o1_ro:1;
1193 uint64_t o0_es:2;
1194 uint64_t o0_ns:1;
1195 uint64_t o0_ro:1;
1196 uint64_t o3_csrm:1;
1197 uint64_t o2_csrm:1;
1198 uint64_t o1_csrm:1;
1199 uint64_t o0_csrm:1;
1200 uint64_t reserved_20_23:4;
1201 uint64_t iptr_o3:1;
1202 uint64_t iptr_o2:1;
1203 uint64_t iptr_o1:1;
1204 uint64_t iptr_o0:1;
1205 uint64_t esr_sl3:2;
1206 uint64_t nsr_sl3:1;
1207 uint64_t ror_sl3:1;
1208 uint64_t esr_sl2:2;
1209 uint64_t nsr_sl2:1;
1210 uint64_t ror_sl2:1;
1211 uint64_t esr_sl1:2;
1212 uint64_t nsr_sl1:1;
1213 uint64_t ror_sl1:1;
1214 uint64_t esr_sl0:2;
1215 uint64_t nsr_sl0:1;
1216 uint64_t ror_sl0:1;
1217 } s;
1218 struct cvmx_npi_output_control_cn30xx {
1219 uint64_t reserved_45_63:19;
1220 uint64_t p0_bmode:1;
1221 uint64_t reserved_32_43:12;
1222 uint64_t o0_es:2;
1223 uint64_t o0_ns:1;
1224 uint64_t o0_ro:1;
1225 uint64_t reserved_25_27:3;
1226 uint64_t o0_csrm:1;
1227 uint64_t reserved_17_23:7;
1228 uint64_t iptr_o0:1;
1229 uint64_t reserved_4_15:12;
1230 uint64_t esr_sl0:2;
1231 uint64_t nsr_sl0:1;
1232 uint64_t ror_sl0:1;
1233 } cn30xx;
1234 struct cvmx_npi_output_control_cn31xx {
1235 uint64_t reserved_46_63:18;
1236 uint64_t p1_bmode:1;
1237 uint64_t p0_bmode:1;
1238 uint64_t reserved_36_43:8;
1239 uint64_t o1_es:2;
1240 uint64_t o1_ns:1;
1241 uint64_t o1_ro:1;
1242 uint64_t o0_es:2;
1243 uint64_t o0_ns:1;
1244 uint64_t o0_ro:1;
1245 uint64_t reserved_26_27:2;
1246 uint64_t o1_csrm:1;
1247 uint64_t o0_csrm:1;
1248 uint64_t reserved_18_23:6;
1249 uint64_t iptr_o1:1;
1250 uint64_t iptr_o0:1;
1251 uint64_t reserved_8_15:8;
1252 uint64_t esr_sl1:2;
1253 uint64_t nsr_sl1:1;
1254 uint64_t ror_sl1:1;
1255 uint64_t esr_sl0:2;
1256 uint64_t nsr_sl0:1;
1257 uint64_t ror_sl0:1;
1258 } cn31xx;
1259 struct cvmx_npi_output_control_s cn38xx;
1260 struct cvmx_npi_output_control_cn38xxp2 {
1261 uint64_t reserved_48_63:16;
1262 uint64_t p3_bmode:1;
1263 uint64_t p2_bmode:1;
1264 uint64_t p1_bmode:1;
1265 uint64_t p0_bmode:1;
1266 uint64_t o3_es:2;
1267 uint64_t o3_ns:1;
1268 uint64_t o3_ro:1;
1269 uint64_t o2_es:2;
1270 uint64_t o2_ns:1;
1271 uint64_t o2_ro:1;
1272 uint64_t o1_es:2;
1273 uint64_t o1_ns:1;
1274 uint64_t o1_ro:1;
1275 uint64_t o0_es:2;
1276 uint64_t o0_ns:1;
1277 uint64_t o0_ro:1;
1278 uint64_t o3_csrm:1;
1279 uint64_t o2_csrm:1;
1280 uint64_t o1_csrm:1;
1281 uint64_t o0_csrm:1;
1282 uint64_t reserved_20_23:4;
1283 uint64_t iptr_o3:1;
1284 uint64_t iptr_o2:1;
1285 uint64_t iptr_o1:1;
1286 uint64_t iptr_o0:1;
1287 uint64_t esr_sl3:2;
1288 uint64_t nsr_sl3:1;
1289 uint64_t ror_sl3:1;
1290 uint64_t esr_sl2:2;
1291 uint64_t nsr_sl2:1;
1292 uint64_t ror_sl2:1;
1293 uint64_t esr_sl1:2;
1294 uint64_t nsr_sl1:1;
1295 uint64_t ror_sl1:1;
1296 uint64_t esr_sl0:2;
1297 uint64_t nsr_sl0:1;
1298 uint64_t ror_sl0:1;
1299 } cn38xxp2;
1300 struct cvmx_npi_output_control_cn50xx {
1301 uint64_t reserved_49_63:15;
1302 uint64_t pkt_rr:1;
1303 uint64_t reserved_46_47:2;
1304 uint64_t p1_bmode:1;
1305 uint64_t p0_bmode:1;
1306 uint64_t reserved_36_43:8;
1307 uint64_t o1_es:2;
1308 uint64_t o1_ns:1;
1309 uint64_t o1_ro:1;
1310 uint64_t o0_es:2;
1311 uint64_t o0_ns:1;
1312 uint64_t o0_ro:1;
1313 uint64_t reserved_26_27:2;
1314 uint64_t o1_csrm:1;
1315 uint64_t o0_csrm:1;
1316 uint64_t reserved_18_23:6;
1317 uint64_t iptr_o1:1;
1318 uint64_t iptr_o0:1;
1319 uint64_t reserved_8_15:8;
1320 uint64_t esr_sl1:2;
1321 uint64_t nsr_sl1:1;
1322 uint64_t ror_sl1:1;
1323 uint64_t esr_sl0:2;
1324 uint64_t nsr_sl0:1;
1325 uint64_t ror_sl0:1;
1326 } cn50xx;
1327 struct cvmx_npi_output_control_s cn58xx;
1328 struct cvmx_npi_output_control_s cn58xxp1;
1329 };
1330
1331 union cvmx_npi_px_dbpair_addr {
1332 uint64_t u64;
1333 struct cvmx_npi_px_dbpair_addr_s {
1334 uint64_t reserved_63_63:1;
1335 uint64_t state:2;
1336 uint64_t naddr:61;
1337 } s;
1338 struct cvmx_npi_px_dbpair_addr_s cn30xx;
1339 struct cvmx_npi_px_dbpair_addr_s cn31xx;
1340 struct cvmx_npi_px_dbpair_addr_s cn38xx;
1341 struct cvmx_npi_px_dbpair_addr_s cn38xxp2;
1342 struct cvmx_npi_px_dbpair_addr_s cn50xx;
1343 struct cvmx_npi_px_dbpair_addr_s cn58xx;
1344 struct cvmx_npi_px_dbpair_addr_s cn58xxp1;
1345 };
1346
1347 union cvmx_npi_px_instr_addr {
1348 uint64_t u64;
1349 struct cvmx_npi_px_instr_addr_s {
1350 uint64_t state:3;
1351 uint64_t naddr:61;
1352 } s;
1353 struct cvmx_npi_px_instr_addr_s cn30xx;
1354 struct cvmx_npi_px_instr_addr_s cn31xx;
1355 struct cvmx_npi_px_instr_addr_s cn38xx;
1356 struct cvmx_npi_px_instr_addr_s cn38xxp2;
1357 struct cvmx_npi_px_instr_addr_s cn50xx;
1358 struct cvmx_npi_px_instr_addr_s cn58xx;
1359 struct cvmx_npi_px_instr_addr_s cn58xxp1;
1360 };
1361
1362 union cvmx_npi_px_instr_cnts {
1363 uint64_t u64;
1364 struct cvmx_npi_px_instr_cnts_s {
1365 uint64_t reserved_38_63:26;
1366 uint64_t fcnt:6;
1367 uint64_t avail:32;
1368 } s;
1369 struct cvmx_npi_px_instr_cnts_s cn30xx;
1370 struct cvmx_npi_px_instr_cnts_s cn31xx;
1371 struct cvmx_npi_px_instr_cnts_s cn38xx;
1372 struct cvmx_npi_px_instr_cnts_s cn38xxp2;
1373 struct cvmx_npi_px_instr_cnts_s cn50xx;
1374 struct cvmx_npi_px_instr_cnts_s cn58xx;
1375 struct cvmx_npi_px_instr_cnts_s cn58xxp1;
1376 };
1377
1378 union cvmx_npi_px_pair_cnts {
1379 uint64_t u64;
1380 struct cvmx_npi_px_pair_cnts_s {
1381 uint64_t reserved_37_63:27;
1382 uint64_t fcnt:5;
1383 uint64_t avail:32;
1384 } s;
1385 struct cvmx_npi_px_pair_cnts_s cn30xx;
1386 struct cvmx_npi_px_pair_cnts_s cn31xx;
1387 struct cvmx_npi_px_pair_cnts_s cn38xx;
1388 struct cvmx_npi_px_pair_cnts_s cn38xxp2;
1389 struct cvmx_npi_px_pair_cnts_s cn50xx;
1390 struct cvmx_npi_px_pair_cnts_s cn58xx;
1391 struct cvmx_npi_px_pair_cnts_s cn58xxp1;
1392 };
1393
1394 union cvmx_npi_pci_burst_size {
1395 uint64_t u64;
1396 struct cvmx_npi_pci_burst_size_s {
1397 uint64_t reserved_14_63:50;
1398 uint64_t wr_brst:7;
1399 uint64_t rd_brst:7;
1400 } s;
1401 struct cvmx_npi_pci_burst_size_s cn30xx;
1402 struct cvmx_npi_pci_burst_size_s cn31xx;
1403 struct cvmx_npi_pci_burst_size_s cn38xx;
1404 struct cvmx_npi_pci_burst_size_s cn38xxp2;
1405 struct cvmx_npi_pci_burst_size_s cn50xx;
1406 struct cvmx_npi_pci_burst_size_s cn58xx;
1407 struct cvmx_npi_pci_burst_size_s cn58xxp1;
1408 };
1409
1410 union cvmx_npi_pci_int_arb_cfg {
1411 uint64_t u64;
1412 struct cvmx_npi_pci_int_arb_cfg_s {
1413 uint64_t reserved_13_63:51;
1414 uint64_t hostmode:1;
1415 uint64_t pci_ovr:4;
1416 uint64_t reserved_5_7:3;
1417 uint64_t en:1;
1418 uint64_t park_mod:1;
1419 uint64_t park_dev:3;
1420 } s;
1421 struct cvmx_npi_pci_int_arb_cfg_cn30xx {
1422 uint64_t reserved_5_63:59;
1423 uint64_t en:1;
1424 uint64_t park_mod:1;
1425 uint64_t park_dev:3;
1426 } cn30xx;
1427 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
1428 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
1429 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
1430 struct cvmx_npi_pci_int_arb_cfg_s cn50xx;
1431 struct cvmx_npi_pci_int_arb_cfg_s cn58xx;
1432 struct cvmx_npi_pci_int_arb_cfg_s cn58xxp1;
1433 };
1434
1435 union cvmx_npi_pci_read_cmd {
1436 uint64_t u64;
1437 struct cvmx_npi_pci_read_cmd_s {
1438 uint64_t reserved_11_63:53;
1439 uint64_t cmd_size:11;
1440 } s;
1441 struct cvmx_npi_pci_read_cmd_s cn30xx;
1442 struct cvmx_npi_pci_read_cmd_s cn31xx;
1443 struct cvmx_npi_pci_read_cmd_s cn38xx;
1444 struct cvmx_npi_pci_read_cmd_s cn38xxp2;
1445 struct cvmx_npi_pci_read_cmd_s cn50xx;
1446 struct cvmx_npi_pci_read_cmd_s cn58xx;
1447 struct cvmx_npi_pci_read_cmd_s cn58xxp1;
1448 };
1449
1450 union cvmx_npi_port32_instr_hdr {
1451 uint64_t u64;
1452 struct cvmx_npi_port32_instr_hdr_s {
1453 uint64_t reserved_44_63:20;
1454 uint64_t pbp:1;
1455 uint64_t rsv_f:5;
1456 uint64_t rparmode:2;
1457 uint64_t rsv_e:1;
1458 uint64_t rskp_len:7;
1459 uint64_t rsv_d:6;
1460 uint64_t use_ihdr:1;
1461 uint64_t rsv_c:5;
1462 uint64_t par_mode:2;
1463 uint64_t rsv_b:1;
1464 uint64_t skp_len:7;
1465 uint64_t rsv_a:6;
1466 } s;
1467 struct cvmx_npi_port32_instr_hdr_s cn30xx;
1468 struct cvmx_npi_port32_instr_hdr_s cn31xx;
1469 struct cvmx_npi_port32_instr_hdr_s cn38xx;
1470 struct cvmx_npi_port32_instr_hdr_s cn38xxp2;
1471 struct cvmx_npi_port32_instr_hdr_s cn50xx;
1472 struct cvmx_npi_port32_instr_hdr_s cn58xx;
1473 struct cvmx_npi_port32_instr_hdr_s cn58xxp1;
1474 };
1475
1476 union cvmx_npi_port33_instr_hdr {
1477 uint64_t u64;
1478 struct cvmx_npi_port33_instr_hdr_s {
1479 uint64_t reserved_44_63:20;
1480 uint64_t pbp:1;
1481 uint64_t rsv_f:5;
1482 uint64_t rparmode:2;
1483 uint64_t rsv_e:1;
1484 uint64_t rskp_len:7;
1485 uint64_t rsv_d:6;
1486 uint64_t use_ihdr:1;
1487 uint64_t rsv_c:5;
1488 uint64_t par_mode:2;
1489 uint64_t rsv_b:1;
1490 uint64_t skp_len:7;
1491 uint64_t rsv_a:6;
1492 } s;
1493 struct cvmx_npi_port33_instr_hdr_s cn31xx;
1494 struct cvmx_npi_port33_instr_hdr_s cn38xx;
1495 struct cvmx_npi_port33_instr_hdr_s cn38xxp2;
1496 struct cvmx_npi_port33_instr_hdr_s cn50xx;
1497 struct cvmx_npi_port33_instr_hdr_s cn58xx;
1498 struct cvmx_npi_port33_instr_hdr_s cn58xxp1;
1499 };
1500
1501 union cvmx_npi_port34_instr_hdr {
1502 uint64_t u64;
1503 struct cvmx_npi_port34_instr_hdr_s {
1504 uint64_t reserved_44_63:20;
1505 uint64_t pbp:1;
1506 uint64_t rsv_f:5;
1507 uint64_t rparmode:2;
1508 uint64_t rsv_e:1;
1509 uint64_t rskp_len:7;
1510 uint64_t rsv_d:6;
1511 uint64_t use_ihdr:1;
1512 uint64_t rsv_c:5;
1513 uint64_t par_mode:2;
1514 uint64_t rsv_b:1;
1515 uint64_t skp_len:7;
1516 uint64_t rsv_a:6;
1517 } s;
1518 struct cvmx_npi_port34_instr_hdr_s cn38xx;
1519 struct cvmx_npi_port34_instr_hdr_s cn38xxp2;
1520 struct cvmx_npi_port34_instr_hdr_s cn58xx;
1521 struct cvmx_npi_port34_instr_hdr_s cn58xxp1;
1522 };
1523
1524 union cvmx_npi_port35_instr_hdr {
1525 uint64_t u64;
1526 struct cvmx_npi_port35_instr_hdr_s {
1527 uint64_t reserved_44_63:20;
1528 uint64_t pbp:1;
1529 uint64_t rsv_f:5;
1530 uint64_t rparmode:2;
1531 uint64_t rsv_e:1;
1532 uint64_t rskp_len:7;
1533 uint64_t rsv_d:6;
1534 uint64_t use_ihdr:1;
1535 uint64_t rsv_c:5;
1536 uint64_t par_mode:2;
1537 uint64_t rsv_b:1;
1538 uint64_t skp_len:7;
1539 uint64_t rsv_a:6;
1540 } s;
1541 struct cvmx_npi_port35_instr_hdr_s cn38xx;
1542 struct cvmx_npi_port35_instr_hdr_s cn38xxp2;
1543 struct cvmx_npi_port35_instr_hdr_s cn58xx;
1544 struct cvmx_npi_port35_instr_hdr_s cn58xxp1;
1545 };
1546
1547 union cvmx_npi_port_bp_control {
1548 uint64_t u64;
1549 struct cvmx_npi_port_bp_control_s {
1550 uint64_t reserved_8_63:56;
1551 uint64_t bp_on:4;
1552 uint64_t enb:4;
1553 } s;
1554 struct cvmx_npi_port_bp_control_s cn30xx;
1555 struct cvmx_npi_port_bp_control_s cn31xx;
1556 struct cvmx_npi_port_bp_control_s cn38xx;
1557 struct cvmx_npi_port_bp_control_s cn38xxp2;
1558 struct cvmx_npi_port_bp_control_s cn50xx;
1559 struct cvmx_npi_port_bp_control_s cn58xx;
1560 struct cvmx_npi_port_bp_control_s cn58xxp1;
1561 };
1562
1563 union cvmx_npi_rsl_int_blocks {
1564 uint64_t u64;
1565 struct cvmx_npi_rsl_int_blocks_s {
1566 uint64_t reserved_32_63:32;
1567 uint64_t rint_31:1;
1568 uint64_t iob:1;
1569 uint64_t reserved_28_29:2;
1570 uint64_t rint_27:1;
1571 uint64_t rint_26:1;
1572 uint64_t rint_25:1;
1573 uint64_t rint_24:1;
1574 uint64_t asx1:1;
1575 uint64_t asx0:1;
1576 uint64_t rint_21:1;
1577 uint64_t pip:1;
1578 uint64_t spx1:1;
1579 uint64_t spx0:1;
1580 uint64_t lmc:1;
1581 uint64_t l2c:1;
1582 uint64_t rint_15:1;
1583 uint64_t reserved_13_14:2;
1584 uint64_t pow:1;
1585 uint64_t tim:1;
1586 uint64_t pko:1;
1587 uint64_t ipd:1;
1588 uint64_t rint_8:1;
1589 uint64_t zip:1;
1590 uint64_t dfa:1;
1591 uint64_t fpa:1;
1592 uint64_t key:1;
1593 uint64_t npi:1;
1594 uint64_t gmx1:1;
1595 uint64_t gmx0:1;
1596 uint64_t mio:1;
1597 } s;
1598 struct cvmx_npi_rsl_int_blocks_cn30xx {
1599 uint64_t reserved_32_63:32;
1600 uint64_t rint_31:1;
1601 uint64_t iob:1;
1602 uint64_t rint_29:1;
1603 uint64_t rint_28:1;
1604 uint64_t rint_27:1;
1605 uint64_t rint_26:1;
1606 uint64_t rint_25:1;
1607 uint64_t rint_24:1;
1608 uint64_t asx1:1;
1609 uint64_t asx0:1;
1610 uint64_t rint_21:1;
1611 uint64_t pip:1;
1612 uint64_t spx1:1;
1613 uint64_t spx0:1;
1614 uint64_t lmc:1;
1615 uint64_t l2c:1;
1616 uint64_t rint_15:1;
1617 uint64_t rint_14:1;
1618 uint64_t usb:1;
1619 uint64_t pow:1;
1620 uint64_t tim:1;
1621 uint64_t pko:1;
1622 uint64_t ipd:1;
1623 uint64_t rint_8:1;
1624 uint64_t zip:1;
1625 uint64_t dfa:1;
1626 uint64_t fpa:1;
1627 uint64_t key:1;
1628 uint64_t npi:1;
1629 uint64_t gmx1:1;
1630 uint64_t gmx0:1;
1631 uint64_t mio:1;
1632 } cn30xx;
1633 struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
1634 struct cvmx_npi_rsl_int_blocks_cn38xx {
1635 uint64_t reserved_32_63:32;
1636 uint64_t rint_31:1;
1637 uint64_t iob:1;
1638 uint64_t rint_29:1;
1639 uint64_t rint_28:1;
1640 uint64_t rint_27:1;
1641 uint64_t rint_26:1;
1642 uint64_t rint_25:1;
1643 uint64_t rint_24:1;
1644 uint64_t asx1:1;
1645 uint64_t asx0:1;
1646 uint64_t rint_21:1;
1647 uint64_t pip:1;
1648 uint64_t spx1:1;
1649 uint64_t spx0:1;
1650 uint64_t lmc:1;
1651 uint64_t l2c:1;
1652 uint64_t rint_15:1;
1653 uint64_t rint_14:1;
1654 uint64_t rint_13:1;
1655 uint64_t pow:1;
1656 uint64_t tim:1;
1657 uint64_t pko:1;
1658 uint64_t ipd:1;
1659 uint64_t rint_8:1;
1660 uint64_t zip:1;
1661 uint64_t dfa:1;
1662 uint64_t fpa:1;
1663 uint64_t key:1;
1664 uint64_t npi:1;
1665 uint64_t gmx1:1;
1666 uint64_t gmx0:1;
1667 uint64_t mio:1;
1668 } cn38xx;
1669 struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
1670 struct cvmx_npi_rsl_int_blocks_cn50xx {
1671 uint64_t reserved_31_63:33;
1672 uint64_t iob:1;
1673 uint64_t lmc1:1;
1674 uint64_t agl:1;
1675 uint64_t reserved_24_27:4;
1676 uint64_t asx1:1;
1677 uint64_t asx0:1;
1678 uint64_t reserved_21_21:1;
1679 uint64_t pip:1;
1680 uint64_t spx1:1;
1681 uint64_t spx0:1;
1682 uint64_t lmc:1;
1683 uint64_t l2c:1;
1684 uint64_t reserved_15_15:1;
1685 uint64_t rad:1;
1686 uint64_t usb:1;
1687 uint64_t pow:1;
1688 uint64_t tim:1;
1689 uint64_t pko:1;
1690 uint64_t ipd:1;
1691 uint64_t reserved_8_8:1;
1692 uint64_t zip:1;
1693 uint64_t dfa:1;
1694 uint64_t fpa:1;
1695 uint64_t key:1;
1696 uint64_t npi:1;
1697 uint64_t gmx1:1;
1698 uint64_t gmx0:1;
1699 uint64_t mio:1;
1700 } cn50xx;
1701 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
1702 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
1703 };
1704
1705 union cvmx_npi_size_inputx {
1706 uint64_t u64;
1707 struct cvmx_npi_size_inputx_s {
1708 uint64_t reserved_32_63:32;
1709 uint64_t size:32;
1710 } s;
1711 struct cvmx_npi_size_inputx_s cn30xx;
1712 struct cvmx_npi_size_inputx_s cn31xx;
1713 struct cvmx_npi_size_inputx_s cn38xx;
1714 struct cvmx_npi_size_inputx_s cn38xxp2;
1715 struct cvmx_npi_size_inputx_s cn50xx;
1716 struct cvmx_npi_size_inputx_s cn58xx;
1717 struct cvmx_npi_size_inputx_s cn58xxp1;
1718 };
1719
1720 union cvmx_npi_win_read_to {
1721 uint64_t u64;
1722 struct cvmx_npi_win_read_to_s {
1723 uint64_t reserved_32_63:32;
1724 uint64_t time:32;
1725 } s;
1726 struct cvmx_npi_win_read_to_s cn30xx;
1727 struct cvmx_npi_win_read_to_s cn31xx;
1728 struct cvmx_npi_win_read_to_s cn38xx;
1729 struct cvmx_npi_win_read_to_s cn38xxp2;
1730 struct cvmx_npi_win_read_to_s cn50xx;
1731 struct cvmx_npi_win_read_to_s cn58xx;
1732 struct cvmx_npi_win_read_to_s cn58xxp1;
1733 };
1734
1735 #endif
Tomato firmware and modifications.