release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/inst.h

   1 /*
   2  * Format of an instruction in memory.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1996, 2000 by Ralf Baechle
   9  * Copyright (C) 2006 by Thiemo Seufer
  10  */
  11 #ifndef _ASM_INST_H
  12 #define _ASM_INST_H
  13
  14 /*
  15  * Major opcodes; before MIPS IV cop1x was called cop3.
  16  */
  17 enum major_op {
  18         spec_op, bcond_op, j_op, jal_op,
  19         beq_op, bne_op, blez_op, bgtz_op,
  20         addi_op, addiu_op, slti_op, sltiu_op,
  21         andi_op, ori_op, xori_op, lui_op,
  22         cop0_op, cop1_op, cop2_op, cop1x_op,
  23         beql_op, bnel_op, blezl_op, bgtzl_op,
  24         daddi_op, daddiu_op, ldl_op, ldr_op,
  25         spec2_op, jalx_op, mdmx_op, spec3_op,
  26         lb_op, lh_op, lwl_op, lw_op,
  27         lbu_op, lhu_op, lwr_op, lwu_op,
  28         sb_op, sh_op, swl_op, sw_op,
  29         sdl_op, sdr_op, swr_op, cache_op,
  30         ll_op, lwc1_op, lwc2_op, pref_op,
  31         lld_op, ldc1_op, ldc2_op, ld_op,
  32         sc_op, swc1_op, swc2_op, major_3b_op,
  33         scd_op, sdc1_op, sdc2_op, sd_op
  34 };
  35
  36 /*
  37  * func field of spec opcode.
  38  */
  39 enum spec_op {
  40         sll_op, movc_op, srl_op, sra_op,
  41         sllv_op, pmon_op, srlv_op, srav_op,
  42         jr_op, jalr_op, movz_op, movn_op,
  43         syscall_op, break_op, spim_op, sync_op,
  44         mfhi_op, mthi_op, mflo_op, mtlo_op,
  45         dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
  46         mult_op, multu_op, div_op, divu_op,
  47         dmult_op, dmultu_op, ddiv_op, ddivu_op,
  48         add_op, addu_op, sub_op, subu_op,
  49         and_op, or_op, xor_op, nor_op,
  50         spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
  51         dadd_op, daddu_op, dsub_op, dsubu_op,
  52         tge_op, tgeu_op, tlt_op, tltu_op,
  53         teq_op, spec5_unused_op, tne_op, spec6_unused_op,
  54         dsll_op, spec7_unused_op, dsrl_op, dsra_op,
  55         dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
  56 };
  57
  58 /*
  59  * func field of spec2 opcode.
  60  */
  61 enum spec2_op {
  62         madd_op, maddu_op, mul_op, spec2_3_unused_op,
  63         msub_op, msubu_op, /* more unused ops */
  64         clz_op = 0x20, clo_op,
  65         dclz_op = 0x24, dclo_op,
  66         sdbpp_op = 0x3f
  67 };
  68
  69 /*
  70  * func field of spec3 opcode.
  71  */
  72 enum spec3_op {
  73         ext_op, dextm_op, dextu_op, dext_op,
  74         ins_op, dinsm_op, dinsu_op, dins_op,
  75         lx_op = 0x0a,
  76         bshfl_op = 0x20,
  77         dbshfl_op = 0x24,
  78         rdhwr_op = 0x3b
  79 };
  80
  81 /*
  82  * rt field of bcond opcodes.
  83  */
  84 enum rt_op {
  85         bltz_op, bgez_op, bltzl_op, bgezl_op,
  86         spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
  87         tgei_op, tgeiu_op, tlti_op, tltiu_op,
  88         teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
  89         bltzal_op, bgezal_op, bltzall_op, bgezall_op,
  90         rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
  91         rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
  92         bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
  93 };
  94
  95 /*
  96  * rs field of cop opcodes.
  97  */
  98 enum cop_op {
  99         mfc_op        = 0x00, dmfc_op       = 0x01,
 100         cfc_op        = 0x02, mtc_op        = 0x04,
 101         dmtc_op       = 0x05, ctc_op        = 0x06,
 102         bc_op         = 0x08, cop_op        = 0x10,
 103         copm_op       = 0x18
 104 };
 105
 106 /*
 107  * rt field of cop.bc_op opcodes
 108  */
 109 enum bcop_op {
 110         bcf_op, bct_op, bcfl_op, bctl_op
 111 };
 112
 113 /*
 114  * func field of cop0 coi opcodes.
 115  */
 116 enum cop0_coi_func {
 117         tlbr_op       = 0x01, tlbwi_op      = 0x02,
 118         tlbwr_op      = 0x06, tlbp_op       = 0x08,
 119         rfe_op        = 0x10, eret_op       = 0x18,
 120         iret_op       = 0x38
 121 };
 122
 123 /*
 124  * func field of cop0 com opcodes.
 125  */
 126 enum cop0_com_func {
 127         tlbr1_op      = 0x01, tlbw_op       = 0x02,
 128         tlbp1_op      = 0x08, dctr_op       = 0x09,
 129         dctw_op       = 0x0a
 130 };
 131
 132 /*
 133  * fmt field of cop1 opcodes.
 134  */
 135 enum cop1_fmt {
 136         s_fmt, d_fmt, e_fmt, q_fmt,
 137         w_fmt, l_fmt
 138 };
 139
 140 /*
 141  * func field of cop1 instructions using d, s or w format.
 142  */
 143 enum cop1_sdw_func {
 144         fadd_op      =  0x00, fsub_op      =  0x01,
 145         fmul_op      =  0x02, fdiv_op      =  0x03,
 146         fsqrt_op     =  0x04, fabs_op      =  0x05,
 147         fmov_op      =  0x06, fneg_op      =  0x07,
 148         froundl_op   =  0x08, ftruncl_op   =  0x09,
 149         fceill_op    =  0x0a, ffloorl_op   =  0x0b,
 150         fround_op    =  0x0c, ftrunc_op    =  0x0d,
 151         fceil_op     =  0x0e, ffloor_op    =  0x0f,
 152         fmovc_op     =  0x11, fmovz_op     =  0x12,
 153         fmovn_op     =  0x13, frecip_op    =  0x15,
 154         frsqrt_op    =  0x16, fcvts_op     =  0x20,
 155         fcvtd_op     =  0x21, fcvte_op     =  0x22,
 156         fcvtw_op     =  0x24, fcvtl_op     =  0x25,
 157         fcmp_op      =  0x30
 158 };
 159
 160 /*
 161  * func field of cop1x opcodes (MIPS IV).
 162  */
 163 enum cop1x_func {
 164         lwxc1_op     =  0x00, ldxc1_op     =  0x01,
 165         pfetch_op    =  0x07, swxc1_op     =  0x08,
 166         sdxc1_op     =  0x09, madd_s_op    =  0x20,
 167         madd_d_op    =  0x21, madd_e_op    =  0x22,
 168         msub_s_op    =  0x28, msub_d_op    =  0x29,
 169         msub_e_op    =  0x2a, nmadd_s_op   =  0x30,
 170         nmadd_d_op   =  0x31, nmadd_e_op   =  0x32,
 171         nmsub_s_op   =  0x38, nmsub_d_op   =  0x39,
 172         nmsub_e_op   =  0x3a
 173 };
 174
 175 /*
 176  * func field for mad opcodes (MIPS IV).
 177  */
 178 enum mad_func {
 179         madd_fp_op      = 0x08, msub_fp_op      = 0x0a,
 180         nmadd_fp_op     = 0x0c, nmsub_fp_op     = 0x0e
 181 };
 182
 183 /*
 184  * func field for special3 lx opcodes (Cavium Octeon).
 185  */
 186 enum lx_func {
 187         lwx_op  = 0x00,
 188         lhx_op  = 0x04,
 189         lbux_op = 0x06,
 190         ldx_op  = 0x08,
 191         lwux_op = 0x10,
 192         lhux_op = 0x14,
 193         lbx_op  = 0x16,
 194 };
 195
 196 /*
 197  * Damn ...  bitfields depend from byteorder :-(
 198  */
 199 #ifdef __MIPSEB__
 200 struct j_format {       /* Jump format */
 201         unsigned int opcode : 6;
 202         unsigned int target : 26;
 203 };
 204
 205 struct i_format {       /* Immediate format (addi, lw, ...) */
 206         unsigned int opcode : 6;
 207         unsigned int rs : 5;
 208         unsigned int rt : 5;
 209         signed int simmediate : 16;
 210 };
 211
 212 struct u_format {       /* Unsigned immediate format (ori, xori, ...) */
 213         unsigned int opcode : 6;
 214         unsigned int rs : 5;
 215         unsigned int rt : 5;
 216         unsigned int uimmediate : 16;
 217 };
 218
 219 struct c_format {       /* Cache (>= R6000) format */
 220         unsigned int opcode : 6;
 221         unsigned int rs : 5;
 222         unsigned int c_op : 3;
 223         unsigned int cache : 2;
 224         unsigned int simmediate : 16;
 225 };
 226
 227 struct r_format {       /* Register format */
 228         unsigned int opcode : 6;
 229         unsigned int rs : 5;
 230         unsigned int rt : 5;
 231         unsigned int rd : 5;
 232         unsigned int re : 5;
 233         unsigned int func : 6;
 234 };
 235
 236 struct p_format {       /* Performance counter format (R10000) */
 237         unsigned int opcode : 6;
 238         unsigned int rs : 5;
 239         unsigned int rt : 5;
 240         unsigned int rd : 5;
 241         unsigned int re : 5;
 242         unsigned int func : 6;
 243 };
 244
 245 struct f_format {       /* FPU register format */
 246         unsigned int opcode : 6;
 247         unsigned int : 1;
 248         unsigned int fmt : 4;
 249         unsigned int rt : 5;
 250         unsigned int rd : 5;
 251         unsigned int re : 5;
 252         unsigned int func : 6;
 253 };
 254
 255 struct ma_format {      /* FPU multipy and add format (MIPS IV) */
 256         unsigned int opcode : 6;
 257         unsigned int fr : 5;
 258         unsigned int ft : 5;
 259         unsigned int fs : 5;
 260         unsigned int fd : 5;
 261         unsigned int func : 4;
 262         unsigned int fmt : 2;
 263 };
 264
 265 struct b_format {       /* BREAK and SYSCALL */
 266         unsigned int opcode:6;
 267         unsigned int code:20;
 268         unsigned int func:6;
 269 };
 270
 271 struct fb_format {      /* FPU branch format */
 272         unsigned int opcode:6;
 273         unsigned int bc:5;
 274         unsigned int cc:3;
 275         unsigned int flag:2;
 276         unsigned int simmediate:16;
 277 };
 278
 279 struct fp0_format {      /* FPU multipy and add format (MIPS32) */
 280         unsigned int opcode:6;
 281         unsigned int fmt:5;
 282         unsigned int ft:5;
 283         unsigned int fs:5;
 284         unsigned int fd:5;
 285         unsigned int func:6;
 286 };
 287
 288 struct mm_fp0_format {      /* FPU multipy and add format (micro_mips) */
 289         unsigned int opcode:6;
 290         unsigned int ft:5;
 291         unsigned int fs:5;
 292         unsigned int fd:5;
 293         unsigned int fmt:3;
 294         unsigned int op:2;
 295         unsigned int func:6;
 296 };
 297
 298 struct fp1_format {      /* FPU mfc1 and cfc1 format (MIPS32) */
 299         unsigned int opcode:6;
 300         unsigned int op:5;
 301         unsigned int rt:5;
 302         unsigned int fs:5;
 303         unsigned int fd:5;
 304         unsigned int func:6;
 305 };
 306
 307 struct mm_fp1_format {      /* FPU mfc1 and cfc1 format (micro_mips) */
 308         unsigned int opcode:6;
 309         unsigned int rt:5;
 310         unsigned int fs:5;
 311         unsigned int fmt:2;
 312         unsigned int op:8;
 313         unsigned int func:6;
 314 };
 315
 316 struct mm_fp2_format {      /* FPU movt and movf format (micro_mips) */
 317         unsigned int opcode:6;
 318         unsigned int fd:5;
 319         unsigned int fs:5;
 320         unsigned int cc:3;
 321         unsigned int zero:2;
 322         unsigned int fmt:2;
 323         unsigned int op:3;
 324         unsigned int func:6;
 325 };
 326
 327 struct mm_fp3_format {      /* FPU abs and neg format (micro_mips) */
 328         unsigned int opcode:6;
 329         unsigned int rt:5;
 330         unsigned int fs:5;
 331         unsigned int fmt:3;
 332         unsigned int op:7;
 333         unsigned int func:6;
 334 };
 335
 336 struct mm_fp4_format {      /* FPU c.cond format (micro_mips) */
 337         unsigned int opcode:6;
 338         unsigned int rt:5;
 339         unsigned int fs:5;
 340         unsigned int cc:3;
 341         unsigned int fmt:3;
 342         unsigned int cond:4;
 343         unsigned int func:6;
 344 };
 345
 346 struct mm_fp5_format {      /* FPU lwxc1 and swxc1 format (micro_mips) */
 347         unsigned int opcode:6;
 348         unsigned int index:5;
 349         unsigned int base:5;
 350         unsigned int fd:5;
 351         unsigned int op:5;
 352         unsigned int func:6;
 353 };
 354
 355 struct fp6_format {     /* FPU madd and msub format (MIPS IV) */
 356         unsigned int opcode:6;
 357         unsigned int fr:5;
 358         unsigned int ft:5;
 359         unsigned int fs:5;
 360         unsigned int fd:5;
 361         unsigned int func:6;
 362 };
 363
 364 struct mm_fp6_format {  /* FPU madd and msub format (micro_mips) */
 365         unsigned int opcode:6;
 366         unsigned int ft:5;
 367         unsigned int fs:5;
 368         unsigned int fd:5;
 369         unsigned int fr:5;
 370         unsigned int func:6;
 371 };
 372
 373 struct mm16b1_format {          /* micro_mips 16-bit branch format */
 374         unsigned int opcode:6;
 375         unsigned int rs:3;
 376         signed int simmediate:7;
 377         unsigned int duplicate:16;      /* a copy of the instn */
 378 };
 379
 380 struct mm16b0_format {          /* micro_mips 16-bit branch format */
 381         unsigned int opcode:6;
 382         signed int simmediate:10;
 383         unsigned int duplicate:16;      /* a copy of the instn */
 384 };
 385
 386 struct mm_i_format {            /* Immediate format (addi, lw, ...) */
 387         unsigned int opcode:6;
 388         unsigned int rt:5;
 389         unsigned int rs:5;
 390         signed int simmediate:16;
 391 };
 392
 393 /*  MIPS16e */
 394
 395 struct rr {
 396         unsigned int opcode:5;
 397         unsigned int rx:3;
 398         unsigned int nd:1;
 399         unsigned int l:1;
 400         unsigned int ra:1;
 401         unsigned int func:5;
 402 };
 403
 404 struct jal {
 405         unsigned int opcode:5;
 406         unsigned int x:1;
 407         unsigned int imm20_16:5;
 408         signed int imm25_21:5;
 409         /* unsigned int    imm20_15:0;  here is only first 16bits in first HW */
 410 };
 411
 412 struct i64 {
 413         unsigned int opcode:5;
 414         unsigned int func:3;
 415         unsigned int imm:8;
 416 };
 417
 418 struct ri64 {
 419         unsigned int opcode:5;
 420         unsigned int func:3;
 421         unsigned int ry:3;
 422         unsigned int imm:5;
 423 };
 424
 425 struct ri {
 426         unsigned int opcode:5;
 427         unsigned int rx:3;
 428         unsigned int imm:8;
 429 };
 430
 431 struct rri {
 432         unsigned int opcode:5;
 433         unsigned int rx:3;
 434         unsigned int ry:3;
 435         unsigned int imm:5;
 436 };
 437
 438 struct i8 {
 439         unsigned int opcode:5;
 440         unsigned int func:3;
 441         unsigned int imm:8;
 442 };
 443
 444 struct mm_m_format {
 445         unsigned int opcode:6;
 446         unsigned int rd:5;
 447         unsigned int base:5;
 448         unsigned int func:4;
 449         signed int simmediate:12;
 450 };
 451
 452 struct mm_x_format {
 453         unsigned int opcode:6;
 454         unsigned int index:5;
 455         unsigned int base:5;
 456         unsigned int rd:5;
 457         unsigned int func:11;
 458 };
 459
 460 struct mm16_m_format {
 461         unsigned int opcode:6;
 462         unsigned int func:4;
 463         unsigned int rlist:2;
 464         unsigned int imm:4;
 465         unsigned int duplicate:16;      /* a copy of the instn */
 466 };
 467
 468 struct mm16_rb_format {
 469         unsigned int opcode:6;
 470         unsigned int rt:3;
 471         unsigned int base:3;
 472         signed int simmediate:4;
 473         unsigned int duplicate:16;      /* a copy of the instn */
 474 };
 475
 476 struct mm16_r5_format {
 477         unsigned int opcode:6;
 478         unsigned int rt:5;
 479         signed int simmediate:5;
 480         unsigned int duplicate:16;      /* a copy of the instn */
 481 };
 482
 483 struct mm16_r3_format {
 484         unsigned int opcode:6;
 485         unsigned int rt:3;
 486         signed int simmediate:7;
 487         unsigned int duplicate:16;      /* a copy of the instn */
 488 };
 489
 490 #elif defined(__MIPSEL__)
 491
 492 struct j_format {               /* Jump format */
 493         unsigned int target:26;
 494         unsigned int opcode:6;
 495 };
 496
 497 struct i_format {               /* Immediate format */
 498         signed int simmediate:16;
 499         unsigned int rt:5;
 500         unsigned int rs:5;
 501         unsigned int opcode:6;
 502 };
 503
 504 struct u_format {               /* Unsigned immediate format */
 505         unsigned int uimmediate:16;
 506         unsigned int rt:5;
 507         unsigned int rs:5;
 508         unsigned int opcode:6;
 509 };
 510
 511 struct c_format {               /* Cache (>= R6000) format */
 512         unsigned int simmediate:16;
 513         unsigned int cache:2;
 514         unsigned int c_op:3;
 515         unsigned int rs:5;
 516         unsigned int opcode:6;
 517 };
 518
 519 struct r_format {               /* Register format */
 520         unsigned int func:6;
 521         unsigned int re:5;
 522         unsigned int rd:5;
 523         unsigned int rt:5;
 524         unsigned int rs:5;
 525         unsigned int opcode:6;
 526 };
 527
 528 struct p_format {               /* Performance counter format (R10000) */
 529         unsigned int func:6;
 530         unsigned int re:5;
 531         unsigned int rd:5;
 532         unsigned int rt:5;
 533         unsigned int rs:5;
 534         unsigned int opcode:6;
 535 };
 536
 537 struct f_format {               /* FPU register format */
 538         unsigned int func:6;
 539         unsigned int re:5;
 540         unsigned int rd:5;
 541         unsigned int rt:5;
 542         unsigned int fmt:4;
 543         unsigned int:1;
 544         unsigned int opcode:6;
 545 };
 546
 547 struct ma_format {              /* FPU multipy and add format (MIPS IV) */
 548         unsigned int fmt:2;
 549         unsigned int func:4;
 550         unsigned int fd:5;
 551         unsigned int fs:5;
 552         unsigned int ft:5;
 553         unsigned int fr:5;
 554         unsigned int opcode:6;
 555 };
 556
 557 struct b_format {               /* BREAK and SYSCALL */
 558         unsigned int func:6;
 559         unsigned int code:20;
 560         unsigned int opcode:6;
 561 };
 562
 563 struct fb_format {              /* FPU branch format */
 564         unsigned int simmediate:16;
 565         unsigned int flag:2;
 566         unsigned int cc:3;
 567         unsigned int bc:5;
 568         unsigned int opcode:6;
 569 };
 570
 571 struct fp0_format {             /* FPU multipy and add format (MIPS32) */
 572         unsigned int func:6;
 573         unsigned int fd:5;
 574         unsigned int fs:5;
 575         unsigned int ft:5;
 576         unsigned int fmt:5;
 577         unsigned int opcode:6;
 578 };
 579
 580 struct mm_fp0_format {          /* FPU multipy and add format (micro_mips) */
 581         unsigned int func:6;
 582         unsigned int op:2;
 583         unsigned int fmt:3;
 584         unsigned int fd:5;
 585         unsigned int fs:5;
 586         unsigned int ft:5;
 587         unsigned int opcode:6;
 588 };
 589
 590 struct fp1_format {             /* FPU mfc1 and cfc1 format (MIPS32) */
 591         unsigned int func:6;
 592         unsigned int fd:5;
 593         unsigned int fs:5;
 594         unsigned int rt:5;
 595         unsigned int op:5;
 596         unsigned int opcode:6;
 597 };
 598
 599 struct mm_fp1_format {          /* FPU mfc1 and cfc1 format (micro_mips) */
 600         unsigned int func:6;
 601         unsigned int op:8;
 602         unsigned int fmt:2;
 603         unsigned int fs:5;
 604         unsigned int rt:5;
 605         unsigned int opcode:6;
 606 };
 607
 608 struct mm_fp2_format {          /* FPU movt and movf format (micro_mips) */
 609         unsigned int func:6;
 610         unsigned int op:3;
 611         unsigned int fmt:2;
 612         unsigned int zero:2;
 613         unsigned int cc:3;
 614         unsigned int fs:5;
 615         unsigned int fd:5;
 616         unsigned int opcode:6;
 617 };
 618
 619 struct mm_fp3_format {          /* FPU abs and neg format (micro_mips) */
 620         unsigned int func:6;
 621         unsigned int op:7;
 622         unsigned int fmt:3;
 623         unsigned int fs:5;
 624         unsigned int rt:5;
 625         unsigned int opcode:6;
 626 };
 627
 628 struct mm_fp4_format {          /* FPU c.cond format (micro_mips) */
 629         unsigned int func:6;
 630         unsigned int cond:4;
 631         unsigned int fmt:3;
 632         unsigned int cc:3;
 633         unsigned int fs:5;
 634         unsigned int rt:5;
 635         unsigned int opcode:6;
 636 };
 637
 638 struct mm_fp5_format {          /* FPU lwxc1 and swxc1 format (micro_mips) */
 639         unsigned int func:6;
 640         unsigned int op:5;
 641         unsigned int fd:5;
 642         unsigned int base:5;
 643         unsigned int index:5;
 644         unsigned int opcode:6;
 645 };
 646
 647 struct fp6_format {             /* FPU madd and msub format (MIPS IV) */
 648         unsigned int func:6;
 649         unsigned int fd:5;
 650         unsigned int fs:5;
 651         unsigned int ft:5;
 652         unsigned int fr:5;
 653         unsigned int opcode:6;
 654 };
 655
 656 struct mm_fp6_format {          /* FPU madd and msub format (micro_mips) */
 657         unsigned int func:6;
 658         unsigned int fr:5;
 659         unsigned int fd:5;
 660         unsigned int fs:5;
 661         unsigned int ft:5;
 662         unsigned int opcode:6;
 663 };
 664
 665 struct mm16b1_format {          /* micro_mips 16-bit branch format */
 666         unsigned int duplicate:16;      /* a copy of the instn */
 667         signed int simmediate:7;
 668         unsigned int rs:3;
 669         unsigned int opcode:6;
 670 };
 671
 672 struct mm16b0_format {          /* micro_mips 16-bit branch format */
 673         unsigned int duplicate:16;      /* a copy of the instn */
 674         signed int simmediate:10;
 675         unsigned int opcode:6;
 676 };
 677
 678 struct mm_i_format {            /* Immediate format */
 679         signed int simmediate:16;
 680         unsigned int rs:5;
 681         unsigned int rt:5;
 682         unsigned int opcode:6;
 683 };
 684
 685 /*  MIPS16e */
 686
 687 struct rr {
 688         unsigned int func:5;
 689         unsigned int ra:1;
 690         unsigned int l:1;
 691         unsigned int nd:1;
 692         unsigned int rx:3;
 693         unsigned int opcode:5;
 694 };
 695
 696 struct jal {
 697         /* unsigned int    imm20_15:0;  here is only first 16bits in first HW */
 698         signed int imm25_21:5;
 699         unsigned int imm20_16:5;
 700         unsigned int x:1;
 701         unsigned int opcode:5;
 702 };
 703
 704 struct i64 {
 705         unsigned int imm:8;
 706         unsigned int func:3;
 707         unsigned int opcode:5;
 708 };
 709
 710 struct ri64 {
 711         unsigned int imm:5;
 712         unsigned int ry:3;
 713         unsigned int func:3;
 714         unsigned int opcode:5;
 715 };
 716
 717 struct ri {
 718         unsigned int imm:8;
 719         unsigned int rx:3;
 720         unsigned int opcode:5;
 721 };
 722
 723 struct rri {
 724         unsigned int imm:5;
 725         unsigned int ry:3;
 726         unsigned int rx:3;
 727         unsigned int opcode:5;
 728 };
 729
 730 struct i8 {
 731         unsigned int imm:8;
 732         unsigned int func:3;
 733         unsigned int opcode:5;
 734 };
 735
 736 struct mm_m_format {
 737         signed int simmediate:12;
 738         unsigned int func:4;
 739         unsigned int base:5;
 740         unsigned int rd:5;
 741         unsigned int opcode:6;
 742 };
 743
 744 struct mm_x_format {
 745         unsigned int func:11;
 746         unsigned int rd:5;
 747         unsigned int base:5;
 748         unsigned int index:5;
 749         unsigned int opcode:6;
 750 };
 751
 752 struct mm16_m_format {
 753         unsigned int duplicate:16;      /* a copy of the instn */
 754         unsigned int imm:4;
 755         unsigned int rlist:2;
 756         unsigned int func:4;
 757         unsigned int opcode:6;
 758 };
 759
 760 struct mm16_rb_format {
 761         unsigned int duplicate:16;      /* a copy of the instn */
 762         signed int simmediate:4;
 763         unsigned int base:3;
 764         unsigned int rt:3;
 765         unsigned int opcode:6;
 766 };
 767
 768 struct mm16_r5_format {
 769         unsigned int duplicate:16;      /* a copy of the instn */
 770         signed int simmediate:5;
 771         unsigned int rt:5;
 772         unsigned int opcode:6;
 773 };
 774
 775 struct mm16_r3_format {
 776         unsigned int duplicate:16;      /* a copy of the instn */
 777         signed int simmediate:7;
 778         unsigned int rt:3;
 779         unsigned int opcode:6;
 780 };
 781
 782 #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
 783 #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
 784 #endif
 785
 786 union mips_instruction {
 787         unsigned int word;
 788         unsigned short halfword[2];
 789         unsigned char byte[4];
 790         struct j_format j_format;
 791         struct i_format i_format;
 792         struct u_format u_format;
 793         struct c_format c_format;
 794         struct r_format r_format;
 795         struct f_format f_format;
 796         struct ma_format ma_format;
 797         struct b_format b_format;
 798         struct mm16b0_format mm16b0_format;
 799         struct mm16b1_format mm16b1_format;
 800         struct mm_i_format mm_i_format;
 801         struct fb_format fb_format;
 802         struct fp0_format fp0_format;
 803         struct fp1_format fp1_format;
 804         struct fp6_format fp6_format;
 805         struct mm_fp0_format mm_fp0_format;
 806         struct mm_fp1_format mm_fp1_format;
 807         struct mm_fp2_format mm_fp2_format;
 808         struct mm_fp3_format mm_fp3_format;
 809         struct mm_fp4_format mm_fp4_format;
 810         struct mm_fp5_format mm_fp5_format;
 811         struct mm_fp6_format mm_fp6_format;
 812         struct mm_m_format mm_m_format;
 813         struct mm_x_format mm_x_format;
 814         struct mm16_m_format mm16_m_format;
 815         struct mm16_rb_format mm16_rb_format;
 816         struct mm16_r3_format mm16_r3_format;
 817         struct mm16_r5_format mm16_r5_format;
 818 };
 819
 820 /* HACHACHAHCAHC ...  */
 821
 822 /* In case some other massaging is needed, keep MIPSInst as wrapper */
 823
 824 #define MIPSInst(x) x
 825
 826 #define I_OPCODE_SFT    26
 827 #define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
 828
 829 #define I_JTARGET_SFT   0
 830 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
 831
 832 #define I_RS_SFT        21
 833 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
 834
 835 #define I_RT_SFT        16
 836 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
 837
 838 #define I_IMM_SFT       0
 839 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
 840 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
 841
 842 #define I_CACHEOP_SFT   18
 843 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
 844
 845 #define I_CACHESEL_SFT  16
 846 #define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
 847
 848 #define I_RD_SFT        11
 849 #define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
 850
 851 #define I_RE_SFT        6
 852 #define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT)
 853
 854 #define I_FUNC_SFT      0
 855 #define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f)
 856
 857 #define I_FFMT_SFT      21
 858 #define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT)
 859
 860 #define I_FT_SFT        16
 861 #define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT)
 862
 863 #define I_FS_SFT        11
 864 #define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT)
 865
 866 #define I_FD_SFT        6
 867 #define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT)
 868
 869 #define I_FR_SFT        21
 870 #define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT)
 871
 872 #define I_FMA_FUNC_SFT  2
 873 #define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT)
 874
 875 #define I_FMA_FFMT_SFT  0
 876 #define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000003)
 877
 878 typedef unsigned int mips_instruction;
 879
 880 /* The following are for micro_mips mode */
 881 #define MM_16_OPCODE_SFT        10
 882 #define MM_NOP16                0x0c00
 883 #define MM_POOL32A_MINOR_MSK    0x3f
 884 #define MM_POOL32A_MINOR_SFT    0x6
 885 #define MIPS32_COND_FC          0x30
 886
 887 /*
 888  * Major opcodes; micro_mips mode.
 889  */
 890 enum mm_major_op {
 891         mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
 892         mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
 893         mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
 894         mm_andiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
 895         mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
 896         mm_ori32_op, mm_pool32f_op, mm_reserve1_op, mm_reserve2_op,
 897         mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
 898         mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserve3_op,
 899         mm_reserve4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
 900         mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
 901         mm_reserve5_op, mm_reserve6_op, mm_sh16_op, mm_bnez16_op,
 902         mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
 903         mm_reserve7_op, mm_reserve8_op, mm_swsp16_op, mm_b16_op,
 904         mm_and32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
 905         mm_reserve11_op, mm_reserve12_op, mm_sw16_op, mm_li16_op,
 906         mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op
 907 };
 908
 909 /*
 910  * POOL32I minor opcodes.
 911  */
 912 enum mm_32i_minor_op {
 913         mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
 914         mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
 915         mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
 916         mm_tnei_op, mm_lui_op, mm_teqi_op, mm_resv1_op,
 917         mm_synci_op, mm_bltzals_op, mm_resv2_op, mm_bgezals_op,
 918         mm_bc2f_op, mm_bc2t_op, mm_resv3_op, mm_resv4_op,
 919         mm_resv5_op, mm_resv6_op, mm_bposge64_op, mm_bposge32_op,
 920         mm_bc1f_op, mm_bc1t_op, mm_resv7_op, mm_resv8_op,
 921         mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op
 922 };
 923
 924 /*
 925  * POOL32A minor opcodes.
 926  */
 927 enum mm_32a_minor_op {
 928         mm_pool32axf_op = 0x3c
 929 };
 930
 931 enum mm_32a_func {
 932         mm_lwxs32_func = 0x118
 933 };
 934
 935 /*
 936  * POOL32B minor opcodes.
 937  */
 938 enum mm_32b_func {
 939         mm_lwc2_func = 0,
 940         mm_lwp32_func = 1,
 941         mm_ldc2_func = 2,
 942         mm_ldp32_func = 4,
 943         mm_lwm32_func = 5,
 944         mm_ldm32_func = 7,
 945         mm_swc2_func = 8,
 946         mm_swp32_func = 9,
 947         mm_sdc2_func = 0xa,
 948         mm_sdp32_func = 0xc,
 949         mm_swm32_func = 0xd,
 950         mm_sdm32_func = 0xf,
 951 };
 952
 953 /*
 954  * POOL32C minor opcodes.
 955  */
 956 enum mm_32c_func {
 957         mm_lwu32_func = 0xe,
 958 };
 959
 960 /*
 961  * POOL32AXF minor opcodes.
 962  */
 963 enum mm_32axf_minor_op {
 964         mm_jalr_op = 0x03c,
 965         mm_jalrhb_op = 0x07c,
 966         mm_jalrs_op = 0x13c,
 967         mm_jalrshb_op = 0x17c,
 968 };
 969
 970 /*
 971  * POOL32F minor opcodes.
 972  */
 973 enum mm_32f_minor_op {
 974         mm_32f_00_op = 0x00,
 975         mm_32f_01_op = 0x01,
 976         mm_32f_02_op = 0x02,
 977         mm_32f_10_op = 0x08,
 978         mm_32f_11_op = 0x09,
 979         mm_32f_12_op = 0x0a,
 980         mm_32f_20_op = 0x10,
 981         mm_32f_30_op = 0x18,
 982         mm_32f_40_op = 0x20,
 983         mm_32f_41_op = 0x21,
 984         mm_32f_42_op = 0x22,
 985         mm_32f_50_op = 0x28,
 986         mm_32f_51_op = 0x29,
 987         mm_32f_52_op = 0x2a,
 988         mm_32f_60_op = 0x30,
 989         mm_32f_70_op = 0x38,
 990         mm_32f_73_op = 0x3b,
 991         mm_32f_74_op = 0x3c,
 992 };
 993
 994 /*
 995  * POOL32F secondary minor opcodes.
 996  */
 997 enum mm_32f_10_minor_op {
 998         mm_lwxc1_op = 0x1,
 999         mm_swxc1_op,
1000         mm_ldxc1_op,
1001         mm_sdxc1_op,
1002         mm_luxc1_op,
1003         mm_suxc1_op,
1004 };
1005
1006 enum mm_32f_func {
1007         mm_lwxc1_func = 0x48,
1008         mm_swxc1_func = 0x88,
1009         mm_ldxc1_func = 0xc8,
1010         mm_sdxc1_func = 0x108,
1011 };
1012
1013 /*
1014  * POOL32F secondary minor opcodes.
1015  */
1016 enum mm_32f_40_minor_op {
1017         mm_fmovf_op,
1018         mm_fmovt_op,
1019 };
1020
1021 /*
1022  * POOL32F secondary minor opcodes.
1023  */
1024 enum mm_32f_60_minor_op {
1025         mm_fadd_op,
1026         mm_fsub_op,
1027         mm_fmul_op,
1028         mm_fdiv_op,
1029 };
1030
1031 /*
1032  * POOL32F secondary minor opcodes.
1033  */
1034 enum mm_32f_70_minor_op {
1035         mm_fmovn_op,
1036         mm_fmovz_op,
1037 };
1038
1039 /*
1040  * POOL32F secondary minor opcodes (POOL32FXF).
1041  */
1042 enum mm_32f_73_minor_op {
1043         mm_fmov0_op = 0x01,
1044         mm_fcvtl_op = 0x04,
1045         mm_movf0_op = 0x05,
1046         mm_frsqrt_op = 0x08,
1047         mm_ffloorl_op = 0x0c,
1048         mm_fabs0_op = 0x0d,
1049         mm_fcvtw_op = 0x24,
1050         mm_movt0_op = 0x25,
1051         mm_fsqrt_op = 0x28,
1052         mm_ffloorw_op = 0x2c,
1053         mm_fneg0_op = 0x2d,
1054         mm_cfc1_op = 0x40,
1055         mm_frecip_op = 0x48,
1056         mm_fceill_op = 0x4c,
1057         mm_fcvtd0_op = 0x4d,
1058         mm_ctc1_op = 0x60,
1059         mm_fceilw_op = 0x6c,
1060         mm_fcvts0_op = 0x6d,
1061         mm_mfc1_op = 0x80,
1062         mm_fmov1_op = 0x81,
1063         mm_movf1_op = 0x85,
1064         mm_ftruncl_op = 0x8c,
1065         mm_fabs1_op = 0x8d,
1066         mm_mtc1_op = 0xa0,
1067         mm_movt1_op = 0xa5,
1068         mm_ftruncw_op = 0xac,
1069         mm_fneg1_op = 0xad,
1070         mm_froundl_op = 0xcc,
1071         mm_fcvtd1_op = 0xcd,
1072         mm_froundw_op = 0xec,
1073         mm_fcvts1_op = 0xed,
1074 };
1075
1076 /*
1077  * POOL16C minor opcodes.
1078  */
1079 enum mm_16c_minor_op {
1080         mm_lwm16_func = 4,
1081         mm_swm16_func,
1082         mm_jr16_op = 0x0c,
1083         mm_jrc_op,
1084         mm_jalr16_op,
1085         mm_jalrs16_op
1086 };
1087
1088 struct decoded_instn {
1089         mips_instruction insn;
1090         mips_instruction next_insn;
1091         int pc_inc;
1092         int next_pc_inc;
1093         int micro_mips_mode;
1094 };
1095
1096 /*  recode table from MIPS16e register notation to GPR */
1097 extern int mips16e_reg2gpr[];
1098
1099 union mips16e_instruction {
1100         unsigned int full:16;
1101         struct rr rr;
1102         struct jal jal;
1103         struct i64 i64;
1104         struct ri64 ri64;
1105         struct ri ri;
1106         struct rri rri;
1107         struct i8 i8;
1108 };
1109
1110 enum MIPS16e_ops {
1111         MIPS16e_jal_op = 003,
1112         MIPS16e_ld_op = 007,
1113         MIPS16e_i8_op = 014,
1114         MIPS16e_sd_op = 017,
1115         MIPS16e_lb_op = 020,
1116         MIPS16e_lh_op = 021,
1117         MIPS16e_lwsp_op = 022,
1118         MIPS16e_lw_op = 023,
1119         MIPS16e_lbu_op = 024,
1120         MIPS16e_lhu_op = 025,
1121         MIPS16e_lwpc_op = 026,
1122         MIPS16e_lwu_op = 027,
1123         MIPS16e_sb_op = 030,
1124         MIPS16e_sh_op = 031,
1125         MIPS16e_swsp_op = 032,
1126         MIPS16e_sw_op = 033,
1127         MIPS16e_rr_op = 035,
1128         MIPS16e_extend_op = 036,
1129         MIPS16e_i64_op = 037,
1130 };
1131
1132 enum MIPS16e_i64_func {
1133         MIPS16e_ldsp_func,
1134         MIPS16e_sdsp_func,
1135         MIPS16e_sdrasp_func,
1136         MIPS16e_dadjsp_func,
1137         MIPS16e_ldpc_func,
1138 };
1139
1140 enum MIPS16e_rr_func {
1141         MIPS16e_jr_func,
1142 };
1143
1144 enum MIPS6e_i8_func {
1145         MIPS16e_swrasp_func = 02,
1146 };
1147
1148 /*
1149  * This functions returns 1 if the micro_mips instr is a 16 bit instr.
1150  * Otherwise return 0.
1151  */
1152 #define MIPS_ISA_MODE   01
1153 #define is16mode(regs)  (regs->cp0_epc & MIPS_ISA_MODE)
1154
1155 static inline int mm_is16bit(u16 instr)
1156 {
1157         /* take LS 3 bits */
1158         u16 opcode_low = (instr >> MM_16_OPCODE_SFT) & 0x7;
1159
1160         if (opcode_low >= 1 && opcode_low <= 3)
1161                 return 1;
1162         else
1163                 return 0;
1164 }
1165
1166 #endif /* _ASM_INST_H */