release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/alchemy/devboards/pb1100/board_setup.c

   1 /*
   2  * Copyright 2002, 2008 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc. <source@mvista.com>
   4  *
   5  *  This program is free software; you can redistribute  it and/or modify it
   6  *  under  the terms of  the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the  License, or (at your
   8  *  option) any later version.
   9  *
  10  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  11  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  13  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  14  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  15  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  16  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  17  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  18  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  19  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  20  *
  21  *  You should have received a copy of the  GNU General Public License along
  22  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  23  *  675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/gpio.h>
  27 #include <linux/init.h>
  28 #include <linux/delay.h>
  29 #include <linux/interrupt.h>
  30
  31 #include <asm/mach-au1x00/au1000.h>
  32 #include <asm/mach-db1x00/bcsr.h>
  33
  34 #include <prom.h>
  35
  36
  37 const char *get_system_type(void)
  38 {
  39         return "Alchemy Pb1100";
  40 }
  41
  42 void __init board_setup(void)
  43 {
  44         volatile void __iomem *base = (volatile void __iomem *)0xac000000UL;
  45
  46         bcsr_init(DB1000_BCSR_PHYS_ADDR,
  47                   DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
  48
  49         /* Set AUX clock to 12 MHz * 8 = 96 MHz */
  50         au_writel(8, SYS_AUXPLL);
  51         alchemy_gpio1_input_enable();
  52         udelay(100);
  53
  54 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  55         {
  56                 u32 pin_func, sys_freqctrl, sys_clksrc;
  57
  58                 /* Configure pins GPIO[14:9] as GPIO */
  59                 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
  60
  61                 /* Zero and disable FREQ2 */
  62                 sys_freqctrl = au_readl(SYS_FREQCTRL0);
  63                 sys_freqctrl &= ~0xFFF00000;
  64                 au_writel(sys_freqctrl, SYS_FREQCTRL0);
  65
  66                 /* Zero and disable USBH/USBD/IrDA clock */
  67                 sys_clksrc = au_readl(SYS_CLKSRC);
  68                 sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
  69                 au_writel(sys_clksrc, SYS_CLKSRC);
  70
  71                 sys_freqctrl = au_readl(SYS_FREQCTRL0);
  72                 sys_freqctrl &= ~0xFFF00000;
  73
  74                 sys_clksrc = au_readl(SYS_CLKSRC);
  75                 sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
  76
  77                 /* FREQ2 = aux / 2 = 48 MHz */
  78                 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
  79                                 SYS_FC_FE2 | SYS_FC_FS2;
  80                 au_writel(sys_freqctrl, SYS_FREQCTRL0);
  81
  82                 /*
  83                  * Route 48 MHz FREQ2 into USBH/USBD/IrDA
  84                  */
  85                 sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MIR_BIT;
  86                 au_writel(sys_clksrc, SYS_CLKSRC);
  87
  88                 /* Setup the static bus controller */
  89                 au_writel(0x00000002, MEM_STCFG3);  /* type = PCMCIA */
  90                 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
  91                 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
  92
  93                 /*
  94                  * Get USB Functionality pin state (device vs host drive pins).
  95                  */
  96                 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
  97                 /* 2nd USB port is USB host. */
  98                 pin_func |= SYS_PF_USB;
  99                 au_writel(pin_func, SYS_PINFUNC);
 100         }
 101 #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
 102
 103         /* Enable sys bus clock divider when IDLE state or no bus activity. */
 104         au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
 105
 106         /* Enable the RTC if not already enabled. */
 107         if (!(readb(base + 0x28) & 0x20)) {
 108                 writeb(readb(base + 0x28) | 0x20, base + 0x28);
 109                 au_sync();
 110         }
 111         /* Put the clock in BCD mode. */
 112         if (readb(base + 0x2C) & 0x4) { /* reg B */
 113                 writeb(readb(base + 0x2c) & ~0x4, base + 0x2c);
 114                 au_sync();
 115         }
 116 }
 117
 118 static int __init pb1100_init_irq(void)
 119 {
 120         set_irq_type(AU1100_GPIO9_INT,  IRQF_TRIGGER_LOW); /* PCCD# */
 121         set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
 122         set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
 123         set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
 124
 125         return 0;
 126 }
 127 arch_initcall(pb1100_init_irq);