2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
29 #include <linux/slab.h>
31 #include <linux/of_address.h>
33 #include <asm/processor.h>
35 #include <asm/pci-bridge.h>
36 #include <asm/byteorder.h>
38 static DEFINE_SPINLOCK(hose_spinlock
);
41 static int global_phb_number
; /* Global phb counter */
43 /* ISA Memory physical address */
44 resource_size_t isa_mem_base
;
46 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
47 unsigned int pci_flags
;
49 static struct dma_map_ops
*pci_dma_ops
= &dma_direct_ops
;
51 void set_pci_dma_ops(struct dma_map_ops
*dma_ops
)
53 pci_dma_ops
= dma_ops
;
56 struct dma_map_ops
*get_pci_dma_ops(void)
60 EXPORT_SYMBOL(get_pci_dma_ops
);
62 int pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
64 return dma_set_mask(&dev
->dev
, mask
);
67 int pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
71 rc
= dma_set_mask(&dev
->dev
, mask
);
72 dev
->dev
.coherent_dma_mask
= dev
->dma_mask
;
77 struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
)
79 struct pci_controller
*phb
;
81 phb
= zalloc_maybe_bootmem(sizeof(struct pci_controller
), GFP_KERNEL
);
84 spin_lock(&hose_spinlock
);
85 phb
->global_number
= global_phb_number
++;
86 list_add_tail(&phb
->list_node
, &hose_list
);
87 spin_unlock(&hose_spinlock
);
89 phb
->is_dynamic
= mem_init_done
;
93 void pcibios_free_controller(struct pci_controller
*phb
)
95 spin_lock(&hose_spinlock
);
96 list_del(&phb
->list_node
);
97 spin_unlock(&hose_spinlock
);
103 static resource_size_t
pcibios_io_size(const struct pci_controller
*hose
)
105 return hose
->io_resource
.end
- hose
->io_resource
.start
+ 1;
108 int pcibios_vaddr_is_ioport(void __iomem
*address
)
111 struct pci_controller
*hose
;
112 resource_size_t size
;
114 spin_lock(&hose_spinlock
);
115 list_for_each_entry(hose
, &hose_list
, list_node
) {
116 size
= pcibios_io_size(hose
);
117 if (address
>= hose
->io_base_virt
&&
118 address
< (hose
->io_base_virt
+ size
)) {
123 spin_unlock(&hose_spinlock
);
127 unsigned long pci_address_to_pio(phys_addr_t address
)
129 struct pci_controller
*hose
;
130 resource_size_t size
;
131 unsigned long ret
= ~0;
133 spin_lock(&hose_spinlock
);
134 list_for_each_entry(hose
, &hose_list
, list_node
) {
135 size
= pcibios_io_size(hose
);
136 if (address
>= hose
->io_base_phys
&&
137 address
< (hose
->io_base_phys
+ size
)) {
139 (unsigned long)hose
->io_base_virt
- _IO_BASE
;
140 ret
= base
+ (address
- hose
->io_base_phys
);
144 spin_unlock(&hose_spinlock
);
148 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
151 * Return the domain number for this bus.
153 int pci_domain_nr(struct pci_bus
*bus
)
155 struct pci_controller
*hose
= pci_bus_to_host(bus
);
157 return hose
->global_number
;
159 EXPORT_SYMBOL(pci_domain_nr
);
161 /* This routine is meant to be used early during boot, when the
162 * PCI bus numbers have not yet been assigned, and you need to
163 * issue PCI config cycles to an OF device.
164 * It could also be used to "fix" RTAS config cycles if you want
165 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
168 struct pci_controller
*pci_find_hose_for_OF_device(struct device_node
*node
)
171 struct pci_controller
*hose
, *tmp
;
172 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
173 if (hose
->dn
== node
)
180 static ssize_t
pci_show_devspec(struct device
*dev
,
181 struct device_attribute
*attr
, char *buf
)
183 struct pci_dev
*pdev
;
184 struct device_node
*np
;
186 pdev
= to_pci_dev(dev
);
187 np
= pci_device_to_OF_node(pdev
);
188 if (np
== NULL
|| np
->full_name
== NULL
)
190 return sprintf(buf
, "%s", np
->full_name
);
192 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
194 /* Add sysfs properties */
195 int pcibios_add_platform_entries(struct pci_dev
*pdev
)
197 return device_create_file(&pdev
->dev
, &dev_attr_devspec
);
200 char __devinit
*pcibios_setup(char *str
)
206 * Reads the interrupt pin to determine if interrupt is use by card.
207 * If the interrupt is used, then gets the interrupt line from the
208 * openfirmware and sets it in the pci_dev and pci_config line.
210 int pci_read_irq_line(struct pci_dev
*pci_dev
)
215 /* The current device-tree that iSeries generates from the HV
216 * PCI informations doesn't contain proper interrupt routing,
217 * and all the fallback would do is print out crap, so we
218 * don't attempt to resolve the interrupts here at all, some
219 * iSeries specific fixup does it.
221 * In the long run, we will hopefully fix the generated device-tree
224 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev
));
227 memset(&oirq
, 0xff, sizeof(oirq
));
229 /* Try to get a mapping from the device-tree */
230 if (of_irq_map_pci(pci_dev
, &oirq
)) {
233 /* If that fails, lets fallback to what is in the config
234 * space and map that through the default controller. We
235 * also set the type to level low since that's what PCI
236 * interrupts are. If your platform does differently, then
237 * either provide a proper interrupt tree or don't use this
240 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &pin
))
244 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, &line
) ||
245 line
== 0xff || line
== 0) {
248 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
251 virq
= irq_create_mapping(NULL
, line
);
253 set_irq_type(virq
, IRQ_TYPE_LEVEL_LOW
);
255 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
256 oirq
.size
, oirq
.specifier
[0], oirq
.specifier
[1],
257 oirq
.controller
? oirq
.controller
->full_name
:
260 virq
= irq_create_of_mapping(oirq
.controller
, oirq
.specifier
,
263 if (virq
== NO_IRQ
) {
264 pr_debug(" Failed to map !\n");
268 pr_debug(" Mapped to linux irq %d\n", virq
);
274 EXPORT_SYMBOL(pci_read_irq_line
);
277 * Platform support for /proc/bus/pci/X/Y mmap()s,
278 * modelled on the sparc64 implementation by Dave Miller.
282 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
283 resource_size_t
*offset
,
284 enum pci_mmap_state mmap_state
)
286 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
287 unsigned long io_offset
= 0;
291 return NULL
; /* should never happen */
293 /* If memory, add on the PCI bridge address offset */
294 if (mmap_state
== pci_mmap_mem
) {
295 res_bit
= IORESOURCE_MEM
;
297 io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
298 *offset
+= io_offset
;
299 res_bit
= IORESOURCE_IO
;
303 * Check that the offset requested corresponds to one of the
304 * resources of the device.
306 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
307 struct resource
*rp
= &dev
->resource
[i
];
308 int flags
= rp
->flags
;
310 /* treat ROM as memory (should be already) */
311 if (i
== PCI_ROM_RESOURCE
)
312 flags
|= IORESOURCE_MEM
;
314 /* Active and same type? */
315 if ((flags
& res_bit
) == 0)
318 /* In the range of this resource? */
319 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
322 /* found it! construct the final physical address */
323 if (mmap_state
== pci_mmap_io
)
324 *offset
+= hose
->io_base_phys
- io_offset
;
332 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
335 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
337 enum pci_mmap_state mmap_state
,
340 pgprot_t prot
= protection
;
342 if (mmap_state
!= pci_mmap_mem
)
344 else if (write_combine
== 0) {
345 if (rp
->flags
& IORESOURCE_PREFETCH
)
349 return pgprot_noncached(prot
);
353 * This one is used by /dev/mem and fbdev who have no clue about the
354 * PCI device, it tries to find the PCI device first and calls the
357 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
362 struct pci_dev
*pdev
= NULL
;
363 struct resource
*found
= NULL
;
364 resource_size_t offset
= ((resource_size_t
)pfn
) << PAGE_SHIFT
;
367 if (page_is_ram(pfn
))
370 prot
= pgprot_noncached(prot
);
371 for_each_pci_dev(pdev
) {
372 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
373 struct resource
*rp
= &pdev
->resource
[i
];
374 int flags
= rp
->flags
;
376 /* Active and same type? */
377 if ((flags
& IORESOURCE_MEM
) == 0)
379 /* In the range of this resource? */
380 if (offset
< (rp
->start
& PAGE_MASK
) ||
390 if (found
->flags
& IORESOURCE_PREFETCH
)
391 prot
= pgprot_noncached_wc(prot
);
395 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
396 (unsigned long long)offset
, pgprot_val(prot
));
402 * Perform the actual remap of the pages for a PCI device mapping, as
403 * appropriate for this architecture. The region in the process to map
404 * is described by vm_start and vm_end members of VMA, the base physical
405 * address is found in vm_pgoff.
406 * The pci device structure is provided so that architectures may make mapping
407 * decisions on a per-device or per-bus basis.
409 * Returns a negative error code on failure, zero on success.
411 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
412 enum pci_mmap_state mmap_state
, int write_combine
)
414 resource_size_t offset
=
415 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
419 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
423 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
424 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
426 mmap_state
, write_combine
);
428 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
429 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
434 /* This provides legacy IO read access on a bus */
435 int pci_legacy_read(struct pci_bus
*bus
, loff_t port
, u32
*val
, size_t size
)
437 unsigned long offset
;
438 struct pci_controller
*hose
= pci_bus_to_host(bus
);
439 struct resource
*rp
= &hose
->io_resource
;
442 /* Check if port can be supported by that bus. We only check
443 * the ranges of the PHB though, not the bus itself as the rules
444 * for forwarding legacy cycles down bridges are not our problem
445 * here. So if the host bridge supports it, we do it.
447 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
450 if (!(rp
->flags
& IORESOURCE_IO
))
452 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
454 addr
= hose
->io_base_virt
+ port
;
458 *((u8
*)val
) = in_8(addr
);
463 *((u16
*)val
) = in_le16(addr
);
468 *((u32
*)val
) = in_le32(addr
);
474 /* This provides legacy IO write access on a bus */
475 int pci_legacy_write(struct pci_bus
*bus
, loff_t port
, u32 val
, size_t size
)
477 unsigned long offset
;
478 struct pci_controller
*hose
= pci_bus_to_host(bus
);
479 struct resource
*rp
= &hose
->io_resource
;
482 /* Check if port can be supported by that bus. We only check
483 * the ranges of the PHB though, not the bus itself as the rules
484 * for forwarding legacy cycles down bridges are not our problem
485 * here. So if the host bridge supports it, we do it.
487 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
490 if (!(rp
->flags
& IORESOURCE_IO
))
492 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
494 addr
= hose
->io_base_virt
+ port
;
496 /* WARNING: The generic code is idiotic. It gets passed a pointer
497 * to what can be a 1, 2 or 4 byte quantity and always reads that
498 * as a u32, which means that we have to correct the location of
499 * the data read within those 32 bits for size 1 and 2
503 out_8(addr
, val
>> 24);
508 out_le16(addr
, val
>> 16);
519 /* This provides legacy IO or memory mmap access on a bus */
520 int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
521 struct vm_area_struct
*vma
,
522 enum pci_mmap_state mmap_state
)
524 struct pci_controller
*hose
= pci_bus_to_host(bus
);
525 resource_size_t offset
=
526 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
527 resource_size_t size
= vma
->vm_end
- vma
->vm_start
;
530 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
531 pci_domain_nr(bus
), bus
->number
,
532 mmap_state
== pci_mmap_mem
? "MEM" : "IO",
533 (unsigned long long)offset
,
534 (unsigned long long)(offset
+ size
- 1));
536 if (mmap_state
== pci_mmap_mem
) {
539 * Because X is lame and can fail starting if it gets an error
540 * trying to mmap legacy_mem (instead of just moving on without
541 * legacy memory access) we fake it here by giving it anonymous
542 * memory, effectively behaving just like /dev/zero
544 if ((offset
+ size
) > hose
->isa_mem_size
) {
547 "Process %s (pid:%d) mapped non-existing PCI"
548 "legacy memory for 0%04x:%02x\n",
549 current
->comm
, current
->pid
, pci_domain_nr(bus
),
552 if (vma
->vm_flags
& VM_SHARED
)
553 return shmem_zero_setup(vma
);
556 offset
+= hose
->isa_mem_phys
;
558 unsigned long io_offset
= (unsigned long)hose
->io_base_virt
- \
560 unsigned long roffset
= offset
+ io_offset
;
561 rp
= &hose
->io_resource
;
562 if (!(rp
->flags
& IORESOURCE_IO
))
564 if (roffset
< rp
->start
|| (roffset
+ size
) > rp
->end
)
566 offset
+= hose
->io_base_phys
;
568 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset
);
570 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
571 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
572 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
573 vma
->vm_end
- vma
->vm_start
,
577 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
578 const struct resource
*rsrc
,
579 resource_size_t
*start
, resource_size_t
*end
)
581 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
582 resource_size_t offset
= 0;
587 if (rsrc
->flags
& IORESOURCE_IO
)
588 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
590 /* We pass a fully fixed up address to userland for MMIO instead of
591 * a BAR value because X is lame and expects to be able to use that
592 * to pass to /dev/mem !
594 * That means that we'll have potentially 64 bits values where some
595 * userland apps only expect 32 (like X itself since it thinks only
596 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
599 * Hopefully, the sysfs insterface is immune to that gunk. Once X
600 * has been fixed (and the fix spread enough), we can re-enable the
601 * 2 lines below and pass down a BAR value to userland. In that case
602 * we'll also have to re-enable the matching code in
603 * __pci_mmap_make_offset().
608 *start
= rsrc
->start
- offset
;
609 *end
= rsrc
->end
- offset
;
613 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
614 * @hose: newly allocated pci_controller to be setup
615 * @dev: device node of the host bridge
616 * @primary: set if primary bus (32 bits only, soon to be deprecated)
618 * This function will parse the "ranges" property of a PCI host bridge device
619 * node and setup the resource mapping of a pci controller based on its
622 * Life would be boring if it wasn't for a few issues that we have to deal
625 * - We can only cope with one IO space range and up to 3 Memory space
626 * ranges. However, some machines (thanks Apple !) tend to split their
627 * space into lots of small contiguous ranges. So we have to coalesce.
629 * - We can only cope with all memory ranges having the same offset
630 * between CPU addresses and PCI addresses. Unfortunately, some bridges
631 * are setup for a large 1:1 mapping along with a small "window" which
632 * maps PCI address 0 to some arbitrary high address of the CPU space in
633 * order to give access to the ISA memory hole.
634 * The way out of here that I've chosen for now is to always set the
635 * offset based on the first resource found, then override it if we
636 * have a different offset and the previous was set by an ISA hole.
638 * - Some busses have IO space not starting at 0, which causes trouble with
639 * the way we do our IO resource renumbering. The code somewhat deals with
640 * it for 64 bits but I would expect problems on 32 bits.
642 * - Some 32 bits platforms such as 4xx can have physical space larger than
643 * 32 bits so we need to use 64 bits values for the parsing
645 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
646 struct device_node
*dev
,
651 int pna
= of_n_addr_cells(dev
);
653 int memno
= 0, isa_hole
= -1;
655 unsigned long long pci_addr
, cpu_addr
, pci_next
, cpu_next
, size
;
656 unsigned long long isa_mb
= 0;
657 struct resource
*res
;
659 printk(KERN_INFO
"PCI host bridge %s %s ranges:\n",
660 dev
->full_name
, primary
? "(primary)" : "");
662 /* Get ranges property */
663 ranges
= of_get_property(dev
, "ranges", &rlen
);
668 pr_debug("Parsing ranges property...\n");
669 while ((rlen
-= np
* 4) >= 0) {
670 /* Read next ranges element */
671 pci_space
= ranges
[0];
672 pci_addr
= of_read_number(ranges
+ 1, 2);
673 cpu_addr
= of_translate_address(dev
, ranges
+ 3);
674 size
= of_read_number(ranges
+ pna
+ 3, 2);
676 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx "
677 "cpu_addr:0x%016llx size:0x%016llx\n",
678 pci_space
, pci_addr
, cpu_addr
, size
);
682 /* If we failed translation or got a zero-sized region
683 * (some FW try to feed us with non sensical zero sized regions
684 * such as power3 which look like some kind of attempt
685 * at exposing the VGA memory hole)
687 if (cpu_addr
== OF_BAD_ADDR
|| size
== 0)
690 /* Now consume following elements while they are contiguous */
691 for (; rlen
>= np
* sizeof(u32
);
692 ranges
+= np
, rlen
-= np
* 4) {
693 if (ranges
[0] != pci_space
)
695 pci_next
= of_read_number(ranges
+ 1, 2);
696 cpu_next
= of_translate_address(dev
, ranges
+ 3);
697 if (pci_next
!= pci_addr
+ size
||
698 cpu_next
!= cpu_addr
+ size
)
700 size
+= of_read_number(ranges
+ pna
+ 3, 2);
703 /* Act based on address space type */
705 switch ((pci_space
>> 24) & 0x3) {
706 case 1: /* PCI IO space */
708 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
709 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
);
711 /* We support only one IO range */
712 if (hose
->pci_io_size
) {
714 " \\--> Skipped (too many) !\n");
717 /* On 32 bits, limit I/O space to 16MB */
718 if (size
> 0x01000000)
721 /* 32 bits needs to map IOs here */
722 hose
->io_base_virt
= ioremap(cpu_addr
, size
);
724 /* Expect trouble if pci_addr is not 0 */
727 (unsigned long)hose
->io_base_virt
;
728 /* pci_io_size and io_base_phys always represent IO
729 * space starting at 0 so we factor in pci_addr
731 hose
->pci_io_size
= pci_addr
+ size
;
732 hose
->io_base_phys
= cpu_addr
- pci_addr
;
735 res
= &hose
->io_resource
;
736 res
->flags
= IORESOURCE_IO
;
737 res
->start
= pci_addr
;
739 case 2: /* PCI Memory space */
740 case 3: /* PCI 64 bits Memory space */
742 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
743 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
,
744 (pci_space
& 0x40000000) ? "Prefetch" : "");
746 /* We support only 3 memory ranges */
749 " \\--> Skipped (too many) !\n");
752 /* Handles ISA memory hole space here */
756 if (primary
|| isa_mem_base
== 0)
757 isa_mem_base
= cpu_addr
;
758 hose
->isa_mem_phys
= cpu_addr
;
759 hose
->isa_mem_size
= size
;
762 /* We get the PCI/Mem offset from the first range or
763 * the, current one if the offset came from an ISA
764 * hole. If they don't match, bugger.
767 (isa_hole
>= 0 && pci_addr
!= 0 &&
768 hose
->pci_mem_offset
== isa_mb
))
769 hose
->pci_mem_offset
= cpu_addr
- pci_addr
;
770 else if (pci_addr
!= 0 &&
771 hose
->pci_mem_offset
!= cpu_addr
- pci_addr
) {
773 " \\--> Skipped (offset mismatch) !\n");
778 res
= &hose
->mem_resources
[memno
++];
779 res
->flags
= IORESOURCE_MEM
;
780 if (pci_space
& 0x40000000)
781 res
->flags
|= IORESOURCE_PREFETCH
;
782 res
->start
= cpu_addr
;
786 res
->name
= dev
->full_name
;
787 res
->end
= res
->start
+ size
- 1;
794 /* If there's an ISA hole and the pci_mem_offset is -not- matching
795 * the ISA hole offset, then we need to remove the ISA hole from
796 * the resource list for that brige
798 if (isa_hole
>= 0 && hose
->pci_mem_offset
!= isa_mb
) {
799 unsigned int next
= isa_hole
+ 1;
800 printk(KERN_INFO
" Removing ISA hole at 0x%016llx\n", isa_mb
);
802 memmove(&hose
->mem_resources
[isa_hole
],
803 &hose
->mem_resources
[next
],
804 sizeof(struct resource
) * (memno
- next
));
805 hose
->mem_resources
[--memno
].flags
= 0;
809 /* Decide whether to display the domain number in /proc */
810 int pci_proc_domain(struct pci_bus
*bus
)
812 struct pci_controller
*hose
= pci_bus_to_host(bus
);
814 if (!(pci_flags
& PCI_ENABLE_PROC_DOMAINS
))
816 if (pci_flags
& PCI_COMPAT_DOMAIN_0
)
817 return hose
->global_number
!= 0;
821 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
822 struct resource
*res
)
824 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
825 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
829 if (res
->flags
& IORESOURCE_IO
) {
830 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
832 } else if (res
->flags
& IORESOURCE_MEM
)
833 offset
= hose
->pci_mem_offset
;
835 region
->start
= (res
->start
- offset
) & mask
;
836 region
->end
= (res
->end
- offset
) & mask
;
838 EXPORT_SYMBOL(pcibios_resource_to_bus
);
840 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
841 struct pci_bus_region
*region
)
843 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
844 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
848 if (res
->flags
& IORESOURCE_IO
) {
849 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
851 } else if (res
->flags
& IORESOURCE_MEM
)
852 offset
= hose
->pci_mem_offset
;
853 res
->start
= (region
->start
+ offset
) & mask
;
854 res
->end
= (region
->end
+ offset
) & mask
;
856 EXPORT_SYMBOL(pcibios_bus_to_resource
);
858 /* Fixup a bus resource into a linux resource */
859 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
861 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
862 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
864 if (res
->flags
& IORESOURCE_IO
) {
865 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
867 } else if (res
->flags
& IORESOURCE_MEM
)
868 offset
= hose
->pci_mem_offset
;
870 res
->start
= (res
->start
+ offset
) & mask
;
871 res
->end
= (res
->end
+ offset
) & mask
;
874 /* This header fixup will do the resource fixup for all devices as they are
875 * probed, but not for bridge ranges
877 static void __devinit
pcibios_fixup_resources(struct pci_dev
*dev
)
879 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
883 printk(KERN_ERR
"No host bridge for PCI dev %s !\n",
887 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
888 struct resource
*res
= dev
->resource
+ i
;
891 /* On platforms that have PCI_PROBE_ONLY set, we don't
892 * consider 0 as an unassigned BAR value. It's technically
893 * a valid value, but linux doesn't like it... so when we can
894 * re-assign things, we do so, but if we can't, we keep it
895 * around and hope for the best...
897 if (res
->start
== 0 && !(pci_flags
& PCI_PROBE_ONLY
)) {
898 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]" \
901 (unsigned long long)res
->start
,
902 (unsigned long long)res
->end
,
903 (unsigned int)res
->flags
);
904 res
->end
-= res
->start
;
906 res
->flags
|= IORESOURCE_UNSET
;
910 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
912 (unsigned long long)res
->start
,\
913 (unsigned long long)res
->end
,
914 (unsigned int)res
->flags
);
916 fixup_resource(res
, dev
);
918 pr_debug("PCI:%s %016llx-%016llx\n",
920 (unsigned long long)res
->start
,
921 (unsigned long long)res
->end
);
924 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
926 /* This function tries to figure out if a bridge resource has been initialized
927 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
928 * things go more smoothly when it gets it right. It should covers cases such
929 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
931 static int __devinit
pcibios_uninitialized_bridge_resource(struct pci_bus
*bus
,
932 struct resource
*res
)
934 struct pci_controller
*hose
= pci_bus_to_host(bus
);
935 struct pci_dev
*dev
= bus
->self
;
936 resource_size_t offset
;
940 /* We don't do anything if PCI_PROBE_ONLY is set */
941 if (pci_flags
& PCI_PROBE_ONLY
)
944 /* Job is a bit different between memory and IO */
945 if (res
->flags
& IORESOURCE_MEM
) {
946 /* If the BAR is non-0 (res != pci_mem_offset) then it's
947 * probably been initialized by somebody
949 if (res
->start
!= hose
->pci_mem_offset
)
952 /* The BAR is 0, let's check if memory decoding is enabled on
953 * the bridge. If not, we consider it unassigned
955 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
956 if ((command
& PCI_COMMAND_MEMORY
) == 0)
959 /* Memory decoding is enabled and the BAR is 0. If any of
960 * the bridge resources covers that starting address (0 then
961 * it's good enough for us for memory
963 for (i
= 0; i
< 3; i
++) {
964 if ((hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
) &&
965 hose
->mem_resources
[i
].start
== hose
->pci_mem_offset
)
969 /* Well, it starts at 0 and we know it will collide so we may as
970 * well consider it as unassigned. That covers the Apple case.
974 /* If the BAR is non-0, then we consider it assigned */
975 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
976 if (((res
->start
- offset
) & 0xfffffffful
) != 0)
979 /* Here, we are a bit different than memory as typically IO
980 * space starting at low addresses -is- valid. What we do
981 * instead if that we consider as unassigned anything that
982 * doesn't have IO enabled in the PCI command register,
985 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
986 if (command
& PCI_COMMAND_IO
)
989 /* It's starting at 0 and IO is disabled in the bridge, consider
996 /* Fixup resources of a PCI<->PCI bridge */
997 static void __devinit
pcibios_fixup_bridge(struct pci_bus
*bus
)
999 struct resource
*res
;
1002 struct pci_dev
*dev
= bus
->self
;
1004 pci_bus_for_each_resource(bus
, res
, i
) {
1005 res
= bus
->resource
[i
];
1010 if (i
>= 3 && bus
->self
->transparent
)
1013 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1015 (unsigned long long)res
->start
,\
1016 (unsigned long long)res
->end
,
1017 (unsigned int)res
->flags
);
1020 fixup_resource(res
, dev
);
1022 /* Try to detect uninitialized P2P bridge resources,
1023 * and clear them out so they get re-assigned later
1025 if (pcibios_uninitialized_bridge_resource(bus
, res
)) {
1027 pr_debug("PCI:%s (unassigned)\n",
1030 pr_debug("PCI:%s %016llx-%016llx\n",
1032 (unsigned long long)res
->start
,
1033 (unsigned long long)res
->end
);
1038 void __devinit
pcibios_setup_bus_self(struct pci_bus
*bus
)
1040 /* Fix up the bus resources for P2P bridges */
1041 if (bus
->self
!= NULL
)
1042 pcibios_fixup_bridge(bus
);
1045 void __devinit
pcibios_setup_bus_devices(struct pci_bus
*bus
)
1047 struct pci_dev
*dev
;
1049 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1050 bus
->number
, bus
->self
? pci_name(bus
->self
) : "PHB");
1052 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1053 struct dev_archdata
*sd
= &dev
->dev
.archdata
;
1055 /* Setup OF node pointer in archdata */
1056 dev
->dev
.of_node
= pci_device_to_OF_node(dev
);
1058 /* Fixup NUMA node as it may not be setup yet by the generic
1059 * code and is needed by the DMA init
1061 set_dev_node(&dev
->dev
, pcibus_to_node(dev
->bus
));
1063 /* Hook up default DMA ops */
1064 sd
->dma_ops
= pci_dma_ops
;
1065 sd
->dma_data
= (void *)PCI_DRAM_OFFSET
;
1067 /* Read default IRQs and fixup if necessary */
1068 pci_read_irq_line(dev
);
1072 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1074 /* When called from the generic PCI probe, read PCI<->PCI bridge
1075 * bases. This is -not- called when generating the PCI tree from
1076 * the OF device-tree.
1078 if (bus
->self
!= NULL
)
1079 pci_read_bridge_bases(bus
);
1081 /* Now fixup the bus bus */
1082 pcibios_setup_bus_self(bus
);
1084 /* Now fixup devices on that bus */
1085 pcibios_setup_bus_devices(bus
);
1087 EXPORT_SYMBOL(pcibios_fixup_bus
);
1089 static int skip_isa_ioresource_align(struct pci_dev
*dev
)
1091 if ((pci_flags
& PCI_CAN_SKIP_ISA_ALIGN
) &&
1092 !(dev
->bus
->bridge_ctl
& PCI_BRIDGE_CTL_ISA
))
1098 * We need to avoid collisions with `mirrored' VGA ports
1099 * and other strange ISA hardware, so we always want the
1100 * addresses to be allocated in the 0x000-0x0ff region
1103 * Why? Because some silly external IO cards only decode
1104 * the low 10 bits of the IO address. The 0x00-0xff region
1105 * is reserved for motherboard devices that decode all 16
1106 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1107 * but we want to try to avoid allocating at 0x2900-0x2bff
1108 * which might have be mirrored at 0x0100-0x03ff..
1110 resource_size_t
pcibios_align_resource(void *data
, const struct resource
*res
,
1111 resource_size_t size
, resource_size_t align
)
1113 struct pci_dev
*dev
= data
;
1114 resource_size_t start
= res
->start
;
1116 if (res
->flags
& IORESOURCE_IO
) {
1117 if (skip_isa_ioresource_align(dev
))
1120 start
= (start
+ 0x3ff) & ~0x3ff;
1125 EXPORT_SYMBOL(pcibios_align_resource
);
1128 * Reparent resource children of pr that conflict with res
1129 * under res, and make res replace those children.
1131 static int __init
reparent_resources(struct resource
*parent
,
1132 struct resource
*res
)
1134 struct resource
*p
, **pp
;
1135 struct resource
**firstpp
= NULL
;
1137 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
1138 if (p
->end
< res
->start
)
1140 if (res
->end
< p
->start
)
1142 if (p
->start
< res
->start
|| p
->end
> res
->end
)
1143 return -1; /* not completely contained */
1144 if (firstpp
== NULL
)
1147 if (firstpp
== NULL
)
1148 return -1; /* didn't find any conflicting entries? */
1149 res
->parent
= parent
;
1150 res
->child
= *firstpp
;
1154 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
1156 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1158 (unsigned long long)p
->start
,
1159 (unsigned long long)p
->end
, res
->name
);
1165 void pcibios_allocate_bus_resources(struct pci_bus
*bus
)
1169 struct resource
*res
, *pr
;
1171 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1172 pci_domain_nr(bus
), bus
->number
);
1174 pci_bus_for_each_resource(bus
, res
, i
) {
1175 res
= bus
->resource
[i
];
1176 if (!res
|| !res
->flags
1177 || res
->start
> res
->end
|| res
->parent
)
1179 if (bus
->parent
== NULL
)
1180 pr
= (res
->flags
& IORESOURCE_IO
) ?
1181 &ioport_resource
: &iomem_resource
;
1183 /* Don't bother with non-root busses when
1184 * re-assigning all resources. We clear the
1185 * resource flags as if they were colliding
1186 * and as such ensure proper re-allocation
1189 if (pci_flags
& PCI_REASSIGN_ALL_RSRC
)
1190 goto clear_resource
;
1191 pr
= pci_find_parent_resource(bus
->self
, res
);
1193 /* this happens when the generic PCI
1194 * code (wrongly) decides that this
1195 * bridge is transparent -- paulus
1201 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1202 "[0x%x], parent %p (%s)\n",
1203 bus
->self
? pci_name(bus
->self
) : "PHB",
1205 (unsigned long long)res
->start
,
1206 (unsigned long long)res
->end
,
1207 (unsigned int)res
->flags
,
1208 pr
, (pr
&& pr
->name
) ? pr
->name
: "nil");
1210 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
1211 if (request_resource(pr
, res
) == 0)
1214 * Must be a conflict with an existing entry.
1215 * Move that entry (or entries) under the
1216 * bridge resource and try again.
1218 if (reparent_resources(pr
, res
) == 0)
1221 printk(KERN_WARNING
"PCI: Cannot allocate resource region "
1222 "%d of PCI bridge %d, will remap\n", i
, bus
->number
);
1224 res
->start
= res
->end
= 0;
1228 list_for_each_entry(b
, &bus
->children
, node
)
1229 pcibios_allocate_bus_resources(b
);
1232 static inline void __devinit
alloc_resource(struct pci_dev
*dev
, int idx
)
1234 struct resource
*pr
, *r
= &dev
->resource
[idx
];
1236 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1238 (unsigned long long)r
->start
,
1239 (unsigned long long)r
->end
,
1240 (unsigned int)r
->flags
);
1242 pr
= pci_find_parent_resource(dev
, r
);
1243 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) ||
1244 request_resource(pr
, r
) < 0) {
1245 printk(KERN_WARNING
"PCI: Cannot allocate resource region %d"
1246 " of device %s, will remap\n", idx
, pci_name(dev
));
1248 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1250 (unsigned long long)pr
->start
,
1251 (unsigned long long)pr
->end
,
1252 (unsigned int)pr
->flags
);
1253 /* We'll assign a new address later */
1254 r
->flags
|= IORESOURCE_UNSET
;
1260 static void __init
pcibios_allocate_resources(int pass
)
1262 struct pci_dev
*dev
= NULL
;
1267 for_each_pci_dev(dev
) {
1268 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1269 for (idx
= 0; idx
<= PCI_ROM_RESOURCE
; idx
++) {
1270 r
= &dev
->resource
[idx
];
1271 if (r
->parent
) /* Already allocated */
1273 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
1274 continue; /* Not assigned at all */
1275 /* We only allocate ROMs on pass 1 just in case they
1276 * have been screwed up by firmware
1278 if (idx
== PCI_ROM_RESOURCE
)
1280 if (r
->flags
& IORESOURCE_IO
)
1281 disabled
= !(command
& PCI_COMMAND_IO
);
1283 disabled
= !(command
& PCI_COMMAND_MEMORY
);
1284 if (pass
== disabled
)
1285 alloc_resource(dev
, idx
);
1289 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
1291 /* Turn the ROM off, leave the resource region,
1292 * but keep it unregistered.
1295 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
1296 if (reg
& PCI_ROM_ADDRESS_ENABLE
) {
1297 pr_debug("PCI: Switching off ROM of %s\n",
1299 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
1300 pci_write_config_dword(dev
, dev
->rom_base_reg
,
1301 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
1307 static void __init
pcibios_reserve_legacy_regions(struct pci_bus
*bus
)
1309 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1310 resource_size_t offset
;
1311 struct resource
*res
, *pres
;
1314 pr_debug("Reserving legacy ranges for domain %04x\n",
1315 pci_domain_nr(bus
));
1318 if (!(hose
->io_resource
.flags
& IORESOURCE_IO
))
1320 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1321 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1322 BUG_ON(res
== NULL
);
1323 res
->name
= "Legacy IO";
1324 res
->flags
= IORESOURCE_IO
;
1325 res
->start
= offset
;
1326 res
->end
= (offset
+ 0xfff) & 0xfffffffful
;
1327 pr_debug("Candidate legacy IO: %pR\n", res
);
1328 if (request_resource(&hose
->io_resource
, res
)) {
1330 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1331 pci_domain_nr(bus
), bus
->number
, res
);
1336 /* Check for memory */
1337 offset
= hose
->pci_mem_offset
;
1338 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset
);
1339 for (i
= 0; i
< 3; i
++) {
1340 pres
= &hose
->mem_resources
[i
];
1341 if (!(pres
->flags
& IORESOURCE_MEM
))
1343 pr_debug("hose mem res: %pR\n", pres
);
1344 if ((pres
->start
- offset
) <= 0xa0000 &&
1345 (pres
->end
- offset
) >= 0xbffff)
1350 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1351 BUG_ON(res
== NULL
);
1352 res
->name
= "Legacy VGA memory";
1353 res
->flags
= IORESOURCE_MEM
;
1354 res
->start
= 0xa0000 + offset
;
1355 res
->end
= 0xbffff + offset
;
1356 pr_debug("Candidate VGA memory: %pR\n", res
);
1357 if (request_resource(pres
, res
)) {
1359 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1360 pci_domain_nr(bus
), bus
->number
, res
);
1365 void __init
pcibios_resource_survey(void)
1369 /* Allocate and assign resources. If we re-assign everything, then
1370 * we skip the allocate phase
1372 list_for_each_entry(b
, &pci_root_buses
, node
)
1373 pcibios_allocate_bus_resources(b
);
1375 if (!(pci_flags
& PCI_REASSIGN_ALL_RSRC
)) {
1376 pcibios_allocate_resources(0);
1377 pcibios_allocate_resources(1);
1380 /* Before we start assigning unassigned resource, we try to reserve
1381 * the low IO area and the VGA memory area if they intersect the
1382 * bus available resources to avoid allocating things on top of them
1384 if (!(pci_flags
& PCI_PROBE_ONLY
)) {
1385 list_for_each_entry(b
, &pci_root_buses
, node
)
1386 pcibios_reserve_legacy_regions(b
);
1389 /* Now, if the platform didn't decide to blindly trust the firmware,
1390 * we proceed to assigning things that were left unassigned
1392 if (!(pci_flags
& PCI_PROBE_ONLY
)) {
1393 pr_debug("PCI: Assigning unassigned resources...\n");
1394 pci_assign_unassigned_resources();
1398 #ifdef CONFIG_HOTPLUG
1400 /* This is used by the PCI hotplug driver to allocate resource
1401 * of newly plugged busses. We can try to consolidate with the
1402 * rest of the code later, for now, keep it as-is as our main
1403 * resource allocation function doesn't deal with sub-trees yet.
1405 void __devinit
pcibios_claim_one_bus(struct pci_bus
*bus
)
1407 struct pci_dev
*dev
;
1408 struct pci_bus
*child_bus
;
1410 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1413 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1414 struct resource
*r
= &dev
->resource
[i
];
1416 if (r
->parent
|| !r
->start
|| !r
->flags
)
1419 pr_debug("PCI: Claiming %s: "
1420 "Resource %d: %016llx..%016llx [%x]\n",
1422 (unsigned long long)r
->start
,
1423 (unsigned long long)r
->end
,
1424 (unsigned int)r
->flags
);
1426 pci_claim_resource(dev
, i
);
1430 list_for_each_entry(child_bus
, &bus
->children
, node
)
1431 pcibios_claim_one_bus(child_bus
);
1433 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
1436 /* pcibios_finish_adding_to_bus
1438 * This is to be called by the hotplug code after devices have been
1439 * added to a bus, this include calling it for a PHB that is just
1442 void pcibios_finish_adding_to_bus(struct pci_bus
*bus
)
1444 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1445 pci_domain_nr(bus
), bus
->number
);
1447 /* Allocate bus and devices resources */
1448 pcibios_allocate_bus_resources(bus
);
1449 pcibios_claim_one_bus(bus
);
1451 /* Add new devices to global lists. Register in proc, sysfs. */
1452 pci_bus_add_devices(bus
);
1455 /* eeh_add_device_tree_late(bus); */
1457 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus
);
1459 #endif /* CONFIG_HOTPLUG */
1461 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
1463 return pci_enable_resources(dev
, mask
);
1466 void __devinit
pcibios_setup_phb_resources(struct pci_controller
*hose
)
1468 struct pci_bus
*bus
= hose
->bus
;
1469 struct resource
*res
;
1472 /* Hookup PHB IO resource */
1473 bus
->resource
[0] = res
= &hose
->io_resource
;
1476 printk(KERN_WARNING
"PCI: I/O resource not set for host"
1477 " bridge %s (domain %d)\n",
1478 hose
->dn
->full_name
, hose
->global_number
);
1479 res
->start
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1480 res
->end
= res
->start
+ IO_SPACE_LIMIT
;
1481 res
->flags
= IORESOURCE_IO
;
1484 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1485 (unsigned long long)res
->start
,
1486 (unsigned long long)res
->end
,
1487 (unsigned long)res
->flags
);
1489 /* Hookup PHB Memory resources */
1490 for (i
= 0; i
< 3; ++i
) {
1491 res
= &hose
->mem_resources
[i
];
1495 printk(KERN_ERR
"PCI: Memory resource 0 not set for "
1496 "host bridge %s (domain %d)\n",
1497 hose
->dn
->full_name
, hose
->global_number
);
1499 res
->start
= hose
->pci_mem_offset
;
1500 res
->end
= (resource_size_t
)-1LL;
1501 res
->flags
= IORESOURCE_MEM
;
1504 bus
->resource
[i
+1] = res
;
1506 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1507 i
, (unsigned long long)res
->start
,
1508 (unsigned long long)res
->end
,
1509 (unsigned long)res
->flags
);
1512 pr_debug("PCI: PHB MEM offset = %016llx\n",
1513 (unsigned long long)hose
->pci_mem_offset
);
1514 pr_debug("PCI: PHB IO offset = %08lx\n",
1515 (unsigned long)hose
->io_base_virt
- _IO_BASE
);
1519 * Null PCI config access functions, for the case when we can't
1522 #define NULL_PCI_OP(rw, size, type) \
1524 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1526 return PCIBIOS_DEVICE_NOT_FOUND; \
1530 null_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1533 return PCIBIOS_DEVICE_NOT_FOUND
;
1537 null_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1540 return PCIBIOS_DEVICE_NOT_FOUND
;
1543 static struct pci_ops null_pci_ops
= {
1544 .read
= null_read_config
,
1545 .write
= null_write_config
,
1549 * These functions are used early on before PCI scanning is done
1550 * and all of the pci_dev and pci_bus structures have been created.
1552 static struct pci_bus
*
1553 fake_pci_bus(struct pci_controller
*hose
, int busnr
)
1555 static struct pci_bus bus
;
1558 printk(KERN_ERR
"Can't find hose for PCI bus %d!\n", busnr
);
1562 bus
.ops
= hose
? hose
->ops
: &null_pci_ops
;
1566 #define EARLY_PCI_OP(rw, size, type) \
1567 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1568 int devfn, int offset, type value) \
1570 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1571 devfn, offset, value); \
1574 EARLY_PCI_OP(read
, byte
, u8
*)
1575 EARLY_PCI_OP(read
, word
, u16
*)
1576 EARLY_PCI_OP(read
, dword
, u32
*)
1577 EARLY_PCI_OP(write
, byte
, u8
)
1578 EARLY_PCI_OP(write
, word
, u16
)
1579 EARLY_PCI_OP(write
, dword
, u32
)
1581 int early_find_capability(struct pci_controller
*hose
, int bus
, int devfn
,
1584 return pci_bus_find_capability(fake_pci_bus(hose
, bus
), devfn
, cap
);