release/src-rt-6.x.4708/linux/linux-2.6.36/arch/microblaze/kernel/timer.c

   1 /*
   2  * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
   3  * Copyright (C) 2007-2009 PetaLogix
   4  * Copyright (C) 2006 Atmark Techno, Inc.
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License. See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/param.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/profile.h>
  16 #include <linux/irq.h>
  17 #include <linux/delay.h>
  18 #include <linux/sched.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22 #include <linux/clocksource.h>
  23 #include <linux/clockchips.h>
  24 #include <linux/io.h>
  25 #include <linux/bug.h>
  26 #include <asm/cpuinfo.h>
  27 #include <asm/setup.h>
  28 #include <asm/prom.h>
  29 #include <asm/irq.h>
  30 #include <asm/system.h>
  31 #include <linux/cnt32_to_63.h>
  32
  33 #ifdef CONFIG_SELFMOD_TIMER
  34 #include <asm/selfmod.h>
  35 #define TIMER_BASE      BARRIER_BASE_ADDR
  36 #else
  37 static unsigned int timer_baseaddr;
  38 #define TIMER_BASE      timer_baseaddr
  39 #endif
  40
  41 #define TCSR0   (0x00)
  42 #define TLR0    (0x04)
  43 #define TCR0    (0x08)
  44 #define TCSR1   (0x10)
  45 #define TLR1    (0x14)
  46 #define TCR1    (0x18)
  47
  48 #define TCSR_MDT        (1<<0)
  49 #define TCSR_UDT        (1<<1)
  50 #define TCSR_GENT       (1<<2)
  51 #define TCSR_CAPT       (1<<3)
  52 #define TCSR_ARHT       (1<<4)
  53 #define TCSR_LOAD       (1<<5)
  54 #define TCSR_ENIT       (1<<6)
  55 #define TCSR_ENT        (1<<7)
  56 #define TCSR_TINT       (1<<8)
  57 #define TCSR_PWMA       (1<<9)
  58 #define TCSR_ENALL      (1<<10)
  59
  60 static inline void microblaze_timer0_stop(void)
  61 {
  62         out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0) & ~TCSR_ENT);
  63 }
  64
  65 static inline void microblaze_timer0_start_periodic(unsigned long load_val)
  66 {
  67         if (!load_val)
  68                 load_val = 1;
  69         out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */
  70
  71         /* load the initial value */
  72         out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);
  73
  74         /* see timer data sheet for detail
  75          * !ENALL - don't enable 'em all
  76          * !PWMA - disable pwm
  77          * TINT - clear interrupt status
  78          * ENT- enable timer itself
  79          * EINT - enable interrupt
  80          * !LOAD - clear the bit to let go
  81          * ARHT - auto reload
  82          * !CAPT - no external trigger
  83          * !GENT - no external signal
  84          * UDT - set the timer as down counter
  85          * !MDT0 - generate mode
  86          */
  87         out_be32(TIMER_BASE + TCSR0,
  88                         TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
  89 }
  90
  91 static inline void microblaze_timer0_start_oneshot(unsigned long load_val)
  92 {
  93         if (!load_val)
  94                 load_val = 1;
  95         out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */
  96
  97         /* load the initial value */
  98         out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);
  99
 100         out_be32(TIMER_BASE + TCSR0,
 101                         TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
 102 }
 103
 104 static int microblaze_timer_set_next_event(unsigned long delta,
 105                                         struct clock_event_device *dev)
 106 {
 107         pr_debug("%s: next event, delta %x\n", __func__, (u32)delta);
 108         microblaze_timer0_start_oneshot(delta);
 109         return 0;
 110 }
 111
 112 static void microblaze_timer_set_mode(enum clock_event_mode mode,
 113                                 struct clock_event_device *evt)
 114 {
 115         switch (mode) {
 116         case CLOCK_EVT_MODE_PERIODIC:
 117                 printk(KERN_INFO "%s: periodic\n", __func__);
 118                 microblaze_timer0_start_periodic(cpuinfo.freq_div_hz);
 119                 break;
 120         case CLOCK_EVT_MODE_ONESHOT:
 121                 printk(KERN_INFO "%s: oneshot\n", __func__);
 122                 break;
 123         case CLOCK_EVT_MODE_UNUSED:
 124                 printk(KERN_INFO "%s: unused\n", __func__);
 125                 break;
 126         case CLOCK_EVT_MODE_SHUTDOWN:
 127                 printk(KERN_INFO "%s: shutdown\n", __func__);
 128                 microblaze_timer0_stop();
 129                 break;
 130         case CLOCK_EVT_MODE_RESUME:
 131                 printk(KERN_INFO "%s: resume\n", __func__);
 132                 break;
 133         }
 134 }
 135
 136 static struct clock_event_device clockevent_microblaze_timer = {
 137         .name           = "microblaze_clockevent",
 138         .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
 139         .shift          = 8,
 140         .rating         = 300,
 141         .set_next_event = microblaze_timer_set_next_event,
 142         .set_mode       = microblaze_timer_set_mode,
 143 };
 144
 145 static inline void timer_ack(void)
 146 {
 147         out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0));
 148 }
 149
 150 static irqreturn_t timer_interrupt(int irq, void *dev_id)
 151 {
 152         struct clock_event_device *evt = &clockevent_microblaze_timer;
 153 #ifdef CONFIG_HEART_BEAT
 154         heartbeat();
 155 #endif
 156         timer_ack();
 157         evt->event_handler(evt);
 158         return IRQ_HANDLED;
 159 }
 160
 161 static struct irqaction timer_irqaction = {
 162         .handler = timer_interrupt,
 163         .flags = IRQF_DISABLED | IRQF_TIMER,
 164         .name = "timer",
 165         .dev_id = &clockevent_microblaze_timer,
 166 };
 167
 168 static __init void microblaze_clockevent_init(void)
 169 {
 170         clockevent_microblaze_timer.mult =
 171                 div_sc(cpuinfo.cpu_clock_freq, NSEC_PER_SEC,
 172                                 clockevent_microblaze_timer.shift);
 173         clockevent_microblaze_timer.max_delta_ns =
 174                 clockevent_delta2ns((u32)~0, &clockevent_microblaze_timer);
 175         clockevent_microblaze_timer.min_delta_ns =
 176                 clockevent_delta2ns(1, &clockevent_microblaze_timer);
 177         clockevent_microblaze_timer.cpumask = cpumask_of(0);
 178         clockevents_register_device(&clockevent_microblaze_timer);
 179 }
 180
 181 static cycle_t microblaze_read(struct clocksource *cs)
 182 {
 183         /* reading actual value of timer 1 */
 184         return (cycle_t) (in_be32(TIMER_BASE + TCR1));
 185 }
 186
 187 static struct timecounter microblaze_tc = {
 188         .cc = NULL,
 189 };
 190
 191 static cycle_t microblaze_cc_read(const struct cyclecounter *cc)
 192 {
 193         return microblaze_read(NULL);
 194 }
 195
 196 static struct cyclecounter microblaze_cc = {
 197         .read = microblaze_cc_read,
 198         .mask = CLOCKSOURCE_MASK(32),
 199         .shift = 8,
 200 };
 201
 202 int __init init_microblaze_timecounter(void)
 203 {
 204         microblaze_cc.mult = div_sc(cpuinfo.cpu_clock_freq, NSEC_PER_SEC,
 205                                 microblaze_cc.shift);
 206
 207         timecounter_init(&microblaze_tc, &microblaze_cc, sched_clock());
 208
 209         return 0;
 210 }
 211
 212 static struct clocksource clocksource_microblaze = {
 213         .name           = "microblaze_clocksource",
 214         .rating         = 300,
 215         .read           = microblaze_read,
 216         .mask           = CLOCKSOURCE_MASK(32),
 217         .shift          = 8, /* I can shift it */
 218         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 219 };
 220
 221 static int __init microblaze_clocksource_init(void)
 222 {
 223         clocksource_microblaze.mult =
 224                         clocksource_hz2mult(cpuinfo.cpu_clock_freq,
 225                                                 clocksource_microblaze.shift);
 226         if (clocksource_register(&clocksource_microblaze))
 227                 panic("failed to register clocksource");
 228
 229         /* stop timer1 */
 230         out_be32(TIMER_BASE + TCSR1, in_be32(TIMER_BASE + TCSR1) & ~TCSR_ENT);
 231         /* start timer1 - up counting without interrupt */
 232         out_be32(TIMER_BASE + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT);
 233
 234         /* register timecounter - for ftrace support */
 235         init_microblaze_timecounter();
 236         return 0;
 237 }
 238
 239 /*
 240  * We have to protect accesses before timer initialization
 241  * and return 0 for sched_clock function below.
 242  */
 243 static int timer_initialized;
 244
 245 void __init time_init(void)
 246 {
 247         u32 irq, i = 0;
 248         u32 timer_num = 1;
 249         struct device_node *timer = NULL;
 250 #ifdef CONFIG_SELFMOD_TIMER
 251         unsigned int timer_baseaddr = 0;
 252         int arr_func[] = {
 253                                 (int)&microblaze_read,
 254                                 (int)&timer_interrupt,
 255                                 (int)&microblaze_clocksource_init,
 256                                 (int)&microblaze_timer_set_mode,
 257                                 (int)&microblaze_timer_set_next_event,
 258                                 0
 259                         };
 260 #endif
 261         char *timer_list[] = {
 262                                 "xlnx,xps-timer-1.00.a",
 263                                 "xlnx,opb-timer-1.00.b",
 264                                 "xlnx,opb-timer-1.00.a",
 265                                 NULL
 266                         };
 267
 268         for (i = 0; timer_list[i] != NULL; i++) {
 269                 timer = of_find_compatible_node(NULL, NULL, timer_list[i]);
 270                 if (timer)
 271                         break;
 272         }
 273         BUG_ON(!timer);
 274
 275         timer_baseaddr = *(int *) of_get_property(timer, "reg", NULL);
 276         timer_baseaddr = (unsigned long) ioremap(timer_baseaddr, PAGE_SIZE);
 277         irq = *(int *) of_get_property(timer, "interrupts", NULL);
 278         timer_num =
 279                 *(int *) of_get_property(timer, "xlnx,one-timer-only", NULL);
 280         if (timer_num) {
 281                 printk(KERN_EMERG "Please enable two timers in HW\n");
 282                 BUG();
 283         }
 284
 285 #ifdef CONFIG_SELFMOD_TIMER
 286         selfmod_function((int *) arr_func, timer_baseaddr);
 287 #endif
 288         printk(KERN_INFO "%s #0 at 0x%08x, irq=%d\n",
 289                 timer_list[i], timer_baseaddr, irq);
 290
 291         cpuinfo.freq_div_hz = cpuinfo.cpu_clock_freq / HZ;
 292
 293         setup_irq(irq, &timer_irqaction);
 294 #ifdef CONFIG_HEART_BEAT
 295         setup_heartbeat();
 296 #endif
 297         microblaze_clocksource_init();
 298         microblaze_clockevent_init();
 299         timer_initialized = 1;
 300 }
 301
 302 unsigned long long notrace sched_clock(void)
 303 {
 304         if (timer_initialized) {
 305                 struct clocksource *cs = &clocksource_microblaze;
 306                 cycle_t cyc = cnt32_to_63(cs->read(NULL));
 307                 return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
 308         }
 309         return 0;
 310 }