1 /* cmode.S: clock mode management
3 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
4 * Written by David Woodhouse (dwmw2@infradead.org)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
13 #include <linux/sys.h>
14 #include <linux/linkage.h>
15 #include <asm/setup.h>
16 #include <asm/segment.h>
17 #include <asm/ptrace.h>
18 #include <asm/errno.h>
19 #include <asm/cache.h>
20 #include <asm/spr-regs.h>
22 #define __addr_MASK 0xfeff9820 /* interrupt controller mask */
24 #define __addr_SDRAMC 0xfe000400 /* SDRAM controller regs */
25 #define SDRAMC_DSTS 0x28 /* SDRAM status */
26 #define SDRAMC_DSTS_SSI 0x00000001 /* indicates that the SDRAM is in self-refresh mode */
27 #define SDRAMC_DRCN 0x30 /* SDRAM refresh control */
28 #define SDRAMC_DRCN_SR 0x00000001 /* transition SDRAM into self-refresh mode */
29 #define __addr_CLKC 0xfeff9a00
30 #define CLKC_SWCMODE 0x00000008
31 #define __addr_LEDS 0xe1200004
42 ###############################################################################
45 # - void frv_change_cmode(int cmode)
47 ###############################################################################
48 .globl frv_change_cmode
49 .type frv_change_cmode,@function
66 # Shift argument left by 24 bits to fit in SWCMODE register later.
69 # (1) Set '0' in the PSR.ET bit, and prohibit interrupts.
71 andi gr14,#~PSR_ET,gr3
75 # (3) Stop the transfer function of DMAC. Stop all the bus masters
76 # to access SDRAM and the internal resources.
78 # (already done by caller)
80 # (4) Preload a series of following instructions to the instruction
82 li #__cmode_icache_lock_start,gr3
83 li #__cmode_icache_lock_end,gr4
86 addi gr3,#L1_CACHE_BYTES,gr3
90 # Set up addresses in regs for later steps.
91 setlos SDRAMC_DRCN_SR,gr3
98 bra __cmode_icache_lock_start
100 .balign L1_CACHE_BYTES
101 __cmode_icache_lock_start:
103 # (5) Flush the content of all caches by the DCEF instruction.
106 # (6) Execute loading the dummy for SDRAM.
109 # (7) Set '1' to the DRCN.SR bit, and change SDRAM to the
110 # self-refresh mode. Execute the dummy load to all memory
111 # devices set to cacheable on the external bus side in parallel
113 sti gr3,@(gr4,#SDRAMC_DRCN)
115 # (8) Execute memory barrier instruction (MEMBAR).
118 # (9) Read the DSTS register repeatedly until '1' stands in the
120 1: ldi @(gr4,#SDRAMC_DSTS),gr3
121 andicc gr3,#SDRAMC_DSTS_SSI,gr3,icc0
124 # (10) Execute memory barrier instruction (MEMBAR).
127 # (11) Set the value of CMODE that you want to change to
129 sti gr8,@(gr5,#CLKC_SWCMODE)
131 # (12) Set '1' to the CLKC.SWEN bit. In that case, do not change
132 # fields other than SWEN of the CLKC register.
134 # (13) Execute the instruction just after the memory barrier
135 # instruction that executes the self-loop 256 times. (Meanwhile,
136 # the CMODE switch is done.)
139 2: subicc gr7,#1,gr7,icc0
144 # (14) Release the self-refresh of SDRAM.
145 sti gr0,@(gr4,#SDRAMC_DRCN)
148 3: ldi @(gr4,#SDRAMC_DSTS),gr3
149 andicc gr3,#SDRAMC_DSTS_SSI,gr3,icc0
153 __cmode_icache_lock_end:
155 li #__cmode_icache_lock_start,gr3
156 li #__cmode_icache_lock_end,gr4
159 addi gr3,#L1_CACHE_BYTES,gr3
163 # (16) Set 1' in the PSR.ET bit, and permit interrupt.
168 .size frv_change_cmode, .-frv_change_cmode