2 * arch/cris/arch-v32/drivers/nandflash.c
6 * Derived from drivers/mtd/nand/spia.c
7 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #include <linux/slab.h>
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/mtd/partitions.h>
21 #include <arch/memmap.h>
22 #include <hwregs/reg_map.h>
23 #include <hwregs/reg_rdwr.h>
24 #include <hwregs/gio_defs.h>
25 #include <hwregs/bif_core_defs.h>
33 struct mtd_info_wrapper
{
35 struct nand_chip chip
;
38 /* Bitmask for control pins */
39 #define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT))
41 /* Bitmask for mtd nand control bits */
42 #define CTRL_BITMASK (NAND_NCE | NAND_CLE | NAND_ALE)
45 static struct mtd_info
*crisv32_mtd
;
47 * hardware specific access to control-lines
49 static void crisv32_hwcontrol(struct mtd_info
*mtd
, int cmd
,
53 reg_gio_rw_pa_dout dout
;
54 struct nand_chip
*this = mtd
->priv
;
56 local_irq_save(flags
);
58 /* control bits change */
59 if (ctrl
& NAND_CTRL_CHANGE
) {
60 dout
= REG_RD(gio
, regi_gio
, rw_pa_dout
);
61 dout
.data
&= ~PIN_BITMASK
;
63 #if (CE_BIT == 4 && NAND_NCE == CLE_BIT == 5 && NAND_CLE == 2 && ALE_BIT == 6 && \
65 /* Pins in same order as control bits, but shifted.
66 * Optimize for this case; works for 2.6.18 */
67 dout
.data
|= ((ctrl
& CTRL_BITMASK
) ^ NAND_NCE
) << CE_BIT
;
70 if (!(ctrl
& NAND_NCE
))
71 dout
.data
|= (1 << CE_BIT
);
73 dout
.data
|= (1 << CLE_BIT
);
75 dout
.data
|= (1 << ALE_BIT
);
77 REG_WR(gio
, regi_gio
, rw_pa_dout
, dout
);
81 if (cmd
!= NAND_CMD_NONE
)
82 writeb(cmd
, this->IO_ADDR_W
);
84 local_irq_restore(flags
);
88 * read device ready pin
90 static int crisv32_device_ready(struct mtd_info
*mtd
)
92 reg_gio_r_pa_din din
= REG_RD(gio
, regi_gio
, r_pa_din
);
93 return ((din
.data
& (1 << BY_BIT
)) >> BY_BIT
);
97 * Main initialization routine
99 struct mtd_info
*__init
crisv32_nand_flash_probe(void)
101 void __iomem
*read_cs
;
102 void __iomem
*write_cs
;
104 reg_bif_core_rw_grp3_cfg bif_cfg
= REG_RD(bif_core
, regi_bif_core
,
106 reg_gio_rw_pa_oe pa_oe
= REG_RD(gio
, regi_gio
, rw_pa_oe
);
107 struct mtd_info_wrapper
*wrapper
;
108 struct nand_chip
*this;
111 /* Allocate memory for MTD device structure and private data */
112 wrapper
= kzalloc(sizeof(struct mtd_info_wrapper
), GFP_KERNEL
);
114 printk(KERN_ERR
"Unable to allocate CRISv32 NAND MTD "
115 "device structure.\n");
120 read_cs
= ioremap(MEM_CSP0_START
| MEM_NON_CACHEABLE
, 8192);
121 write_cs
= ioremap(MEM_CSP1_START
| MEM_NON_CACHEABLE
, 8192);
123 if (!read_cs
|| !write_cs
) {
124 printk(KERN_ERR
"CRISv32 NAND ioremap failed\n");
129 /* Get pointer to private data */
130 this = &wrapper
->chip
;
131 crisv32_mtd
= &wrapper
->info
;
133 pa_oe
.oe
|= 1 << CE_BIT
;
134 pa_oe
.oe
|= 1 << ALE_BIT
;
135 pa_oe
.oe
|= 1 << CLE_BIT
;
136 pa_oe
.oe
&= ~(1 << BY_BIT
);
137 REG_WR(gio
, regi_gio
, rw_pa_oe
, pa_oe
);
139 bif_cfg
.gated_csp0
= regk_bif_core_rd
;
140 bif_cfg
.gated_csp1
= regk_bif_core_wr
;
141 REG_WR(bif_core
, regi_bif_core
, rw_grp3_cfg
, bif_cfg
);
143 /* Link the private data with the MTD structure */
144 crisv32_mtd
->priv
= this;
146 /* Set address of NAND IO lines */
147 this->IO_ADDR_R
= read_cs
;
148 this->IO_ADDR_W
= write_cs
;
149 this->cmd_ctrl
= crisv32_hwcontrol
;
150 this->dev_ready
= crisv32_device_ready
;
151 /* 20 us command delay time */
152 this->chip_delay
= 20;
153 this->ecc
.mode
= NAND_ECC_SOFT
;
155 /* Enable the following for a flash based bad block table */
156 /* this->options = NAND_USE_FLASH_BBT; */
158 /* Scan to find existance of the device */
159 if (nand_scan(crisv32_mtd
, 1)) {
167 iounmap((void *)read_cs
);
168 iounmap((void *)write_cs
);