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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / cris / arch-v32 / drivers / mach-a3 / gpio.c
blob67ddc9ceedd866268e01d76bfce159e2a9e9d3ec
1 /*
2 * Artec-3 general port I/O device
3 *
4 * Copyright (c) 2007 Axis Communications AB
5 *
6 * Authors: Bjorn Wesen (initial version)
7 * Ola Knutsson (LED handling)
8 * Johan Adolfsson (read/set directions, write, port G,
9 * port to ETRAX FS.
10 * Ricard Wanderlof (PWM for Artpec-3)
11 *
12 */
13
14 #include <linux/module.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <linux/ioport.h>
18 #include <linux/errno.h>
19 #include <linux/kernel.h>
20 #include <linux/fs.h>
21 #include <linux/string.h>
22 #include <linux/poll.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/spinlock.h>
26 #include <linux/smp_lock.h>
27
28 #include <asm/etraxgpio.h>
29 #include <hwregs/reg_map.h>
30 #include <hwregs/reg_rdwr.h>
31 #include <hwregs/gio_defs.h>
32 #include <hwregs/intr_vect_defs.h>
33 #include <asm/io.h>
34 #include <asm/system.h>
35 #include <asm/irq.h>
36 #include <mach/pinmux.h>
37
38 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
39 #include "../i2c.h"
40
41 #define VIRT_I2C_ADDR 0x40
42 #endif
43
44 /* The following gio ports on ARTPEC-3 is available:
45 * pa 32 bits
46 * pb 32 bits
47 * pc 16 bits
48 * each port has a rw_px_dout, r_px_din and rw_px_oe register.
49 */
50
51 #define GPIO_MAJOR 120 /* experimental MAJOR number */
52
53 #define I2C_INTERRUPT_BITS 0x300 /* i2c0_done and i2c1_done bits */
54
55 #define D(x)
56
57 #define DP(x)
58
59 static char gpio_name[] = "etrax gpio";
60
61 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
62 static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
63 unsigned long arg);
64 #endif
65 static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
66 static ssize_t gpio_write(struct file *file, const char __user *buf,
67 size_t count, loff_t *off);
68 static int gpio_open(struct inode *inode, struct file *filp);
69 static int gpio_release(struct inode *inode, struct file *filp);
70 static unsigned int gpio_poll(struct file *filp,
71 struct poll_table_struct *wait);
72
73 /* private data per open() of this driver */
74
75 struct gpio_private {
76 struct gpio_private *next;
77 /* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */
78 unsigned char clk_mask;
79 unsigned char data_mask;
80 unsigned char write_msb;
81 unsigned char pad1;
82 /* These fields are generic */
83 unsigned long highalarm, lowalarm;
84 wait_queue_head_t alarm_wq;
85 int minor;
86 };
87
88 static void gpio_set_alarm(struct gpio_private *priv);
89 static int gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
90 static int gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd,
91 unsigned long arg);
92
93
94 /* linked list of alarms to check for */
95
96 static struct gpio_private *alarmlist;
97
98 static int wanted_interrupts;
99
100 static DEFINE_SPINLOCK(gpio_lock);
101
102 #define NUM_PORTS (GPIO_MINOR_LAST+1)
103 #define GIO_REG_RD_ADDR(reg) \
104 (unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
105 #define GIO_REG_WR_ADDR(reg) \
106 (unsigned long *)(regi_gio + REG_WR_ADDR_gio_##reg)
107 static unsigned long led_dummy;
108 static unsigned long port_d_dummy; /* Only input on Artpec-3 */
109 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
110 static unsigned long port_e_dummy; /* Non existent on Artpec-3 */
111 static unsigned long virtual_dummy;
112 static unsigned long virtual_rw_pv_oe = CONFIG_ETRAX_DEF_GIO_PV_OE;
113 static unsigned short cached_virtual_gpio_read;
114 #endif
115
116 static unsigned long *data_out[NUM_PORTS] = {
117 GIO_REG_WR_ADDR(rw_pa_dout),
118 GIO_REG_WR_ADDR(rw_pb_dout),
119 &led_dummy,
120 GIO_REG_WR_ADDR(rw_pc_dout),
121 &port_d_dummy,
122 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
123 &port_e_dummy,
124 &virtual_dummy,
125 #endif
126 };
127
128 static unsigned long *data_in[NUM_PORTS] = {
129 GIO_REG_RD_ADDR(r_pa_din),
130 GIO_REG_RD_ADDR(r_pb_din),
131 &led_dummy,
132 GIO_REG_RD_ADDR(r_pc_din),
133 GIO_REG_RD_ADDR(r_pd_din),
134 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
135 &port_e_dummy,
136 &virtual_dummy,
137 #endif
138 };
139
140 static unsigned long changeable_dir[NUM_PORTS] = {
141 CONFIG_ETRAX_PA_CHANGEABLE_DIR,
142 CONFIG_ETRAX_PB_CHANGEABLE_DIR,
143 0,
144 CONFIG_ETRAX_PC_CHANGEABLE_DIR,
145 0,
146 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
147 0,
148 CONFIG_ETRAX_PV_CHANGEABLE_DIR,
149 #endif
150 };
151
152 static unsigned long changeable_bits[NUM_PORTS] = {
153 CONFIG_ETRAX_PA_CHANGEABLE_BITS,
154 CONFIG_ETRAX_PB_CHANGEABLE_BITS,
155 0,
156 CONFIG_ETRAX_PC_CHANGEABLE_BITS,
157 0,
158 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
159 0,
160 CONFIG_ETRAX_PV_CHANGEABLE_BITS,
161 #endif
162 };
163
164 static unsigned long *dir_oe[NUM_PORTS] = {
165 GIO_REG_WR_ADDR(rw_pa_oe),
166 GIO_REG_WR_ADDR(rw_pb_oe),
167 &led_dummy,
168 GIO_REG_WR_ADDR(rw_pc_oe),
169 &port_d_dummy,
170 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
171 &port_e_dummy,
172 &virtual_rw_pv_oe,
173 #endif
174 };
175
176 static void gpio_set_alarm(struct gpio_private *priv)
177 {
178 int bit;
179 int intr_cfg;
180 int mask;
181 int pins;
182 unsigned long flags;
183
184 spin_lock_irqsave(&gpio_lock, flags);
185 intr_cfg = REG_RD_INT(gio, regi_gio, rw_intr_cfg);
186 pins = REG_RD_INT(gio, regi_gio, rw_intr_pins);
187 mask = REG_RD_INT(gio, regi_gio, rw_intr_mask) & I2C_INTERRUPT_BITS;
188
189 for (bit = 0; bit < 32; bit++) {
190 int intr = bit % 8;
191 int pin = bit / 8;
192 if (priv->minor < GPIO_MINOR_LEDS)
193 pin += priv->minor * 4;
194 else
195 pin += (priv->minor - 1) * 4;
196
197 if (priv->highalarm & (1<<bit)) {
198 intr_cfg |= (regk_gio_hi << (intr * 3));
199 mask |= 1 << intr;
200 wanted_interrupts = mask & 0xff;
201 pins |= pin << (intr * 4);
202 } else if (priv->lowalarm & (1<<bit)) {
203 intr_cfg |= (regk_gio_lo << (intr * 3));
204 mask |= 1 << intr;
205 wanted_interrupts = mask & 0xff;
206 pins |= pin << (intr * 4);
207 }
208 }
209
210 REG_WR_INT(gio, regi_gio, rw_intr_cfg, intr_cfg);
211 REG_WR_INT(gio, regi_gio, rw_intr_pins, pins);
212 REG_WR_INT(gio, regi_gio, rw_intr_mask, mask);
213
214 spin_unlock_irqrestore(&gpio_lock, flags);
215 }
216
217 static unsigned int gpio_poll(struct file *file, struct poll_table_struct *wait)
218 {
219 unsigned int mask = 0;
220 struct gpio_private *priv = file->private_data;
221 unsigned long data;
222 unsigned long tmp;
223
224 if (priv->minor >= GPIO_MINOR_PWM0 &&
225 priv->minor <= GPIO_MINOR_LAST_PWM)
226 return 0;
227
228 poll_wait(file, &priv->alarm_wq, wait);
229 if (priv->minor <= GPIO_MINOR_D) {
230 data = readl(data_in[priv->minor]);
231 REG_WR_INT(gio, regi_gio, rw_ack_intr, wanted_interrupts);
232 tmp = REG_RD_INT(gio, regi_gio, rw_intr_mask);
233 tmp &= I2C_INTERRUPT_BITS;
234 tmp |= wanted_interrupts;
235 REG_WR_INT(gio, regi_gio, rw_intr_mask, tmp);
236 } else
237 return 0;
238
239 if ((data & priv->highalarm) || (~data & priv->lowalarm))
240 mask = POLLIN|POLLRDNORM;
241
242 DP(printk(KERN_DEBUG "gpio_poll ready: mask 0x%08X\n", mask));
243 return mask;
244 }
245
246 static irqreturn_t gpio_interrupt(int irq, void *dev_id)
247 {
248 reg_gio_rw_intr_mask intr_mask;
249 reg_gio_r_masked_intr masked_intr;
250 reg_gio_rw_ack_intr ack_intr;
251 unsigned long flags;
252 unsigned long tmp;
253 unsigned long tmp2;
254 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
255 unsigned char enable_gpiov_ack = 0;
256 #endif
257
258 /* Find what PA interrupts are active */
259 masked_intr = REG_RD(gio, regi_gio, r_masked_intr);
260 tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr);
261
262 /* Find those that we have enabled */
263 spin_lock_irqsave(&gpio_lock, flags);
264 tmp &= wanted_interrupts;
265 spin_unlock_irqrestore(&gpio_lock, flags);
266
267 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
268 /* Something changed on virtual GPIO. Interrupt is acked by
269 * reading the device.
270 */
271 if (tmp & (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN)) {
272 i2c_read(VIRT_I2C_ADDR, (void *)&cached_virtual_gpio_read,
273 sizeof(cached_virtual_gpio_read));
274 enable_gpiov_ack = 1;
275 }
276 #endif
277
278 /* Ack them */
279 ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp);
280 REG_WR(gio, regi_gio, rw_ack_intr, ack_intr);
281
282 /* Disable those interrupts.. */
283 intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
284 tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask);
285 tmp2 &= ~tmp;
286 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
287 /* Do not disable interrupt on virtual GPIO. Changes on virtual
288 * pins are only noticed by an interrupt.
289 */
290 if (enable_gpiov_ack)
291 tmp2 |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
292 #endif
293 intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2);
294 REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
295
296 return IRQ_RETVAL(tmp);
297 }
298
299 static void gpio_write_bit(unsigned long *port, unsigned char data, int bit,
300 unsigned char clk_mask, unsigned char data_mask)
301 {
302 unsigned long shadow = readl(port) & ~clk_mask;
303 writel(shadow, port);
304 if (data & 1 << bit)
305 shadow |= data_mask;
306 else
307 shadow &= ~data_mask;
308 writel(shadow, port);
309 /* For FPGA: min 5.0ns (DCC) before CCLK high */
310 shadow |= clk_mask;
311 writel(shadow, port);
312 }
313
314 static void gpio_write_byte(struct gpio_private *priv, unsigned long *port,
315 unsigned char data)
316 {
317 int i;
318
319 if (priv->write_msb)
320 for (i = 7; i >= 0; i--)
321 gpio_write_bit(port, data, i, priv->clk_mask,
322 priv->data_mask);
323 else
324 for (i = 0; i <= 7; i++)
325 gpio_write_bit(port, data, i, priv->clk_mask,
326 priv->data_mask);
327 }
328
329
330 static ssize_t gpio_write(struct file *file, const char __user *buf,
331 size_t count, loff_t *off)
332 {
333 struct gpio_private *priv = file->private_data;
334 unsigned long flags;
335 ssize_t retval = count;
336 /* Only bits 0-7 may be used for write operations but allow all
337 devices except leds... */
338 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
339 if (priv->minor == GPIO_MINOR_V)
340 return -EFAULT;
341 #endif
342 if (priv->minor == GPIO_MINOR_LEDS)
343 return -EFAULT;
344
345 if (priv->minor >= GPIO_MINOR_PWM0 &&
346 priv->minor <= GPIO_MINOR_LAST_PWM)
347 return -EFAULT;
348
349 if (!access_ok(VERIFY_READ, buf, count))
350 return -EFAULT;
351
352 /* It must have been configured using the IO_CFG_WRITE_MODE */
353 /* Perhaps a better error code? */
354 if (priv->clk_mask == 0 || priv->data_mask == 0)
355 return -EPERM;
356
357 D(printk(KERN_DEBUG "gpio_write: %lu to data 0x%02X clk 0x%02X "
358 "msb: %i\n",
359 count, priv->data_mask, priv->clk_mask, priv->write_msb));
360
361 spin_lock_irqsave(&gpio_lock, flags);
362
363 while (count--)
364 gpio_write_byte(priv, data_out[priv->minor], *buf++);
365
366 spin_unlock_irqrestore(&gpio_lock, flags);
367 return retval;
368 }
369
370 static int gpio_open(struct inode *inode, struct file *filp)
371 {
372 struct gpio_private *priv;
373 int p = iminor(inode);
374
375 if (p > GPIO_MINOR_LAST_PWM ||
376 (p > GPIO_MINOR_LAST && p < GPIO_MINOR_PWM0))
377 return -EINVAL;
378
379 priv = kmalloc(sizeof(struct gpio_private), GFP_KERNEL);
380
381 if (!priv)
382 return -ENOMEM;
383
384 lock_kernel();
385 memset(priv, 0, sizeof(*priv));
386
387 priv->minor = p;
388 filp->private_data = priv;
389
390 /* initialize the io/alarm struct, not for PWM ports though */
391 if (p <= GPIO_MINOR_LAST) {
392
393 priv->clk_mask = 0;
394 priv->data_mask = 0;
395 priv->highalarm = 0;
396 priv->lowalarm = 0;
397
398 init_waitqueue_head(&priv->alarm_wq);
399
400 /* link it into our alarmlist */
401 spin_lock_irq(&gpio_lock);
402 priv->next = alarmlist;
403 alarmlist = priv;
404 spin_unlock_irq(&gpio_lock);
405 }
406
407 unlock_kernel();
408 return 0;
409 }
410
411 static int gpio_release(struct inode *inode, struct file *filp)
412 {
413 struct gpio_private *p;
414 struct gpio_private *todel;
415 /* local copies while updating them: */
416 unsigned long a_high, a_low;
417
418 /* prepare to free private structure */
419 todel = filp->private_data;
420
421 /* unlink from alarmlist - only for non-PWM ports though */
422 if (todel->minor <= GPIO_MINOR_LAST) {
423 spin_lock_irq(&gpio_lock);
424 p = alarmlist;
425
426 if (p == todel)
427 alarmlist = todel->next;
428 else {
429 while (p->next != todel)
430 p = p->next;
431 p->next = todel->next;
432 }
433
434 /* Check if there are still any alarms set */
435 p = alarmlist;
436 a_high = 0;
437 a_low = 0;
438 while (p) {
439 if (p->minor == GPIO_MINOR_A) {
440 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
441 p->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
442 #endif
443 a_high |= p->highalarm;
444 a_low |= p->lowalarm;
445 }
446
447 p = p->next;
448 }
449
450 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
451 /* Variable 'a_low' needs to be set here again
452 * to ensure that interrupt for virtual GPIO is handled.
453 */
454 a_low |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
455 #endif
456
457 spin_unlock_irq(&gpio_lock);
458 }
459 kfree(todel);
460
461 return 0;
462 }
463
464 /* Main device API. ioctl's to read/set/clear bits, as well as to
465 * set alarms to wait for using a subsequent select().
466 */
467
468 inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg)
469 {
470 /* Set direction 0=unchanged 1=input,
471 * return mask with 1=input
472 */
473 unsigned long flags;
474 unsigned long dir_shadow;
475
476 spin_lock_irqsave(&gpio_lock, flags);
477
478 dir_shadow = readl(dir_oe[priv->minor]) &
479 ~(arg & changeable_dir[priv->minor]);
480 writel(dir_shadow, dir_oe[priv->minor]);
481
482 spin_unlock_irqrestore(&gpio_lock, flags);
483
484 if (priv->minor == GPIO_MINOR_C)
485 dir_shadow ^= 0xFFFF; /* Only 16 bits */
486 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
487 else if (priv->minor == GPIO_MINOR_V)
488 dir_shadow ^= 0xFFFF; /* Only 16 bits */
489 #endif
490 else
491 dir_shadow ^= 0xFFFFFFFF; /* PA, PB and PD 32 bits */
492
493 return dir_shadow;
494
495 } /* setget_input */
496
497 static inline unsigned long setget_output(struct gpio_private *priv,
498 unsigned long arg)
499 {
500 unsigned long flags;
501 unsigned long dir_shadow;
502
503 spin_lock_irqsave(&gpio_lock, flags);
504
505 dir_shadow = readl(dir_oe[priv->minor]) |
506 (arg & changeable_dir[priv->minor]);
507 writel(dir_shadow, dir_oe[priv->minor]);
508
509 spin_unlock_irqrestore(&gpio_lock, flags);
510 return dir_shadow;
511 } /* setget_output */
512
513 static long gpio_ioctl_unlocked(struct file *file,
514 unsigned int cmd, unsigned long arg)
515 {
516 unsigned long flags;
517 unsigned long val;
518 unsigned long shadow;
519 struct gpio_private *priv = file->private_data;
520
521 if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
522 return -ENOTTY;
523
524 /* Check for special ioctl handlers first */
525
526 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
527 if (priv->minor == GPIO_MINOR_V)
528 return virtual_gpio_ioctl(file, cmd, arg);
529 #endif
530
531 if (priv->minor == GPIO_MINOR_LEDS)
532 return gpio_leds_ioctl(cmd, arg);
533
534 if (priv->minor >= GPIO_MINOR_PWM0 &&
535 priv->minor <= GPIO_MINOR_LAST_PWM)
536 return gpio_pwm_ioctl(priv, cmd, arg);
537
538 switch (_IOC_NR(cmd)) {
539 case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
540 /* Read the port. */
541 return readl(data_in[priv->minor]);
542 case IO_SETBITS:
543 spin_lock_irqsave(&gpio_lock, flags);
544 /* Set changeable bits with a 1 in arg. */
545 shadow = readl(data_out[priv->minor]) |
546 (arg & changeable_bits[priv->minor]);
547 writel(shadow, data_out[priv->minor]);
548 spin_unlock_irqrestore(&gpio_lock, flags);
549 break;
550 case IO_CLRBITS:
551 spin_lock_irqsave(&gpio_lock, flags);
552 /* Clear changeable bits with a 1 in arg. */
553 shadow = readl(data_out[priv->minor]) &
554 ~(arg & changeable_bits[priv->minor]);
555 writel(shadow, data_out[priv->minor]);
556 spin_unlock_irqrestore(&gpio_lock, flags);
557 break;
558 case IO_HIGHALARM:
559 /* Set alarm when bits with 1 in arg go high. */
560 priv->highalarm |= arg;
561 gpio_set_alarm(priv);
562 break;
563 case IO_LOWALARM:
564 /* Set alarm when bits with 1 in arg go low. */
565 priv->lowalarm |= arg;
566 gpio_set_alarm(priv);
567 break;
568 case IO_CLRALARM:
569 /* Clear alarm for bits with 1 in arg. */
570 priv->highalarm &= ~arg;
571 priv->lowalarm &= ~arg;
572 gpio_set_alarm(priv);
573 break;
574 case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
575 /* Read direction 0=input 1=output */
576 return readl(dir_oe[priv->minor]);
577
578 case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
579 /* Set direction 0=unchanged 1=input,
580 * return mask with 1=input
581 */
582 return setget_input(priv, arg);
583
584 case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
585 /* Set direction 0=unchanged 1=output,
586 * return mask with 1=output
587 */
588 return setget_output(priv, arg);
589
590 case IO_CFG_WRITE_MODE:
591 {
592 int res = -EPERM;
593 unsigned long dir_shadow, clk_mask, data_mask, write_msb;
594
595 clk_mask = arg & 0xFF;
596 data_mask = (arg >> 8) & 0xFF;
597 write_msb = (arg >> 16) & 0x01;
598
599 /* Check if we're allowed to change the bits and
600 * the direction is correct
601 */
602 spin_lock_irqsave(&gpio_lock, flags);
603 dir_shadow = readl(dir_oe[priv->minor]);
604 if ((clk_mask & changeable_bits[priv->minor]) &&
605 (data_mask & changeable_bits[priv->minor]) &&
606 (clk_mask & dir_shadow) &&
607 (data_mask & dir_shadow)) {
608 priv->clk_mask = clk_mask;
609 priv->data_mask = data_mask;
610 priv->write_msb = write_msb;
611 res = 0;
612 }
613 spin_unlock_irqrestore(&gpio_lock, flags);
614
615 return res;
616 }
617 case IO_READ_INBITS:
618 /* *arg is result of reading the input pins */
619 val = readl(data_in[priv->minor]);
620 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
621 return -EFAULT;
622 return 0;
623 case IO_READ_OUTBITS:
624 /* *arg is result of reading the output shadow */
625 val = *data_out[priv->minor];
626 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
627 return -EFAULT;
628 break;
629 case IO_SETGET_INPUT:
630 /* bits set in *arg is set to input,
631 * *arg updated with current input pins.
632 */
633 if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
634 return -EFAULT;
635 val = setget_input(priv, val);
636 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
637 return -EFAULT;
638 break;
639 case IO_SETGET_OUTPUT:
640 /* bits set in *arg is set to output,
641 * *arg updated with current output pins.
642 */
643 if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
644 return -EFAULT;
645 val = setget_output(priv, val);
646 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
647 return -EFAULT;
648 break;
649 default:
650 return -EINVAL;
651 } /* switch */
652
653 return 0;
654 }
655
656 static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
657 {
658 long ret;
659
660 lock_kernel();
661 ret = gpio_ioctl_unlocked(file, cmd, arg);
662 unlock_kernel();
663
664 return ret;
665 }
666
667 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
668 static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
669 unsigned long arg)
670 {
671 unsigned long flags;
672 unsigned short val;
673 unsigned short shadow;
674 struct gpio_private *priv = file->private_data;
675
676 switch (_IOC_NR(cmd)) {
677 case IO_SETBITS:
678 spin_lock_irqsave(&gpio_lock, flags);
679 /* Set changeable bits with a 1 in arg. */
680 i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
681 shadow |= ~readl(dir_oe[priv->minor]) |
682 (arg & changeable_bits[priv->minor]);
683 i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
684 spin_unlock_irqrestore(&gpio_lock, flags);
685 break;
686 case IO_CLRBITS:
687 spin_lock_irqsave(&gpio_lock, flags);
688 /* Clear changeable bits with a 1 in arg. */
689 i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
690 shadow |= ~readl(dir_oe[priv->minor]) &
691 ~(arg & changeable_bits[priv->minor]);
692 i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
693 spin_unlock_irqrestore(&gpio_lock, flags);
694 break;
695 case IO_HIGHALARM:
696 /* Set alarm when bits with 1 in arg go high. */
697 priv->highalarm |= arg;
698 break;
699 case IO_LOWALARM:
700 /* Set alarm when bits with 1 in arg go low. */
701 priv->lowalarm |= arg;
702 break;
703 case IO_CLRALARM:
704 /* Clear alarm for bits with 1 in arg. */
705 priv->highalarm &= ~arg;
706 priv->lowalarm &= ~arg;
707 break;
708 case IO_CFG_WRITE_MODE:
709 {
710 unsigned long dir_shadow;
711 dir_shadow = readl(dir_oe[priv->minor]);
712
713 priv->clk_mask = arg & 0xFF;
714 priv->data_mask = (arg >> 8) & 0xFF;
715 priv->write_msb = (arg >> 16) & 0x01;
716 /* Check if we're allowed to change the bits and
717 * the direction is correct
718 */
719 if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
720 (priv->data_mask & changeable_bits[priv->minor]) &&
721 (priv->clk_mask & dir_shadow) &&
722 (priv->data_mask & dir_shadow))) {
723 priv->clk_mask = 0;
724 priv->data_mask = 0;
725 return -EPERM;
726 }
727 break;
728 }
729 case IO_READ_INBITS:
730 /* *arg is result of reading the input pins */
731 val = cached_virtual_gpio_read & ~readl(dir_oe[priv->minor]);
732 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
733 return -EFAULT;
734 return 0;
735
736 case IO_READ_OUTBITS:
737 /* *arg is result of reading the output shadow */
738 i2c_read(VIRT_I2C_ADDR, (void *)&val, sizeof(val));
739 val &= readl(dir_oe[priv->minor]);
740 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
741 return -EFAULT;
742 break;
743 case IO_SETGET_INPUT:
744 {
745 /* bits set in *arg is set to input,
746 * *arg updated with current input pins.
747 */
748 unsigned short input_mask = ~readl(dir_oe[priv->minor]);
749 if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
750 return -EFAULT;
751 val = setget_input(priv, val);
752 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
753 return -EFAULT;
754 if ((input_mask & val) != input_mask) {
755 /* Input pins changed. All ports desired as input
756 * should be set to logic 1.
757 */
758 unsigned short change = input_mask ^ val;
759 i2c_read(VIRT_I2C_ADDR, (void *)&shadow,
760 sizeof(shadow));
761 shadow &= ~change;
762 shadow |= val;
763 i2c_write(VIRT_I2C_ADDR, (void *)&shadow,
764 sizeof(shadow));
765 }
766 break;
767 }
768 case IO_SETGET_OUTPUT:
769 /* bits set in *arg is set to output,
770 * *arg updated with current output pins.
771 */
772 if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
773 return -EFAULT;
774 val = setget_output(priv, val);
775 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
776 return -EFAULT;
777 break;
778 default:
779 return -EINVAL;
780 } /* switch */
781 return 0;
782 }
783 #endif /* CONFIG_ETRAX_VIRTUAL_GPIO */
784
785 static int gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
786 {
787 unsigned char green;
788 unsigned char red;
789
790 switch (_IOC_NR(cmd)) {
791 case IO_LEDACTIVE_SET:
792 green = ((unsigned char) arg) & 1;
793 red = (((unsigned char) arg) >> 1) & 1;
794 CRIS_LED_ACTIVE_SET_G(green);
795 CRIS_LED_ACTIVE_SET_R(red);
796 break;
797
798 default:
799 return -EINVAL;
800 } /* switch */
801
802 return 0;
803 }
804
805 static int gpio_pwm_set_mode(unsigned long arg, int pwm_port)
806 {
807 int pinmux_pwm = pinmux_pwm0 + pwm_port;
808 int mode;
809 reg_gio_rw_pwm0_ctrl rw_pwm_ctrl = {
810 .ccd_val = 0,
811 .ccd_override = regk_gio_no,
812 .mode = regk_gio_no
813 };
814 int allocstatus;
815
816 if (get_user(mode, &((struct io_pwm_set_mode *) arg)->mode))
817 return -EFAULT;
818 rw_pwm_ctrl.mode = mode;
819 if (mode != PWM_OFF)
820 allocstatus = crisv32_pinmux_alloc_fixed(pinmux_pwm);
821 else
822 allocstatus = crisv32_pinmux_dealloc_fixed(pinmux_pwm);
823 if (allocstatus)
824 return allocstatus;
825 REG_WRITE(reg_gio_rw_pwm0_ctrl, REG_ADDR(gio, regi_gio, rw_pwm0_ctrl) +
826 12 * pwm_port, rw_pwm_ctrl);
827 return 0;
828 }
829
830 static int gpio_pwm_set_period(unsigned long arg, int pwm_port)
831 {
832 struct io_pwm_set_period periods;
833 reg_gio_rw_pwm0_var rw_pwm_widths;
834
835 if (copy_from_user(&periods, (void __user *)arg, sizeof(periods)))
836 return -EFAULT;
837 if (periods.lo > 8191 || periods.hi > 8191)
838 return -EINVAL;
839 rw_pwm_widths.lo = periods.lo;
840 rw_pwm_widths.hi = periods.hi;
841 REG_WRITE(reg_gio_rw_pwm0_var, REG_ADDR(gio, regi_gio, rw_pwm0_var) +
842 12 * pwm_port, rw_pwm_widths);
843 return 0;
844 }
845
846 static int gpio_pwm_set_duty(unsigned long arg, int pwm_port)
847 {
848 unsigned int duty;
849 reg_gio_rw_pwm0_data rw_pwm_duty;
850
851 if (get_user(duty, &((struct io_pwm_set_duty *) arg)->duty))
852 return -EFAULT;
853 if (duty > 255)
854 return -EINVAL;
855 rw_pwm_duty.data = duty;
856 REG_WRITE(reg_gio_rw_pwm0_data, REG_ADDR(gio, regi_gio, rw_pwm0_data) +
857 12 * pwm_port, rw_pwm_duty);
858 return 0;
859 }
860
861 static int gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd,
862 unsigned long arg)
863 {
864 int pwm_port = priv->minor - GPIO_MINOR_PWM0;
865
866 switch (_IOC_NR(cmd)) {
867 case IO_PWM_SET_MODE:
868 return gpio_pwm_set_mode(arg, pwm_port);
869 case IO_PWM_SET_PERIOD:
870 return gpio_pwm_set_period(arg, pwm_port);
871 case IO_PWM_SET_DUTY:
872 return gpio_pwm_set_duty(arg, pwm_port);
873 default:
874 return -EINVAL;
875 }
876 return 0;
877 }
878
879 static const struct file_operations gpio_fops = {
880 .owner = THIS_MODULE,
881 .poll = gpio_poll,
882 .unlocked_ioctl = gpio_ioctl,
883 .write = gpio_write,
884 .open = gpio_open,
885 .release = gpio_release,
886 };
887
888 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
889 static void __init virtual_gpio_init(void)
890 {
891 reg_gio_rw_intr_cfg intr_cfg;
892 reg_gio_rw_intr_mask intr_mask;
893 unsigned short shadow;
894
895 shadow = ~virtual_rw_pv_oe; /* Input ports should be set to logic 1 */
896 shadow |= CONFIG_ETRAX_DEF_GIO_PV_OUT;
897 i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
898
899 /* Set interrupt mask and on what state the interrupt shall trigger.
900 * For virtual gpio the interrupt shall trigger on logic '0'.
901 */
902 intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
903 intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
904
905 switch (CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN) {
906 case 0:
907 intr_cfg.pa0 = regk_gio_lo;
908 intr_mask.pa0 = regk_gio_yes;
909 break;
910 case 1:
911 intr_cfg.pa1 = regk_gio_lo;
912 intr_mask.pa1 = regk_gio_yes;
913 break;
914 case 2:
915 intr_cfg.pa2 = regk_gio_lo;
916 intr_mask.pa2 = regk_gio_yes;
917 break;
918 case 3:
919 intr_cfg.pa3 = regk_gio_lo;
920 intr_mask.pa3 = regk_gio_yes;
921 break;
922 case 4:
923 intr_cfg.pa4 = regk_gio_lo;
924 intr_mask.pa4 = regk_gio_yes;
925 break;
926 case 5:
927 intr_cfg.pa5 = regk_gio_lo;
928 intr_mask.pa5 = regk_gio_yes;
929 break;
930 case 6:
931 intr_cfg.pa6 = regk_gio_lo;
932 intr_mask.pa6 = regk_gio_yes;
933 break;
934 case 7:
935 intr_cfg.pa7 = regk_gio_lo;
936 intr_mask.pa7 = regk_gio_yes;
937 break;
938 }
939
940 REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
941 REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
942 }
943 #endif
944
945 /* main driver initialization routine, called from mem.c */
946
947 static int __init gpio_init(void)
948 {
949 int res;
950
951 printk(KERN_INFO "ETRAX FS GPIO driver v2.7, (c) 2003-2008 "
952 "Axis Communications AB\n");
953
954 /* do the formalities */
955
956 res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
957 if (res < 0) {
958 printk(KERN_ERR "gpio: couldn't get a major number.\n");
959 return res;
960 }
961
962 /* Clear all leds */
963 CRIS_LED_NETWORK_GRP0_SET(0);
964 CRIS_LED_NETWORK_GRP1_SET(0);
965 CRIS_LED_ACTIVE_SET(0);
966 CRIS_LED_DISK_READ(0);
967 CRIS_LED_DISK_WRITE(0);
968
969 int res2 = request_irq(GIO_INTR_VECT, gpio_interrupt,
970 IRQF_SHARED | IRQF_DISABLED, "gpio", &alarmlist);
971 if (res2) {
972 printk(KERN_ERR "err: irq for gpio\n");
973 return res2;
974 }
975
976 /* No IRQs by default. */
977 REG_WR_INT(gio, regi_gio, rw_intr_pins, 0);
978
979 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
980 virtual_gpio_init();
981 #endif
982
983 return res;
984 }
985
986 /* this makes sure that gpio_init is called during kernel boot */
987
988 module_init(gpio_init);
Tomato firmware and modifications.