release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf561/boards/acvilon.c

   1 /*
   2  * File:         arch/blackfin/mach-bf561/acvilon.c
   3  * Based on:     arch/blackfin/mach-bf561/ezkit.c
   4  * Author:
   5  *
   6  * Created:
   7  * Description:
   8  *
   9  * Modified:
  10  *               Copyright 2004-2006 Analog Devices Inc.
  11  *               Copyright 2009 CJSC "NII STT"
  12  *
  13  * Bugs:
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, see the file COPYING, or write
  27  * to the Free Software Foundation, Inc.,
  28  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  29  *
  30  *
  31  * For more information about Acvilon BF561 SoM please
  32  * go to http://www.niistt.ru/
  33  *
  34  */
  35
  36 #include <linux/device.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/mtd/mtd.h>
  39 #include <linux/mtd/partitions.h>
  40 #include <linux/mtd/physmap.h>
  41 #include <linux/mtd/nand.h>
  42 #include <linux/mtd/plat-ram.h>
  43 #include <linux/spi/spi.h>
  44 #include <linux/spi/flash.h>
  45 #include <linux/irq.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/jiffies.h>
  48 #include <linux/i2c-pca-platform.h>
  49 #include <linux/delay.h>
  50 #include <linux/io.h>
  51 #include <asm/dma.h>
  52 #include <asm/bfin5xx_spi.h>
  53 #include <asm/portmux.h>
  54 #include <asm/dpmc.h>
  55 #include <asm/cacheflush.h>
  56 #include <linux/i2c.h>
  57
  58 /*
  59  * Name the Board for the /proc/cpuinfo
  60  */
  61 const char bfin_board_name[] = "Acvilon board";
  62
  63 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
  64 #include <linux/usb/isp1760.h>
  65 static struct resource bfin_isp1760_resources[] = {
  66         [0] = {
  67                .start = 0x20000000,
  68                .end = 0x20000000 + 0x000fffff,
  69                .flags = IORESOURCE_MEM,
  70                },
  71         [1] = {
  72                .start = IRQ_PF15,
  73                .end = IRQ_PF15,
  74                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
  75                },
  76 };
  77
  78 static struct isp1760_platform_data isp1760_priv = {
  79         .is_isp1761 = 0,
  80         .port1_disable = 0,
  81         .bus_width_16 = 1,
  82         .port1_otg = 0,
  83         .analog_oc = 0,
  84         .dack_polarity_high = 0,
  85         .dreq_polarity_high = 0,
  86 };
  87
  88 static struct platform_device bfin_isp1760_device = {
  89         .name = "isp1760-hcd",
  90         .id = 0,
  91         .dev = {
  92                 .platform_data = &isp1760_priv,
  93                 },
  94         .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
  95         .resource = bfin_isp1760_resources,
  96 };
  97 #endif
  98
  99 static struct resource bfin_i2c_pca_resources[] = {
 100         {
 101          .name = "pca9564-regs",
 102          .start = 0x2C000000,
 103          .end = 0x2C000000 + 16,
 104          .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
 105          }, {
 106
 107              .start = IRQ_PF8,
 108              .end = IRQ_PF8,
 109              .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
 110              },
 111 };
 112
 113 struct i2c_pca9564_pf_platform_data pca9564_platform_data = {
 114         .gpio = -1,
 115         .i2c_clock_speed = 330000,
 116         .timeout = HZ,
 117 };
 118
 119 /* PCA9564 I2C Bus driver */
 120 static struct platform_device bfin_i2c_pca_device = {
 121         .name = "i2c-pca-platform",
 122         .id = 0,
 123         .num_resources = ARRAY_SIZE(bfin_i2c_pca_resources),
 124         .resource = bfin_i2c_pca_resources,
 125         .dev = {
 126                 .platform_data = &pca9564_platform_data,
 127                 }
 128 };
 129
 130 /* I2C devices fitted. */
 131 static struct i2c_board_info acvilon_i2c_devs[] __initdata = {
 132         {
 133          I2C_BOARD_INFO("ds1339", 0x68),
 134          },
 135         {
 136          I2C_BOARD_INFO("tcn75", 0x49),
 137          },
 138 };
 139
 140 #if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
 141 static struct platdata_mtd_ram mtd_ram_data = {
 142         .mapname = "rootfs(RAM)",
 143         .bankwidth = 4,
 144 };
 145
 146 static struct resource mtd_ram_resource = {
 147         .start = 0x4000000,
 148         .end = 0x5ffffff,
 149         .flags = IORESOURCE_MEM,
 150 };
 151
 152 static struct platform_device mtd_ram_device = {
 153         .name = "mtd-ram",
 154         .id = 0,
 155         .dev = {
 156                 .platform_data = &mtd_ram_data,
 157                 },
 158         .num_resources = 1,
 159         .resource = &mtd_ram_resource,
 160 };
 161 #endif
 162
 163 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 164 #include <linux/smsc911x.h>
 165 static struct resource smsc911x_resources[] = {
 166         {
 167          .name = "smsc911x-memory",
 168          .start = 0x28000000,
 169          .end = 0x28000000 + 0xFF,
 170          .flags = IORESOURCE_MEM,
 171          },
 172         {
 173          .start = IRQ_PF7,
 174          .end = IRQ_PF7,
 175          .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
 176          },
 177 };
 178
 179 static struct smsc911x_platform_config smsc911x_config = {
 180         .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
 181         .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
 182         .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
 183         .phy_interface = PHY_INTERFACE_MODE_MII,
 184 };
 185
 186 static struct platform_device smsc911x_device = {
 187         .name = "smsc911x",
 188         .id = 0,
 189         .num_resources = ARRAY_SIZE(smsc911x_resources),
 190         .resource = smsc911x_resources,
 191         .dev = {
 192                 .platform_data = &smsc911x_config,
 193                 },
 194 };
 195 #endif
 196
 197 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 198 #ifdef CONFIG_SERIAL_BFIN_UART0
 199 static struct resource bfin_uart0_resources[] = {
 200         {
 201          .start = BFIN_UART_THR,
 202          .end = BFIN_UART_GCTL + 2,
 203          .flags = IORESOURCE_MEM,
 204          },
 205         {
 206          .start = IRQ_UART_RX,
 207          .end = IRQ_UART_RX + 1,
 208          .flags = IORESOURCE_IRQ,
 209          },
 210         {
 211          .start = IRQ_UART_ERROR,
 212          .end = IRQ_UART_ERROR,
 213          .flags = IORESOURCE_IRQ,
 214          },
 215         {
 216          .start = CH_UART_TX,
 217          .end = CH_UART_TX,
 218          .flags = IORESOURCE_DMA,
 219          },
 220         {
 221          .start = CH_UART_RX,
 222          .end = CH_UART_RX,
 223          .flags = IORESOURCE_DMA,
 224          },
 225 };
 226
 227 unsigned short bfin_uart0_peripherals[] = {
 228         P_UART0_TX, P_UART0_RX, 0
 229 };
 230
 231 static struct platform_device bfin_uart0_device = {
 232         .name = "bfin-uart",
 233         .id = 0,
 234         .num_resources = ARRAY_SIZE(bfin_uart0_resources),
 235         .resource = bfin_uart0_resources,
 236         .dev = {
 237                 /* Passed to driver */
 238                 .platform_data = &bfin_uart0_peripherals,
 239                 },
 240 };
 241 #endif
 242 #endif
 243
 244 #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
 245
 246 #ifdef CONFIG_MTD_PARTITIONS
 247 const char *part_probes[] = { "cmdlinepart", NULL };
 248
 249 static struct mtd_partition bfin_plat_nand_partitions[] = {
 250         {
 251          .name = "params(nand)",
 252          .size = 32 * 1024 * 1024,
 253          .offset = 0,
 254          }, {
 255              .name = "userfs(nand)",
 256              .size = MTDPART_SIZ_FULL,
 257              .offset = MTDPART_OFS_APPEND,
 258              },
 259 };
 260 #endif
 261
 262 #define BFIN_NAND_PLAT_CLE 2
 263 #define BFIN_NAND_PLAT_ALE 3
 264
 265 static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 266                                     unsigned int ctrl)
 267 {
 268         struct nand_chip *this = mtd->priv;
 269
 270         if (cmd == NAND_CMD_NONE)
 271                 return;
 272
 273         if (ctrl & NAND_CLE)
 274                 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
 275         else
 276                 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
 277 }
 278
 279 #define BFIN_NAND_PLAT_READY GPIO_PF10
 280 static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
 281 {
 282         return gpio_get_value(BFIN_NAND_PLAT_READY);
 283 }
 284
 285 static struct platform_nand_data bfin_plat_nand_data = {
 286         .chip = {
 287                  .nr_chips = 1,
 288                  .chip_delay = 30,
 289 #ifdef CONFIG_MTD_PARTITIONS
 290                  .part_probe_types = part_probes,
 291                  .partitions = bfin_plat_nand_partitions,
 292                  .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
 293 #endif
 294                  },
 295         .ctrl = {
 296                  .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
 297                  .dev_ready = bfin_plat_nand_dev_ready,
 298                  },
 299 };
 300
 301 #define MAX(x, y) (x > y ? x : y)
 302 static struct resource bfin_plat_nand_resources = {
 303         .start = 0x24000000,
 304         .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
 305         .flags = IORESOURCE_IO,
 306 };
 307
 308 static struct platform_device bfin_async_nand_device = {
 309         .name = "gen_nand",
 310         .id = -1,
 311         .num_resources = 1,
 312         .resource = &bfin_plat_nand_resources,
 313         .dev = {
 314                 .platform_data = &bfin_plat_nand_data,
 315                 },
 316 };
 317
 318 static void bfin_plat_nand_init(void)
 319 {
 320         gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
 321 }
 322 #else
 323 static void bfin_plat_nand_init(void)
 324 {
 325 }
 326 #endif
 327
 328 #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
 329 static struct mtd_partition bfin_spi_dataflash_partitions[] = {
 330         {
 331          .name = "bootloader",
 332          .size = 0x4200,
 333          .offset = 0,
 334          .mask_flags = MTD_CAP_ROM},
 335         {
 336          .name = "u-boot",
 337          .size = 0x42000,
 338          .offset = MTDPART_OFS_APPEND,
 339          },
 340         {
 341          .name = "u-boot(params)",
 342          .size = 0x4200,
 343          .offset = MTDPART_OFS_APPEND,
 344          },
 345         {
 346          .name = "kernel",
 347          .size = 0x294000,
 348          .offset = MTDPART_OFS_APPEND,
 349          },
 350         {
 351          .name = "params",
 352          .size = 0x42000,
 353          .offset = MTDPART_OFS_APPEND,
 354          },
 355         {
 356          .name = "rootfs",
 357          .size = MTDPART_SIZ_FULL,
 358          .offset = MTDPART_OFS_APPEND,
 359          }
 360 };
 361
 362 static struct flash_platform_data bfin_spi_dataflash_data = {
 363         .name = "SPI Dataflash",
 364         .parts = bfin_spi_dataflash_partitions,
 365         .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
 366 };
 367
 368 /* DataFlash chip */
 369 static struct bfin5xx_spi_chip data_flash_chip_info = {
 370         .enable_dma = 0,        /* use dma transfer with this chip */
 371         .bits_per_word = 8,
 372 };
 373 #endif
 374
 375 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
 376 static struct bfin5xx_spi_chip spidev_chip_info = {
 377         .enable_dma = 0,
 378         .bits_per_word = 8,
 379 };
 380 #endif
 381
 382 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
 383 /* SPI (0) */
 384 static struct resource bfin_spi0_resource[] = {
 385         [0] = {
 386                .start = SPI0_REGBASE,
 387                .end = SPI0_REGBASE + 0xFF,
 388                .flags = IORESOURCE_MEM,
 389                },
 390         [1] = {
 391                .start = CH_SPI,
 392                .end = CH_SPI,
 393                .flags = IORESOURCE_DMA,
 394                },
 395         [2] = {
 396                .start = IRQ_SPI,
 397                .end = IRQ_SPI,
 398                .flags = IORESOURCE_IRQ,
 399                },
 400 };
 401
 402 /* SPI controller data */
 403 static struct bfin5xx_spi_master bfin_spi0_info = {
 404         .num_chipselect = 8,
 405         .enable_dma = 1,        /* master has the ability to do dma transfer */
 406         .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
 407 };
 408
 409 static struct platform_device bfin_spi0_device = {
 410         .name = "bfin-spi",
 411         .id = 0,                /* Bus number */
 412         .num_resources = ARRAY_SIZE(bfin_spi0_resource),
 413         .resource = bfin_spi0_resource,
 414         .dev = {
 415                 .platform_data = &bfin_spi0_info,       /* Passed to driver */
 416                 },
 417 };
 418 #endif
 419
 420 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 421 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
 422         {
 423          .modalias = "spidev",
 424          .max_speed_hz = 3125000,       /* max spi clock (SCK) speed in HZ */
 425          .bus_num = 0,
 426          .chip_select = 3,
 427          .controller_data = &spidev_chip_info,
 428          },
 429 #endif
 430 #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
 431         {                       /* DataFlash chip */
 432          .modalias = "mtd_dataflash",
 433          .max_speed_hz = 33250000,      /* max spi clock (SCK) speed in HZ */
 434          .bus_num = 0,          /* Framework bus number */
 435          .chip_select = 2,      /* Framework chip select */
 436          .platform_data = &bfin_spi_dataflash_data,
 437          .controller_data = &data_flash_chip_info,
 438          .mode = SPI_MODE_3,
 439          },
 440 #endif
 441 };
 442
 443 static struct resource bfin_gpios_resources = {
 444         .start = 31,
 445 /*      .end   = MAX_BLACKFIN_GPIOS - 1, */
 446         .end = 32,
 447         .flags = IORESOURCE_IRQ,
 448 };
 449
 450 static struct platform_device bfin_gpios_device = {
 451         .name = "simple-gpio",
 452         .id = -1,
 453         .num_resources = 1,
 454         .resource = &bfin_gpios_resources,
 455 };
 456
 457 static const unsigned int cclk_vlev_datasheet[] = {
 458         VRPAIR(VLEV_085, 250000000),
 459         VRPAIR(VLEV_090, 300000000),
 460         VRPAIR(VLEV_095, 313000000),
 461         VRPAIR(VLEV_100, 350000000),
 462         VRPAIR(VLEV_105, 400000000),
 463         VRPAIR(VLEV_110, 444000000),
 464         VRPAIR(VLEV_115, 450000000),
 465         VRPAIR(VLEV_120, 475000000),
 466         VRPAIR(VLEV_125, 500000000),
 467         VRPAIR(VLEV_130, 600000000),
 468 };
 469
 470 static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
 471         .tuple_tab = cclk_vlev_datasheet,
 472         .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
 473         .vr_settling_time = 25 /* us */ ,
 474 };
 475
 476 static struct platform_device bfin_dpmc = {
 477         .name = "bfin dpmc",
 478         .dev = {
 479                 .platform_data = &bfin_dmpc_vreg_data,
 480                 },
 481 };
 482
 483 static struct platform_device *acvilon_devices[] __initdata = {
 484         &bfin_dpmc,
 485
 486 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
 487         &bfin_spi0_device,
 488 #endif
 489
 490 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 491 #ifdef CONFIG_SERIAL_BFIN_UART0
 492         &bfin_uart0_device,
 493 #endif
 494 #endif
 495
 496         &bfin_gpios_device,
 497
 498 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 499         &smsc911x_device,
 500 #endif
 501
 502         &bfin_i2c_pca_device,
 503
 504 #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
 505         &bfin_async_nand_device,
 506 #endif
 507
 508 #if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
 509         &mtd_ram_device,
 510 #endif
 511
 512 };
 513
 514 static int __init acvilon_init(void)
 515 {
 516         int ret;
 517
 518         printk(KERN_INFO "%s(): registering device resources\n", __func__);
 519
 520         bfin_plat_nand_init();
 521         ret =
 522             platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices));
 523         if (ret < 0)
 524                 return ret;
 525
 526         i2c_register_board_info(0, acvilon_i2c_devs,
 527                                 ARRAY_SIZE(acvilon_i2c_devs));
 528
 529         bfin_write_FIO0_FLAG_C(1 << 14);
 530         msleep(5);
 531         bfin_write_FIO0_FLAG_S(1 << 14);
 532
 533         spi_register_board_info(bfin_spi_board_info,
 534                                 ARRAY_SIZE(bfin_spi_board_info));
 535         return 0;
 536 }
 537
 538 arch_initcall(acvilon_init);
 539
 540 static struct platform_device *acvilon_early_devices[] __initdata = {
 541 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
 542 #ifdef CONFIG_SERIAL_BFIN_UART0
 543         &bfin_uart0_device,
 544 #endif
 545 #endif
 546 };
 547
 548 void __init native_machine_early_platform_add_devices(void)
 549 {
 550         printk(KERN_INFO "register early platform devices\n");
 551         early_platform_add_devices(acvilon_early_devices,
 552                                    ARRAY_SIZE(acvilon_early_devices));
 553 }