2 * arch/blackfin/kernel/kgdb.c - Blackfin kgdb pieces
4 * Copyright 2005-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
9 #include <linux/ptrace.h> /* for linux pt_regs struct */
10 #include <linux/kgdb.h>
11 #include <linux/uaccess.h>
13 void pt_regs_to_gdb_regs(unsigned long *gdb_regs
, struct pt_regs
*regs
)
15 gdb_regs
[BFIN_R0
] = regs
->r0
;
16 gdb_regs
[BFIN_R1
] = regs
->r1
;
17 gdb_regs
[BFIN_R2
] = regs
->r2
;
18 gdb_regs
[BFIN_R3
] = regs
->r3
;
19 gdb_regs
[BFIN_R4
] = regs
->r4
;
20 gdb_regs
[BFIN_R5
] = regs
->r5
;
21 gdb_regs
[BFIN_R6
] = regs
->r6
;
22 gdb_regs
[BFIN_R7
] = regs
->r7
;
23 gdb_regs
[BFIN_P0
] = regs
->p0
;
24 gdb_regs
[BFIN_P1
] = regs
->p1
;
25 gdb_regs
[BFIN_P2
] = regs
->p2
;
26 gdb_regs
[BFIN_P3
] = regs
->p3
;
27 gdb_regs
[BFIN_P4
] = regs
->p4
;
28 gdb_regs
[BFIN_P5
] = regs
->p5
;
29 gdb_regs
[BFIN_SP
] = regs
->reserved
;
30 gdb_regs
[BFIN_FP
] = regs
->fp
;
31 gdb_regs
[BFIN_I0
] = regs
->i0
;
32 gdb_regs
[BFIN_I1
] = regs
->i1
;
33 gdb_regs
[BFIN_I2
] = regs
->i2
;
34 gdb_regs
[BFIN_I3
] = regs
->i3
;
35 gdb_regs
[BFIN_M0
] = regs
->m0
;
36 gdb_regs
[BFIN_M1
] = regs
->m1
;
37 gdb_regs
[BFIN_M2
] = regs
->m2
;
38 gdb_regs
[BFIN_M3
] = regs
->m3
;
39 gdb_regs
[BFIN_B0
] = regs
->b0
;
40 gdb_regs
[BFIN_B1
] = regs
->b1
;
41 gdb_regs
[BFIN_B2
] = regs
->b2
;
42 gdb_regs
[BFIN_B3
] = regs
->b3
;
43 gdb_regs
[BFIN_L0
] = regs
->l0
;
44 gdb_regs
[BFIN_L1
] = regs
->l1
;
45 gdb_regs
[BFIN_L2
] = regs
->l2
;
46 gdb_regs
[BFIN_L3
] = regs
->l3
;
47 gdb_regs
[BFIN_A0_DOT_X
] = regs
->a0x
;
48 gdb_regs
[BFIN_A0_DOT_W
] = regs
->a0w
;
49 gdb_regs
[BFIN_A1_DOT_X
] = regs
->a1x
;
50 gdb_regs
[BFIN_A1_DOT_W
] = regs
->a1w
;
51 gdb_regs
[BFIN_ASTAT
] = regs
->astat
;
52 gdb_regs
[BFIN_RETS
] = regs
->rets
;
53 gdb_regs
[BFIN_LC0
] = regs
->lc0
;
54 gdb_regs
[BFIN_LT0
] = regs
->lt0
;
55 gdb_regs
[BFIN_LB0
] = regs
->lb0
;
56 gdb_regs
[BFIN_LC1
] = regs
->lc1
;
57 gdb_regs
[BFIN_LT1
] = regs
->lt1
;
58 gdb_regs
[BFIN_LB1
] = regs
->lb1
;
59 gdb_regs
[BFIN_CYCLES
] = 0;
60 gdb_regs
[BFIN_CYCLES2
] = 0;
61 gdb_regs
[BFIN_USP
] = regs
->usp
;
62 gdb_regs
[BFIN_SEQSTAT
] = regs
->seqstat
;
63 gdb_regs
[BFIN_SYSCFG
] = regs
->syscfg
;
64 gdb_regs
[BFIN_RETI
] = regs
->pc
;
65 gdb_regs
[BFIN_RETX
] = regs
->retx
;
66 gdb_regs
[BFIN_RETN
] = regs
->retn
;
67 gdb_regs
[BFIN_RETE
] = regs
->rete
;
68 gdb_regs
[BFIN_PC
] = regs
->pc
;
69 gdb_regs
[BFIN_CC
] = (regs
->astat
>> 5) & 1;
70 gdb_regs
[BFIN_EXTRA1
] = 0;
71 gdb_regs
[BFIN_EXTRA2
] = 0;
72 gdb_regs
[BFIN_EXTRA3
] = 0;
73 gdb_regs
[BFIN_IPEND
] = regs
->ipend
;
77 * Extracts ebp, esp and eip values understandable by gdb from the values
79 * thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
80 * prior to entering switch_to is 8 greater than the value that is saved.
81 * If switch_to changes, change following code appropriately.
83 void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs
, struct task_struct
*p
)
85 gdb_regs
[BFIN_SP
] = p
->thread
.ksp
;
86 gdb_regs
[BFIN_PC
] = p
->thread
.pc
;
87 gdb_regs
[BFIN_SEQSTAT
] = p
->thread
.seqstat
;
90 void gdb_regs_to_pt_regs(unsigned long *gdb_regs
, struct pt_regs
*regs
)
92 regs
->r0
= gdb_regs
[BFIN_R0
];
93 regs
->r1
= gdb_regs
[BFIN_R1
];
94 regs
->r2
= gdb_regs
[BFIN_R2
];
95 regs
->r3
= gdb_regs
[BFIN_R3
];
96 regs
->r4
= gdb_regs
[BFIN_R4
];
97 regs
->r5
= gdb_regs
[BFIN_R5
];
98 regs
->r6
= gdb_regs
[BFIN_R6
];
99 regs
->r7
= gdb_regs
[BFIN_R7
];
100 regs
->p0
= gdb_regs
[BFIN_P0
];
101 regs
->p1
= gdb_regs
[BFIN_P1
];
102 regs
->p2
= gdb_regs
[BFIN_P2
];
103 regs
->p3
= gdb_regs
[BFIN_P3
];
104 regs
->p4
= gdb_regs
[BFIN_P4
];
105 regs
->p5
= gdb_regs
[BFIN_P5
];
106 regs
->fp
= gdb_regs
[BFIN_FP
];
107 regs
->i0
= gdb_regs
[BFIN_I0
];
108 regs
->i1
= gdb_regs
[BFIN_I1
];
109 regs
->i2
= gdb_regs
[BFIN_I2
];
110 regs
->i3
= gdb_regs
[BFIN_I3
];
111 regs
->m0
= gdb_regs
[BFIN_M0
];
112 regs
->m1
= gdb_regs
[BFIN_M1
];
113 regs
->m2
= gdb_regs
[BFIN_M2
];
114 regs
->m3
= gdb_regs
[BFIN_M3
];
115 regs
->b0
= gdb_regs
[BFIN_B0
];
116 regs
->b1
= gdb_regs
[BFIN_B1
];
117 regs
->b2
= gdb_regs
[BFIN_B2
];
118 regs
->b3
= gdb_regs
[BFIN_B3
];
119 regs
->l0
= gdb_regs
[BFIN_L0
];
120 regs
->l1
= gdb_regs
[BFIN_L1
];
121 regs
->l2
= gdb_regs
[BFIN_L2
];
122 regs
->l3
= gdb_regs
[BFIN_L3
];
123 regs
->a0x
= gdb_regs
[BFIN_A0_DOT_X
];
124 regs
->a0w
= gdb_regs
[BFIN_A0_DOT_W
];
125 regs
->a1x
= gdb_regs
[BFIN_A1_DOT_X
];
126 regs
->a1w
= gdb_regs
[BFIN_A1_DOT_W
];
127 regs
->rets
= gdb_regs
[BFIN_RETS
];
128 regs
->lc0
= gdb_regs
[BFIN_LC0
];
129 regs
->lt0
= gdb_regs
[BFIN_LT0
];
130 regs
->lb0
= gdb_regs
[BFIN_LB0
];
131 regs
->lc1
= gdb_regs
[BFIN_LC1
];
132 regs
->lt1
= gdb_regs
[BFIN_LT1
];
133 regs
->lb1
= gdb_regs
[BFIN_LB1
];
134 regs
->usp
= gdb_regs
[BFIN_USP
];
135 regs
->syscfg
= gdb_regs
[BFIN_SYSCFG
];
136 regs
->retx
= gdb_regs
[BFIN_RETX
];
137 regs
->retn
= gdb_regs
[BFIN_RETN
];
138 regs
->rete
= gdb_regs
[BFIN_RETE
];
139 regs
->pc
= gdb_regs
[BFIN_PC
];
143 static struct hw_breakpoint
{
144 unsigned int occupied
:1;
146 unsigned int enabled
:1;
148 unsigned int dataacc
:2;
149 unsigned short count
;
151 } breakinfo
[HW_WATCHPOINT_NUM
];
153 static int bfin_set_hw_break(unsigned long addr
, int len
, enum kgdb_bptype type
)
160 case BP_HARDWARE_BREAKPOINT
:
161 bfin_type
= TYPE_INST_WATCHPOINT
;
163 case BP_WRITE_WATCHPOINT
:
165 bfin_type
= TYPE_DATA_WATCHPOINT
;
167 case BP_READ_WATCHPOINT
:
169 bfin_type
= TYPE_DATA_WATCHPOINT
;
171 case BP_ACCESS_WATCHPOINT
:
173 bfin_type
= TYPE_DATA_WATCHPOINT
;
179 /* Becasue hardware data watchpoint impelemented in current
180 * Blackfin can not trigger an exception event as the hardware
181 * instrction watchpoint does, we ignaore all data watch point here.
182 * They can be turned on easily after future blackfin design
183 * supports this feature.
185 for (breakno
= 0; breakno
< HW_INST_WATCHPOINT_NUM
; breakno
++)
186 if (bfin_type
== breakinfo
[breakno
].type
187 && !breakinfo
[breakno
].occupied
) {
188 breakinfo
[breakno
].occupied
= 1;
189 breakinfo
[breakno
].skip
= 0;
190 breakinfo
[breakno
].enabled
= 1;
191 breakinfo
[breakno
].addr
= addr
;
192 breakinfo
[breakno
].dataacc
= dataacc
;
193 breakinfo
[breakno
].count
= 0;
200 static int bfin_remove_hw_break(unsigned long addr
, int len
, enum kgdb_bptype type
)
206 case BP_HARDWARE_BREAKPOINT
:
207 bfin_type
= TYPE_INST_WATCHPOINT
;
209 case BP_WRITE_WATCHPOINT
:
210 case BP_READ_WATCHPOINT
:
211 case BP_ACCESS_WATCHPOINT
:
212 bfin_type
= TYPE_DATA_WATCHPOINT
;
217 for (breakno
= 0; breakno
< HW_WATCHPOINT_NUM
; breakno
++)
218 if (bfin_type
== breakinfo
[breakno
].type
219 && breakinfo
[breakno
].occupied
220 && breakinfo
[breakno
].addr
== addr
) {
221 breakinfo
[breakno
].occupied
= 0;
222 breakinfo
[breakno
].enabled
= 0;
228 static void bfin_remove_all_hw_break(void)
232 memset(breakinfo
, 0, sizeof(struct hw_breakpoint
)*HW_WATCHPOINT_NUM
);
234 for (breakno
= 0; breakno
< HW_INST_WATCHPOINT_NUM
; breakno
++)
235 breakinfo
[breakno
].type
= TYPE_INST_WATCHPOINT
;
236 for (; breakno
< HW_WATCHPOINT_NUM
; breakno
++)
237 breakinfo
[breakno
].type
= TYPE_DATA_WATCHPOINT
;
240 static void bfin_correct_hw_break(void)
243 unsigned int wpiactl
= 0;
244 unsigned int wpdactl
= 0;
247 for (breakno
= 0; breakno
< HW_WATCHPOINT_NUM
; breakno
++)
248 if (breakinfo
[breakno
].enabled
) {
253 wpiactl
|= WPIAEN0
|WPICNTEN0
;
254 bfin_write_WPIA0(breakinfo
[breakno
].addr
);
255 bfin_write_WPIACNT0(breakinfo
[breakno
].count
259 wpiactl
|= WPIAEN1
|WPICNTEN1
;
260 bfin_write_WPIA1(breakinfo
[breakno
].addr
);
261 bfin_write_WPIACNT1(breakinfo
[breakno
].count
265 wpiactl
|= WPIAEN2
|WPICNTEN2
;
266 bfin_write_WPIA2(breakinfo
[breakno
].addr
);
267 bfin_write_WPIACNT2(breakinfo
[breakno
].count
271 wpiactl
|= WPIAEN3
|WPICNTEN3
;
272 bfin_write_WPIA3(breakinfo
[breakno
].addr
);
273 bfin_write_WPIACNT3(breakinfo
[breakno
].count
277 wpiactl
|= WPIAEN4
|WPICNTEN4
;
278 bfin_write_WPIA4(breakinfo
[breakno
].addr
);
279 bfin_write_WPIACNT4(breakinfo
[breakno
].count
283 wpiactl
|= WPIAEN5
|WPICNTEN5
;
284 bfin_write_WPIA5(breakinfo
[breakno
].addr
);
285 bfin_write_WPIACNT5(breakinfo
[breakno
].count
289 wpdactl
|= WPDAEN0
|WPDCNTEN0
|WPDSRC0
;
290 wpdactl
|= breakinfo
[breakno
].dataacc
292 bfin_write_WPDA0(breakinfo
[breakno
].addr
);
293 bfin_write_WPDACNT0(breakinfo
[breakno
].count
297 wpdactl
|= WPDAEN1
|WPDCNTEN1
|WPDSRC1
;
298 wpdactl
|= breakinfo
[breakno
].dataacc
300 bfin_write_WPDA1(breakinfo
[breakno
].addr
);
301 bfin_write_WPDACNT1(breakinfo
[breakno
].count
307 /* Should enable WPPWR bit first before set any other
308 * WPIACTL and WPDACTL bits */
310 bfin_write_WPIACTL(WPPWR
);
312 bfin_write_WPIACTL(wpiactl
|WPPWR
);
313 bfin_write_WPDACTL(wpdactl
);
318 void kgdb_disable_hw_debug(struct pt_regs
*regs
)
320 /* Disable hardware debugging while we are in kgdb */
321 bfin_write_WPIACTL(0);
322 bfin_write_WPDACTL(0);
327 void kgdb_passive_cpu_callback(void *info
)
329 kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
332 void kgdb_roundup_cpus(unsigned long flags
)
334 smp_call_function(kgdb_passive_cpu_callback
, NULL
, 0);
337 void kgdb_roundup_cpu(int cpu
, unsigned long flags
)
339 smp_call_function_single(cpu
, kgdb_passive_cpu_callback
, NULL
, 0);
343 int kgdb_arch_handle_exception(int vector
, int signo
,
344 int err_code
, char *remcom_in_buffer
,
345 char *remcom_out_buffer
,
346 struct pt_regs
*regs
)
353 switch (remcom_in_buffer
[0]) {
356 if (kgdb_contthread
&& kgdb_contthread
!= current
) {
357 strcpy(remcom_out_buffer
, "E00");
361 kgdb_contthread
= NULL
;
363 /* try to read optional parameter, pc unchanged if no parm */
364 ptr
= &remcom_in_buffer
[1];
365 if (kgdb_hex2long(&ptr
, &addr
)) {
370 /* clear the trace bit */
371 regs
->syscfg
&= 0xfffffffe;
373 /* set the trace bit if we're stepping */
374 if (remcom_in_buffer
[0] == 's') {
376 kgdb_single_step
= regs
->ipend
;
377 kgdb_single_step
>>= 6;
378 for (i
= 10; i
> 0; i
--, kgdb_single_step
>>= 1)
379 if (kgdb_single_step
& 1)
381 /* i indicate event priority of current stopped instruction
382 * user space instruction is 0, IVG15 is 1, IVTMR is 10.
383 * kgdb_single_step > 0 means in single step mode
385 kgdb_single_step
= i
+ 1;
388 bfin_correct_hw_break();
392 return -1; /* this means that we do not want to exit from the handler */
395 struct kgdb_arch arch_kgdb_ops
= {
396 .gdb_bpt_instr
= {0xa1},
398 .flags
= KGDB_HW_BREAKPOINT
|KGDB_THR_PROC_SWAP
,
400 .flags
= KGDB_HW_BREAKPOINT
,
402 .set_hw_breakpoint
= bfin_set_hw_break
,
403 .remove_hw_breakpoint
= bfin_remove_hw_break
,
404 .remove_all_hw_break
= bfin_remove_all_hw_break
,
405 .correct_hw_break
= bfin_correct_hw_break
,
408 #define IN_MEM(addr, size, l1_addr, l1_size) \
410 unsigned long __addr = (unsigned long)(addr); \
411 (l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \
413 #define ASYNC_BANK_SIZE \
414 (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
415 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE)
417 int kgdb_validate_break_address(unsigned long addr
)
419 int cpu
= raw_smp_processor_id();
421 if (addr
>= 0x1000 && (addr
+ BREAK_INSTR_SIZE
) <= physical_mem_end
)
423 if (IN_MEM(addr
, BREAK_INSTR_SIZE
, ASYNC_BANK0_BASE
, ASYNC_BANK_SIZE
))
425 if (cpu
== 0 && IN_MEM(addr
, BREAK_INSTR_SIZE
, L1_CODE_START
, L1_CODE_LENGTH
))
428 else if (cpu
== 1 && IN_MEM(addr
, BREAK_INSTR_SIZE
, COREB_L1_CODE_START
, L1_CODE_LENGTH
))
431 if (IN_MEM(addr
, BREAK_INSTR_SIZE
, L2_START
, L2_LENGTH
))
437 void kgdb_arch_set_pc(struct pt_regs
*regs
, unsigned long ip
)
442 int kgdb_arch_init(void)
444 kgdb_single_step
= 0;
446 bfin_remove_all_hw_break();
450 void kgdb_arch_exit(void)