release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/include/asm/mem_init.h

   1 /*
   2  * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory
   3  *
   4  * Copyright 2004-2008 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #if defined(EBIU_SDGCTL)
  10 #if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
  11         defined(CONFIG_MEM_MT48LC16M8A2TG_75) || defined(CONFIG_MEM_MT48LC32M8A2_75) || \
  12         defined(CONFIG_MEM_MT48LC8M32B2B5_7) || defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
  13         defined(CONFIG_MEM_MT48LC32M8A2_75)
  14 #if (CONFIG_SCLK_HZ > 119402985)
  15 #define SDRAM_tRP       TRP_2
  16 #define SDRAM_tRP_num   2
  17 #define SDRAM_tRAS      TRAS_7
  18 #define SDRAM_tRAS_num  7
  19 #define SDRAM_tRCD      TRCD_2
  20 #define SDRAM_tWR       TWR_2
  21 #endif
  22 #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
  23 #define SDRAM_tRP       TRP_2
  24 #define SDRAM_tRP_num   2
  25 #define SDRAM_tRAS      TRAS_6
  26 #define SDRAM_tRAS_num  6
  27 #define SDRAM_tRCD      TRCD_2
  28 #define SDRAM_tWR       TWR_2
  29 #endif
  30 #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
  31 #define SDRAM_tRP       TRP_2
  32 #define SDRAM_tRP_num   2
  33 #define SDRAM_tRAS      TRAS_5
  34 #define SDRAM_tRAS_num  5
  35 #define SDRAM_tRCD      TRCD_2
  36 #define SDRAM_tWR       TWR_2
  37 #endif
  38 #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
  39 #define SDRAM_tRP       TRP_2
  40 #define SDRAM_tRP_num   2
  41 #define SDRAM_tRAS      TRAS_4
  42 #define SDRAM_tRAS_num  4
  43 #define SDRAM_tRCD      TRCD_2
  44 #define SDRAM_tWR       TWR_2
  45 #endif
  46 #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
  47 #define SDRAM_tRP       TRP_2
  48 #define SDRAM_tRP_num   2
  49 #define SDRAM_tRAS      TRAS_3
  50 #define SDRAM_tRAS_num  3
  51 #define SDRAM_tRCD      TRCD_2
  52 #define SDRAM_tWR       TWR_2
  53 #endif
  54 #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
  55 #define SDRAM_tRP       TRP_1
  56 #define SDRAM_tRP_num   1
  57 #define SDRAM_tRAS      TRAS_4
  58 #define SDRAM_tRAS_num  4
  59 #define SDRAM_tRCD      TRCD_1
  60 #define SDRAM_tWR       TWR_2
  61 #endif
  62 #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
  63 #define SDRAM_tRP       TRP_1
  64 #define SDRAM_tRP_num   1
  65 #define SDRAM_tRAS      TRAS_3
  66 #define SDRAM_tRAS_num  3
  67 #define SDRAM_tRCD      TRCD_1
  68 #define SDRAM_tWR       TWR_2
  69 #endif
  70 #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
  71 #define SDRAM_tRP       TRP_1
  72 #define SDRAM_tRP_num   1
  73 #define SDRAM_tRAS      TRAS_2
  74 #define SDRAM_tRAS_num  2
  75 #define SDRAM_tRCD      TRCD_1
  76 #define SDRAM_tWR       TWR_2
  77 #endif
  78 #if (CONFIG_SCLK_HZ <= 29850746)
  79 #define SDRAM_tRP       TRP_1
  80 #define SDRAM_tRP_num   1
  81 #define SDRAM_tRAS      TRAS_1
  82 #define SDRAM_tRAS_num  1
  83 #define SDRAM_tRCD      TRCD_1
  84 #define SDRAM_tWR       TWR_2
  85 #endif
  86 #endif
  87
  88 /*
  89  * The BF526-EZ-Board changed SDRAM chips between revisions,
  90  * so we use below timings to accommodate both.
  91  */
  92 #if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
  93 #if (CONFIG_SCLK_HZ > 119402985)
  94 #define SDRAM_tRP       TRP_2
  95 #define SDRAM_tRP_num   2
  96 #define SDRAM_tRAS      TRAS_8
  97 #define SDRAM_tRAS_num  8
  98 #define SDRAM_tRCD      TRCD_2
  99 #define SDRAM_tWR       TWR_2
 100 #endif
 101 #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
 102 #define SDRAM_tRP       TRP_2
 103 #define SDRAM_tRP_num   2
 104 #define SDRAM_tRAS      TRAS_7
 105 #define SDRAM_tRAS_num  7
 106 #define SDRAM_tRCD      TRCD_2
 107 #define SDRAM_tWR       TWR_2
 108 #endif
 109 #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
 110 #define SDRAM_tRP       TRP_2
 111 #define SDRAM_tRP_num   2
 112 #define SDRAM_tRAS      TRAS_6
 113 #define SDRAM_tRAS_num  6
 114 #define SDRAM_tRCD      TRCD_2
 115 #define SDRAM_tWR       TWR_2
 116 #endif
 117 #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
 118 #define SDRAM_tRP       TRP_2
 119 #define SDRAM_tRP_num   2
 120 #define SDRAM_tRAS      TRAS_5
 121 #define SDRAM_tRAS_num  5
 122 #define SDRAM_tRCD      TRCD_2
 123 #define SDRAM_tWR       TWR_2
 124 #endif
 125 #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
 126 #define SDRAM_tRP       TRP_2
 127 #define SDRAM_tRP_num   2
 128 #define SDRAM_tRAS      TRAS_4
 129 #define SDRAM_tRAS_num  4
 130 #define SDRAM_tRCD      TRCD_2
 131 #define SDRAM_tWR       TWR_2
 132 #endif
 133 #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
 134 #define SDRAM_tRP       TRP_2
 135 #define SDRAM_tRP_num   2
 136 #define SDRAM_tRAS      TRAS_4
 137 #define SDRAM_tRAS_num  4
 138 #define SDRAM_tRCD      TRCD_1
 139 #define SDRAM_tWR       TWR_2
 140 #endif
 141 #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
 142 #define SDRAM_tRP       TRP_2
 143 #define SDRAM_tRP_num   2
 144 #define SDRAM_tRAS      TRAS_3
 145 #define SDRAM_tRAS_num  3
 146 #define SDRAM_tRCD      TRCD_1
 147 #define SDRAM_tWR       TWR_2
 148 #endif
 149 #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
 150 #define SDRAM_tRP       TRP_1
 151 #define SDRAM_tRP_num   1
 152 #define SDRAM_tRAS      TRAS_3
 153 #define SDRAM_tRAS_num  3
 154 #define SDRAM_tRCD      TRCD_1
 155 #define SDRAM_tWR       TWR_2
 156 #endif
 157 #if (CONFIG_SCLK_HZ <= 29850746)
 158 #define SDRAM_tRP       TRP_1
 159 #define SDRAM_tRP_num   1
 160 #define SDRAM_tRAS      TRAS_2
 161 #define SDRAM_tRAS_num  2
 162 #define SDRAM_tRCD      TRCD_1
 163 #define SDRAM_tWR       TWR_2
 164 #endif
 165 #endif
 166
 167 #if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || defined(CONFIG_MEM_MT48LC8M32B2B5_7)
 168   /*SDRAM INFORMATION: */
 169 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
 170 #define SDRAM_NRA   4096        /* Number of row addresses in SDRAM */
 171 #define SDRAM_CL    CL_3
 172 #endif
 173
 174 #if defined(CONFIG_MEM_MT48LC32M8A2_75) || defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
 175         defined(CONFIG_MEM_MT48LC32M16A2TG_75) || defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
 176         defined(CONFIG_MEM_MT48LC32M8A2_75)
 177   /*SDRAM INFORMATION: */
 178 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
 179 #define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
 180 #define SDRAM_CL    CL_3
 181 #endif
 182
 183 #if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
 184   /*SDRAM INFORMATION: */
 185 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
 186 #define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
 187 #define SDRAM_CL    CL_2
 188 #endif
 189
 190
 191 #ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
 192 /* Equation from section 17 (p17-46) of BF533 HRM */
 193 #define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
 194
 195 /* Enable SCLK Out */
 196 #define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
 197 #else
 198 #define mem_SDRRC       CONFIG_MEM_SDRRC
 199 #define mem_SDGCTL      CONFIG_MEM_SDGCTL
 200 #endif
 201 #endif
 202
 203
 204 #if defined(EBIU_DDRCTL0)
 205 #define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
 206 #define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
 207 #define DDR_CLK_HZ(x)   (1000*1000*1000/x)
 208
 209 #if defined(CONFIG_MEM_MT46V32M16_6T)
 210 #define DDR_SIZE        DEVSZ_512
 211 #define DDR_WIDTH       DEVWD_16
 212 #define DDR_MAX_tCK     13
 213
 214 #define DDR_tRC         DDR_TRC(MIN_DDR_SCLK(60))
 215 #define DDR_tRAS        DDR_TRAS(MIN_DDR_SCLK(42))
 216 #define DDR_tRP         DDR_TRP(MIN_DDR_SCLK(15))
 217 #define DDR_tRFC        DDR_TRFC(MIN_DDR_SCLK(72))
 218 #define DDR_tREFI       DDR_TREFI(MAX_DDR_SCLK(7800))
 219
 220 #define DDR_tRCD        DDR_TRCD(MIN_DDR_SCLK(15))
 221 #define DDR_tWTR        DDR_TWTR(1)
 222 #define DDR_tMRD        DDR_TMRD(MIN_DDR_SCLK(12))
 223 #define DDR_tWR         DDR_TWR(MIN_DDR_SCLK(15))
 224 #endif
 225
 226 #if defined(CONFIG_MEM_MT46V32M16_5B)
 227 #define DDR_SIZE        DEVSZ_512
 228 #define DDR_WIDTH       DEVWD_16
 229 #define DDR_MAX_tCK     13
 230
 231 #define DDR_tRC         DDR_TRC(MIN_DDR_SCLK(55))
 232 #define DDR_tRAS        DDR_TRAS(MIN_DDR_SCLK(40))
 233 #define DDR_tRP         DDR_TRP(MIN_DDR_SCLK(15))
 234 #define DDR_tRFC        DDR_TRFC(MIN_DDR_SCLK(70))
 235 #define DDR_tREFI       DDR_TREFI(MAX_DDR_SCLK(7800))
 236
 237 #define DDR_tRCD        DDR_TRCD(MIN_DDR_SCLK(15))
 238 #define DDR_tWTR        DDR_TWTR(2)
 239 #define DDR_tMRD        DDR_TMRD(MIN_DDR_SCLK(10))
 240 #define DDR_tWR         DDR_TWR(MIN_DDR_SCLK(15))
 241 #endif
 242
 243 #if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
 244 # error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
 245 #elif(CONFIG_SCLK_HZ <= 133333333)
 246 # define        DDR_CL          CL_2
 247 #else
 248 # error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
 249 #endif
 250
 251 #ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
 252 #define mem_DDRCTL0     (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
 253 #define mem_DDRCTL1     (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
 254                         | DDR_tMRD | DDR_tWR | DDR_tRCD)
 255 #define mem_DDRCTL2     DDR_CL
 256 #else
 257 #define mem_DDRCTL0     CONFIG_MEM_DDRCTL0
 258 #define mem_DDRCTL1     CONFIG_MEM_DDRCTL1
 259 #define mem_DDRCTL2     CONFIG_MEM_DDRCTL2
 260 #endif
 261 #endif
 262
 263 #if defined CONFIG_CLKIN_HALF
 264 #define CLKIN_HALF       1
 265 #else
 266 #define CLKIN_HALF       0
 267 #endif
 268
 269 #if defined CONFIG_PLL_BYPASS
 270 #define PLL_BYPASS      1
 271 #else
 272 #define PLL_BYPASS       0
 273 #endif