2 * Low-level Power Management code.
4 * Copyright (C) 2008 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <asm/asm-offsets.h>
12 #include <asm/thread_info.h>
18 /* Same as 0xfff00000 but fits in a 21 bit signed immediate */
19 #define PM_BASE -0x100000
21 .section .bss, "wa", @nobits
22 .global disable_idle_sleep
23 .type disable_idle_sleep, @object
26 .size disable_idle_sleep, . - disable_idle_sleep
28 /* Keep this close to the irq handlers */
29 .section .irq.text, "ax", @progbits
31 .global cpu_enter_idle
32 .type cpu_enter_idle, @function
37 bld r9, TIF_NEED_RESCHED
39 sbr r9, TIF_CPU_GOING_TO_SLEEP
43 .size cpu_idle_sleep, . - cpu_idle_sleep
46 * Common return path for PM functions that don't run from
49 .global cpu_idle_skip_sleep
50 .type cpu_idle_skip_sleep, @function
54 cbr r9, TIF_CPU_GOING_TO_SLEEP
59 .size cpu_idle_skip_sleep, . - cpu_idle_skip_sleep
62 .section .init.text, "ax", @progbits
65 .type pm_exception, @function
68 * Exceptions are masked when we switch to this handler, so
69 * we'll only get "unrecoverable" exceptions (offset 0.)
71 sub r12, pc, . - .Lpanic_msg
72 lddpc pc, .Lpanic_addr
78 .asciz "Unrecoverable exception during suspend\n"
79 .size pm_exception, . - pm_exception
82 .type pm_irq0, @function
84 /* Disable interrupts and return after the sleep instruction */
85 mfsr r9, SYSREG_RSR_INT0
86 mtsr SYSREG_RAR_INT0, r8
87 sbr r9, SYSREG_GM_OFFSET
88 mtsr SYSREG_RSR_INT0, r9
92 * void cpu_enter_standby(unsigned long sdramc_base)
94 * Enter PM_SUSPEND_STANDBY mode. At this point, all drivers
95 * are suspended and interrupts are disabled. Interrupts
96 * marked as 'wakeup' event sources may still come along and
99 * The SDRAM will be put into self-refresh mode (which does
100 * not require a clock from the CPU), and the CPU will be put
101 * into "frozen" mode (HSB bus stopped). The SDRAM controller
102 * will automatically bring the SDRAM into normal mode on the
103 * first access, and the power manager will automatically
104 * start the HSB and CPU clocks upon a wakeup event.
106 * This code uses the same "skip sleep" technique as above.
107 * It is very important that we jump directly to
108 * cpu_after_sleep after the sleep instruction since that's
109 * where we'll end up if the interrupt handler decides that we
110 * need to skip the sleep instruction.
113 .type pm_standby, @function
116 * interrupts are already masked at this point, and EVBA
117 * points to pm_exception above.
119 ld.w r10, r12[SDRAMC_LPR]
120 sub r8, pc, . - 1f /* return address for irq handler */
121 mov r11, SDRAMC_LPR_LPCB_SELF_RFR
122 bfins r10, r11, 0, 2 /* LPCB <- self Refresh */
123 sync 0 /* flush write buffer */
124 st.w r12[SDRAMC_LPR], r10 /* put SDRAM in self-refresh mode */
125 ld.w r11, r12[SDRAMC_LPR]
127 sleep CPU_SLEEP_FROZEN
130 .size pm_standby, . - pm_standby
132 .global pm_suspend_to_ram
133 .type pm_suspend_to_ram, @function
136 * interrupts are already masked at this point, and EVBA
137 * points to pm_exception above.
140 cache r11[2], 8 /* clean all dcache lines */
141 sync 0 /* flush write buffer */
142 ld.w r10, r12[SDRAMC_LPR]
143 sub r8, pc, . - 1f /* return address for irq handler */
144 mov r11, SDRAMC_LPR_LPCB_SELF_RFR
145 bfins r10, r11, 0, 2 /* LPCB <- self refresh */
146 st.w r12[SDRAMC_LPR], r10 /* put SDRAM in self-refresh mode */
147 ld.w r11, r12[SDRAMC_LPR]
154 .size pm_suspend_to_ram, . - pm_suspend_to_ram
157 .type pm_sram_end, @function
161 #endif /* CONFIG_PM */