release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h

   1 /* linux/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
   2  *
   3  * Copyright (C) 2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * Samsung S3C24XX DMA support - per SoC functions
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <plat/dma-core.h>
  14
  15 extern struct sysdev_class dma_sysclass;
  16 extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
  17
  18 #define DMA_CH_VALID            (1<<31)
  19 #define DMA_CH_NEVER            (1<<30)
  20
  21 struct s3c24xx_dma_addr {
  22         unsigned long           from;
  23         unsigned long           to;
  24 };
  25
  26 /* struct s3c24xx_dma_map
  27  *
  28  * this holds the mapping information for the channel selected
  29  * to be connected to the specified device
  30 */
  31
  32 struct s3c24xx_dma_map {
  33         const char              *name;
  34         struct s3c24xx_dma_addr  hw_addr;
  35
  36         unsigned long            channels[S3C_DMA_CHANNELS];
  37         unsigned long            channels_rx[S3C_DMA_CHANNELS];
  38 };
  39
  40 struct s3c24xx_dma_selection {
  41         struct s3c24xx_dma_map  *map;
  42         unsigned long            map_size;
  43         unsigned long            dcon_mask;
  44
  45         void    (*select)(struct s3c2410_dma_chan *chan,
  46                           struct s3c24xx_dma_map *map);
  47
  48         void    (*direction)(struct s3c2410_dma_chan *chan,
  49                              struct s3c24xx_dma_map *map,
  50                              enum s3c2410_dmasrc dir);
  51 };
  52
  53 extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
  54
  55 /* struct s3c24xx_dma_order_ch
  56  *
  57  * channel map for one of the `enum dma_ch` dma channels. the list
  58  * entry contains a set of low-level channel numbers, orred with
  59  * DMA_CH_VALID, which are checked in the order in the array.
  60 */
  61
  62 struct s3c24xx_dma_order_ch {
  63         unsigned int    list[S3C_DMA_CHANNELS]; /* list of channels */
  64         unsigned int    flags;                          /* flags */
  65 };
  66
  67 /* struct s3c24xx_dma_order
  68  *
  69  * information provided by either the core or the board to give the
  70  * dma system a hint on how to allocate channels
  71 */
  72
  73 struct s3c24xx_dma_order {
  74         struct s3c24xx_dma_order_ch     channels[DMACH_MAX];
  75 };
  76
  77 extern int s3c24xx_dma_order_set(struct s3c24xx_dma_order *map);
  78
  79 /* DMA init code, called from the cpu support code */
  80
  81 extern int s3c2410_dma_init(void);
  82
  83 extern int s3c24xx_dma_init(unsigned int channels, unsigned int irq,
  84                             unsigned int stride);