release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-omap/include/plat/usb.h

   1 // include/asm-arm/mach-omap/usb.h
   2
   3 #ifndef __ASM_ARCH_OMAP_USB_H
   4 #define __ASM_ARCH_OMAP_USB_H
   5
   6 #include <linux/usb/musb.h>
   7 #include <plat/board.h>
   8
   9 #define OMAP3_HS_USB_PORTS      3
  10 enum ehci_hcd_omap_mode {
  11         EHCI_HCD_OMAP_MODE_UNKNOWN,
  12         EHCI_HCD_OMAP_MODE_PHY,
  13         EHCI_HCD_OMAP_MODE_TLL,
  14 };
  15
  16 enum ohci_omap3_port_mode {
  17         OMAP_OHCI_PORT_MODE_UNUSED,
  18         OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
  19         OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
  20         OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
  21         OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
  22         OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
  23         OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
  24         OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
  25         OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
  26         OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
  27         OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM,
  28 };
  29
  30 struct ehci_hcd_omap_platform_data {
  31         enum ehci_hcd_omap_mode         port_mode[OMAP3_HS_USB_PORTS];
  32         unsigned                        phy_reset:1;
  33
  34         /* have to be valid if phy_reset is true and portx is in phy mode */
  35         int     reset_gpio_port[OMAP3_HS_USB_PORTS];
  36 };
  37
  38 struct ohci_hcd_omap_platform_data {
  39         enum ohci_omap3_port_mode       port_mode[OMAP3_HS_USB_PORTS];
  40
  41         /* Set this to true for ES2.x silicon */
  42         unsigned                        es2_compatibility:1;
  43 };
  44
  45 /*-------------------------------------------------------------------------*/
  46
  47 #define OMAP1_OTG_BASE                  0xfffb0400
  48 #define OMAP1_UDC_BASE                  0xfffb4000
  49 #define OMAP1_OHCI_BASE                 0xfffba000
  50
  51 #define OMAP2_OHCI_BASE                 0x4805e000
  52 #define OMAP2_UDC_BASE                  0x4805e200
  53 #define OMAP2_OTG_BASE                  0x4805e300
  54
  55 #ifdef CONFIG_ARCH_OMAP1
  56
  57 #define OTG_BASE                        OMAP1_OTG_BASE
  58 #define UDC_BASE                        OMAP1_UDC_BASE
  59 #define OMAP_OHCI_BASE                  OMAP1_OHCI_BASE
  60
  61 #else
  62
  63 #define OTG_BASE                        OMAP2_OTG_BASE
  64 #define UDC_BASE                        OMAP2_UDC_BASE
  65 #define OMAP_OHCI_BASE                  OMAP2_OHCI_BASE
  66
  67 struct omap_musb_board_data {
  68         u8      interface_type;
  69         u8      mode;
  70         u16     power;
  71         unsigned extvbus:1;
  72 };
  73
  74 enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
  75
  76 extern void usb_musb_init(struct omap_musb_board_data *board_data);
  77
  78 extern void usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata);
  79
  80 extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata);
  81
  82 #endif
  83
  84
  85 #ifdef  CONFIG_USB_GADGET_OMAP
  86 #define is_usb0_device(config)  1
  87 #else
  88 #define is_usb0_device(config)  0
  89 #endif
  90
  91 void omap_otg_init(struct omap_usb_config *config);
  92
  93 #if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
  94 void omap1_usb_init(struct omap_usb_config *pdata);
  95 #else
  96 static inline void omap1_usb_init(struct omap_usb_config *pdata)
  97 {
  98 }
  99 #endif
 100
 101 #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
 102 void omap2_usbfs_init(struct omap_usb_config *pdata);
 103 #else
 104 static inline omap2_usbfs_init(struct omap_usb_config *pdata)
 105 {
 106 }
 107 #endif
 108
 109 /*-------------------------------------------------------------------------*/
 110
 111 /*
 112  * OTG and transceiver registers, for OMAPs starting with ARM926
 113  */
 114 #define OTG_REV                         (OTG_BASE + 0x00)
 115 #define OTG_SYSCON_1                    (OTG_BASE + 0x04)
 116 #       define   USB2_TRX_MODE(w)       (((w)>>24)&0x07)
 117 #       define   USB1_TRX_MODE(w)       (((w)>>20)&0x07)
 118 #       define   USB0_TRX_MODE(w)       (((w)>>16)&0x07)
 119 #       define   OTG_IDLE_EN            (1 << 15)
 120 #       define   HST_IDLE_EN            (1 << 14)
 121 #       define   DEV_IDLE_EN            (1 << 13)
 122 #       define   OTG_RESET_DONE         (1 << 2)
 123 #       define   OTG_SOFT_RESET         (1 << 1)
 124 #define OTG_SYSCON_2                    (OTG_BASE + 0x08)
 125 #       define   OTG_EN                 (1 << 31)
 126 #       define   USBX_SYNCHRO           (1 << 30)
 127 #       define   OTG_MST16              (1 << 29)
 128 #       define   SRP_GPDATA             (1 << 28)
 129 #       define   SRP_GPDVBUS            (1 << 27)
 130 #       define   SRP_GPUVBUS(w)         (((w)>>24)&0x07)
 131 #       define   A_WAIT_VRISE(w)        (((w)>>20)&0x07)
 132 #       define   B_ASE_BRST(w)          (((w)>>16)&0x07)
 133 #       define   SRP_DPW                (1 << 14)
 134 #       define   SRP_DATA               (1 << 13)
 135 #       define   SRP_VBUS               (1 << 12)
 136 #       define   OTG_PADEN              (1 << 10)
 137 #       define   HMC_PADEN              (1 << 9)
 138 #       define   UHOST_EN               (1 << 8)
 139 #       define   HMC_TLLSPEED           (1 << 7)
 140 #       define   HMC_TLLATTACH          (1 << 6)
 141 #       define   OTG_HMC(w)             (((w)>>0)&0x3f)
 142 #define OTG_CTRL                        (OTG_BASE + 0x0c)
 143 #       define   OTG_USB2_EN            (1 << 29)
 144 #       define   OTG_USB2_DP            (1 << 28)
 145 #       define   OTG_USB2_DM            (1 << 27)
 146 #       define   OTG_USB1_EN            (1 << 26)
 147 #       define   OTG_USB1_DP            (1 << 25)
 148 #       define   OTG_USB1_DM            (1 << 24)
 149 #       define   OTG_USB0_EN            (1 << 23)
 150 #       define   OTG_USB0_DP            (1 << 22)
 151 #       define   OTG_USB0_DM            (1 << 21)
 152 #       define   OTG_ASESSVLD           (1 << 20)
 153 #       define   OTG_BSESSEND           (1 << 19)
 154 #       define   OTG_BSESSVLD           (1 << 18)
 155 #       define   OTG_VBUSVLD            (1 << 17)
 156 #       define   OTG_ID                 (1 << 16)
 157 #       define   OTG_DRIVER_SEL         (1 << 15)
 158 #       define   OTG_A_SETB_HNPEN       (1 << 12)
 159 #       define   OTG_A_BUSREQ           (1 << 11)
 160 #       define   OTG_B_HNPEN            (1 << 9)
 161 #       define   OTG_B_BUSREQ           (1 << 8)
 162 #       define   OTG_BUSDROP            (1 << 7)
 163 #       define   OTG_PULLDOWN           (1 << 5)
 164 #       define   OTG_PULLUP             (1 << 4)
 165 #       define   OTG_DRV_VBUS           (1 << 3)
 166 #       define   OTG_PD_VBUS            (1 << 2)
 167 #       define   OTG_PU_VBUS            (1 << 1)
 168 #       define   OTG_PU_ID              (1 << 0)
 169 #define OTG_IRQ_EN                      (OTG_BASE + 0x10)       /* 16-bit */
 170 #       define   DRIVER_SWITCH          (1 << 15)
 171 #       define   A_VBUS_ERR             (1 << 13)
 172 #       define   A_REQ_TMROUT           (1 << 12)
 173 #       define   A_SRP_DETECT           (1 << 11)
 174 #       define   B_HNP_FAIL             (1 << 10)
 175 #       define   B_SRP_TMROUT           (1 << 9)
 176 #       define   B_SRP_DONE             (1 << 8)
 177 #       define   B_SRP_STARTED          (1 << 7)
 178 #       define   OPRT_CHG               (1 << 0)
 179 #define OTG_IRQ_SRC                     (OTG_BASE + 0x14)       /* 16-bit */
 180         // same bits as in IRQ_EN
 181 #define OTG_OUTCTRL                     (OTG_BASE + 0x18)       /* 16-bit */
 182 #       define   OTGVPD                 (1 << 14)
 183 #       define   OTGVPU                 (1 << 13)
 184 #       define   OTGPUID                (1 << 12)
 185 #       define   USB2VDR                (1 << 10)
 186 #       define   USB2PDEN               (1 << 9)
 187 #       define   USB2PUEN               (1 << 8)
 188 #       define   USB1VDR                (1 << 6)
 189 #       define   USB1PDEN               (1 << 5)
 190 #       define   USB1PUEN               (1 << 4)
 191 #       define   USB0VDR                (1 << 2)
 192 #       define   USB0PDEN               (1 << 1)
 193 #       define   USB0PUEN               (1 << 0)
 194 #define OTG_TEST                        (OTG_BASE + 0x20)       /* 16-bit */
 195 #define OTG_VENDOR_CODE                 (OTG_BASE + 0xfc)       /* 16-bit */
 196
 197 /*-------------------------------------------------------------------------*/
 198
 199 /* OMAP1 */
 200 #define USB_TRANSCEIVER_CTRL            (0xfffe1000 + 0x0064)
 201 #       define  CONF_USB2_UNI_R         (1 << 8)
 202 #       define  CONF_USB1_UNI_R         (1 << 7)
 203 #       define  CONF_USB_PORT0_R(x)     (((x)>>4)&0x7)
 204 #       define  CONF_USB0_ISOLATE_R     (1 << 3)
 205 #       define  CONF_USB_PWRDN_DM_R     (1 << 2)
 206 #       define  CONF_USB_PWRDN_DP_R     (1 << 1)
 207
 208 /* OMAP2 */
 209 #       define  USB_UNIDIR                      0x0
 210 #       define  USB_UNIDIR_TLL                  0x1
 211 #       define  USB_BIDIR                       0x2
 212 #       define  USB_BIDIR_TLL                   0x3
 213 #       define  USBTXWRMODEI(port, x)   ((x) << (22 - (port * 2)))
 214 #       define  USBT2TLL5PI             (1 << 17)
 215 #       define  USB0PUENACTLOI          (1 << 16)
 216 #       define  USBSTANDBYCTRL          (1 << 15)
 217
 218 #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
 219 u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
 220 u32 omap1_usb1_init(unsigned nwires);
 221 u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup);
 222 #else
 223 static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
 224 {
 225         return 0;
 226 }
 227 static inline u32 omap1_usb1_init(unsigned nwires)
 228 {
 229         return 0;
 230
 231 }
 232 static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
 233 {
 234         return 0;
 235 }
 236 #endif
 237
 238 #endif  /* __ASM_ARCH_OMAP_USB_H */