release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-mxc/tzic.c

   1 /*
   2  * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/init.h>
  15 #include <linux/device.h>
  16 #include <linux/errno.h>
  17 #include <linux/io.h>
  18
  19 #include <asm/mach/irq.h>
  20
  21 #include <mach/hardware.h>
  22 #include <mach/common.h>
  23
  24 /*
  25  *****************************************
  26  * TZIC Registers                        *
  27  *****************************************
  28  */
  29
  30 #define TZIC_INTCNTL    0x0000  /* Control register */
  31 #define TZIC_INTTYPE    0x0004  /* Controller Type register */
  32 #define TZIC_IMPID      0x0008  /* Distributor Implementer Identification */
  33 #define TZIC_PRIOMASK   0x000C  /* Priority Mask Reg */
  34 #define TZIC_SYNCCTRL   0x0010  /* Synchronizer Control register */
  35 #define TZIC_DSMINT     0x0014  /* DSM interrupt Holdoffregister */
  36 #define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
  37 #define TZIC_ENSET0(i)  (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
  38 #define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
  39 #define TZIC_SRCSET0    0x0200  /* Source Set Register 0 */
  40 #define TZIC_SRCCLAR0   0x0280  /* Source Clear Register 0 */
  41 #define TZIC_PRIORITY0  0x0400  /* Priority Register 0 */
  42 #define TZIC_PND0       0x0D00  /* Pending Register 0 */
  43 #define TZIC_HIPND0     0x0D80  /* High Priority Pending Register */
  44 #define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2))   /* Wakeup Config Register */
  45 #define TZIC_SWINT      0x0F00  /* Software Interrupt Rigger Register */
  46 #define TZIC_ID0        0x0FD0  /* Indentification Register 0 */
  47
  48 void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
  49
  50 /**
  51  * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC
  52  *
  53  * @param  irq          interrupt source number
  54  */
  55 static void tzic_mask_irq(unsigned int irq)
  56 {
  57         int index, off;
  58
  59         index = irq >> 5;
  60         off = irq & 0x1F;
  61         __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index));
  62 }
  63
  64 /**
  65  * tzic_unmask_irq() - Enable interrupt number "irq" in the TZIC
  66  *
  67  * @param  irq          interrupt source number
  68  */
  69 static void tzic_unmask_irq(unsigned int irq)
  70 {
  71         int index, off;
  72
  73         index = irq >> 5;
  74         off = irq & 0x1F;
  75         __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index));
  76 }
  77
  78 static unsigned int wakeup_intr[4];
  79
  80 /**
  81  * tzic_set_wake_irq() - Set interrupt number "irq" in the TZIC as a wake-up source.
  82  *
  83  * @param  irq          interrupt source number
  84  * @param  enable       enable as wake-up if equal to non-zero
  85  *                      disble as wake-up if equal to zero
  86  *
  87  * @return       This function returns 0 on success.
  88  */
  89 static int tzic_set_wake_irq(unsigned int irq, unsigned int enable)
  90 {
  91         unsigned int index, off;
  92
  93         index = irq >> 5;
  94         off = irq & 0x1F;
  95
  96         if (index > 3)
  97                 return -EINVAL;
  98
  99         if (enable)
 100                 wakeup_intr[index] |= (1 << off);
 101         else
 102                 wakeup_intr[index] &= ~(1 << off);
 103
 104         return 0;
 105 }
 106
 107 static struct irq_chip mxc_tzic_chip = {
 108         .name = "MXC_TZIC",
 109         .ack = tzic_mask_irq,
 110         .mask = tzic_mask_irq,
 111         .unmask = tzic_unmask_irq,
 112         .set_wake = tzic_set_wake_irq,
 113 };
 114
 115 /*
 116  * This function initializes the TZIC hardware and disables all the
 117  * interrupts. It registers the interrupt enable and disable functions
 118  * to the kernel for each interrupt source.
 119  */
 120 void __init tzic_init_irq(void __iomem *irqbase)
 121 {
 122         int i;
 123
 124         tzic_base = irqbase;
 125         /* put the TZIC into the reset value with
 126          * all interrupts disabled
 127          */
 128         i = __raw_readl(tzic_base + TZIC_INTCNTL);
 129
 130         __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);
 131         __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);
 132         __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);
 133
 134         for (i = 0; i < 4; i++)
 135                 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
 136
 137         /* disable all interrupts */
 138         for (i = 0; i < 4; i++)
 139                 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
 140
 141         /* all IRQ no FIQ Warning :: No selection */
 142
 143         for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
 144                 set_irq_chip(i, &mxc_tzic_chip);
 145                 set_irq_handler(i, handle_level_irq);
 146                 set_irq_flags(i, IRQF_VALID);
 147         }
 148         pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
 149 }
 150
 151 /**
 152  * tzic_enable_wake() - enable wakeup interrupt
 153  *
 154  * @param is_idle               1 if called in idle loop (ENSET0 register);
 155  *                              0 to be used when called from low power entry
 156  * @return                      0 if successful; non-zero otherwise
 157  */
 158 int tzic_enable_wake(int is_idle)
 159 {
 160         unsigned int i, v;
 161
 162         __raw_writel(1, tzic_base + TZIC_DSMINT);
 163         if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
 164                 return -EAGAIN;
 165
 166         for (i = 0; i < 4; i++) {
 167                 v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) :
 168                         wakeup_intr[i];
 169                 __raw_writel(v, tzic_base + TZIC_WAKEUP0(i));
 170         }
 171
 172         return 0;
 173 }