release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-mxc/include/mach/mx25.h

   1 #ifndef __MACH_MX25_H__
   2 #define __MACH_MX25_H__
   3
   4 #define MX25_AIPS1_BASE_ADDR            0x43f00000
   5 #define MX25_AIPS1_BASE_ADDR_VIRT       0xfc000000
   6 #define MX25_AIPS1_SIZE                 SZ_1M
   7 #define MX25_AIPS2_BASE_ADDR            0x53f00000
   8 #define MX25_AIPS2_BASE_ADDR_VIRT       0xfc200000
   9 #define MX25_AIPS2_SIZE                 SZ_1M
  10 #define MX25_AVIC_BASE_ADDR             0x68000000
  11 #define MX25_AVIC_BASE_ADDR_VIRT        0xfc400000
  12 #define MX25_AVIC_SIZE                  SZ_1M
  13
  14 #define MX25_I2C1_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x80000)
  15 #define MX25_I2C3_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x84000)
  16 #define MX25_CAN1_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x88000)
  17 #define MX25_CAN2_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x8c000)
  18 #define MX25_I2C2_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x98000)
  19 #define MX25_CSPI1_BASE_ADDR            (MX25_AIPS1_BASE_ADDR + 0xa4000)
  20 #define MX25_IOMUXC_BASE_ADDR           (MX25_AIPS1_BASE_ADDR + 0xac000)
  21
  22 #define MX25_CRM_BASE_ADDR              (MX25_AIPS2_BASE_ADDR + 0x80000)
  23 #define MX25_GPT1_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0x90000)
  24 #define MX25_WDOG_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xdc000)
  25
  26 #define MX25_GPIO1_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000)
  27 #define MX25_GPIO2_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000)
  28 #define MX25_GPIO3_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000)
  29 #define MX25_GPIO4_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000)
  30
  31 #define MX25_IO_ADDRESS(x) (                                    \
  32         IMX_IO_ADDRESS(x, MX25_AIPS1) ?:                        \
  33         IMX_IO_ADDRESS(x, MX25_AIPS2) ?:                        \
  34         IMX_IO_ADDRESS(x, MX25_AVIC))
  35
  36 #define MX25_AIPS1_IO_ADDRESS(x) \
  37         (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
  38
  39 #define MX25_UART1_BASE_ADDR            0x43f90000
  40 #define MX25_UART2_BASE_ADDR            0x43f94000
  41 #define MX25_AUDMUX_BASE_ADDR           0x43fb0000
  42 #define MX25_UART3_BASE_ADDR            0x5000c000
  43 #define MX25_UART4_BASE_ADDR            0x50008000
  44 #define MX25_UART5_BASE_ADDR            0x5002c000
  45
  46 #define MX25_CSPI3_BASE_ADDR            0x50004000
  47 #define MX25_CSPI2_BASE_ADDR            0x50010000
  48 #define MX25_FEC_BASE_ADDR              0x50038000
  49 #define MX25_SSI2_BASE_ADDR             0x50014000
  50 #define MX25_SSI1_BASE_ADDR             0x50034000
  51 #define MX25_NFC_BASE_ADDR              0xbb000000
  52 #define MX25_DRYICE_BASE_ADDR           0x53ffc000
  53 #define MX25_LCDC_BASE_ADDR             0x53fbc000
  54 #define MX25_KPP_BASE_ADDR              0x43fa8000
  55 #define MX25_OTG_BASE_ADDR              0x53ff4000
  56 #define MX25_CSI_BASE_ADDR              0x53ff8000
  57
  58 #define MX25_INT_CSPI3          0
  59 #define MX25_INT_I2C1           3
  60 #define MX25_INT_I2C2           4
  61 #define MX25_INT_UART4          5
  62 #define MX25_INT_I2C3           10
  63 #define MX25_INT_SSI2           11
  64 #define MX25_INT_SSI1           12
  65 #define MX25_INT_CSPI2          13
  66 #define MX25_INT_CSPI1          14
  67 #define MX25_INT_CSI            17
  68 #define MX25_INT_UART3          18
  69 #define MX25_INT_KPP            24
  70 #define MX25_INT_DRYICE         25
  71 #define MX25_INT_UART2          32
  72 #define MX25_INT_NANDFC         33
  73 #define MX25_INT_LCDC           39
  74 #define MX25_INT_UART5          40
  75 #define MX25_INT_CAN1           43
  76 #define MX25_INT_CAN2           44
  77 #define MX25_INT_UART1          45
  78 #define MX25_INT_FEC            57
  79
  80 #endif /* ifndef __MACH_MX25_H__ */