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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / arm / plat-brcm / bcm5301x_pcie.c
blob65455909eae5379d8a00ce79c4f708c51650fac6
1 /* Modified by Broadcom Corp. Portions Copyright (c) Broadcom Corp, 2012. */
2 /*
3 * Northstar PCI-Express driver
4 * Only supports Root-Complex (RC) mode
5 *
6 * Notes:
7 * PCI Domains are being used to identify the PCIe port 1:1.
8 *
9 * Only MEM access is supported, PAX does not support IO.
10 *
11 * TODO:
12 * MSI interrupts,
13 * DRAM > 128 MBytes (e.g. DMA zones)
14 */
15
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/bug.h>
19 #include <linux/delay.h>
20 #include <linux/pci.h>
21 #include <linux/io.h>
22 #include <linux/ioport.h>
23 #include <linux/interrupt.h>
24
25 #include <mach/memory.h>
26 #include <mach/io_map.h>
27
28 #include <typedefs.h>
29 #include <bcmutils.h>
30 #include <hndsoc.h>
31 #include <siutils.h>
32 #include <hndcpu.h>
33 #include <hndpci.h>
34 #include <pcicfg.h>
35 #include <bcmdevs.h>
36 #include <bcmnvram.h>
37
38 /* Global SB handle */
39 extern si_t *bcm947xx_sih;
40 extern spinlock_t bcm947xx_sih_lock;
41
42 /* Convenience */
43 #define sih bcm947xx_sih
44 #define sih_lock bcm947xx_sih_lock
45
46 /*
47 * Register offset definitions
48 */
49 #define SOC_PCIE_CONTROL 0x000 /* a.k.a. CLK_CONTROL reg */
50 #define SOC_PCIE_PM_STATUS 0x008
51 #define SOC_PCIE_PM_CONTROL 0x00c /* in EP mode only ! */
52
53 #define SOC_PCIE_EXT_CFG_ADDR 0x120
54 #define SOC_PCIE_EXT_CFG_DATA 0x124
55 #define SOC_PCIE_CFG_ADDR 0x1f8
56 #define SOC_PCIE_CFG_DATA 0x1fc
57
58 #define SOC_PCIE_SYS_RC_INTX_EN 0x330
59 #define SOC_PCIE_SYS_RC_INTX_CSR 0x334
60 #define SOC_PCIE_SYS_HOST_INTR_EN 0x344
61 #define SOC_PCIE_SYS_HOST_INTR_CSR 0x348
62
63 #define SOC_PCIE_HDR_OFF 0x400 /* 256 bytes per function */
64
65 /* 32-bit 4KB in-bound mapping windows for Function 0..3, n=0..7 */
66 #define SOC_PCIE_SYS_IMAP0(f, n) (0xc00+((f)<<9)((n)<<2))
67 /* 64-bit in-bound mapping windows for func 0..3 */
68 #define SOC_PCIE_SYS_IMAP1(f) (0xc80+((f)<<3))
69 #define SOC_PCIE_SYS_IMAP2(f) (0xcc0+((f)<<3))
70 /* 64-bit in-bound address range n=0..2 */
71 #define SOC_PCIE_SYS_IARR(n) (0xd00+((n)<<3))
72 /* 64-bit out-bound address filter n=0..2 */
73 #define SOC_PCIE_SYS_OARR(n) (0xd20+((n)<<3))
74 /* 64-bit out-bound mapping windows n=0..2 */
75 #define SOC_PCIE_SYS_OMAP(n) (0xd40+((n)<<3))
76
77 #ifdef __nonexistent_regs_
78 #define SOC_PCIE_MDIO_CONTROL 0x128
79 #define SOC_PCIE_MDIO_RD_DATA 0x12c
80 #define SOC_PCIE_MDIO_WR_DATA 0x130
81 #define SOC_PCIE_CLK_STAT 0x1e0
82 #endif
83
84 extern int _memsize;
85
86 #define PCI_MAX_BUS 4
87 #define PLX_PRIM_SEC_BUS_NUM (0x00000201 | (PCI_MAX_BUS << 16))
88
89
90 #ifdef CONFIG_PCI
91
92 /*
93 * Forward declarations
94 */
95 static int soc_pci_setup(int nr, struct pci_sys_data *sys);
96 static struct pci_bus *soc_pci_scan_bus(int nr, struct pci_sys_data *sys);
97 static int soc_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
98 static int soc_pci_read_config(struct pci_bus *bus, unsigned int devfn,
99 int where, int size, u32 *val);
100 static int soc_pci_write_config(struct pci_bus *bus, unsigned int devfn,
101 int where, int size, u32 val);
102
103 #ifndef CONFIG_PCI_DOMAINS
104 #error CONFIG_PCI_DOMAINS is required
105 #endif
106
107 static int
108 sbpci_read_config_reg(struct pci_bus *bus, unsigned int devfn, int where,
109 int size, u32 *value)
110 {
111 unsigned long flags;
112 int ret;
113
114 spin_lock_irqsave(&sih_lock, flags);
115 ret = hndpci_read_config(sih, bus->number, PCI_SLOT(devfn),
116 PCI_FUNC(devfn), where, value, size);
117 spin_unlock_irqrestore(&sih_lock, flags);
118 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
119 }
120
121 static int
122 sbpci_write_config_reg(struct pci_bus *bus, unsigned int devfn, int where,
123 int size, u32 value)
124 {
125 unsigned long flags;
126 int ret;
127
128 spin_lock_irqsave(&sih_lock, flags);
129 ret = hndpci_write_config(sih, bus->number, PCI_SLOT(devfn),
130 PCI_FUNC(devfn), where, &value, size);
131 spin_unlock_irqrestore(&sih_lock, flags);
132 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
133 }
134
135 static struct pci_ops pcibios_ops = {
136 sbpci_read_config_reg,
137 sbpci_write_config_reg
138 };
139
140 /*
141 * PCIe host controller registers
142 * one entry per port
143 */
144 static struct resource soc_pcie_regs[3] = {
145 {
146 .name = "pcie0",
147 .start = 0x18012000,
148 .end = 0x18012fff,
149 .flags = IORESOURCE_MEM,
150 },
151 {
152 .name = "pcie1",
153 .start = 0x18013000,
154 .end = 0x18013fff,
155 .flags = IORESOURCE_MEM,
156 },
157 {
158 .name = "pcie2",
159 .start = 0x18014000,
160 .end = 0x18014fff,
161 .flags = IORESOURCE_MEM,
162 },
163 };
164
165 static struct resource soc_pcie_owin[3] = {
166 {
167 .name = "PCIe Outbound Window, Port 0",
168 .start = 0x08000000,
169 .end = 0x08000000 + SZ_128M - 1,
170 .flags = IORESOURCE_MEM,
171 },
172 {
173 .name = "PCIe Outbound Window, Port 1",
174 .start = 0x40000000,
175 .end = 0x40000000 + SZ_128M - 1,
176 .flags = IORESOURCE_MEM,
177 },
178 {
179 .name = "PCIe Outbound Window, Port 2",
180 .start = 0x48000000,
181 .end = 0x48000000 + SZ_128M - 1,
182 .flags = IORESOURCE_MEM,
183 },
184 };
185
186 /*
187 * Per port control structure
188 */
189 static struct soc_pcie_port {
190 struct resource *regs_res;
191 struct resource *owin_res;
192 void * __iomem reg_base;
193 unsigned short irqs[6];
194 struct hw_pci hw_pci;
195
196 bool enable;
197 bool link;
198 bool isswitch;
199 bool port1active;
200 bool port2active;
201 } soc_pcie_ports[4] = {
202 {
203 .irqs = {0, 0, 0, 0, 0, 0},
204 .hw_pci = {
205 .domain = 0,
206 .swizzle = NULL,
207 .nr_controllers = 1,
208 .map_irq = NULL,
209 },
210 .enable = 1,
211 .isswitch = 0,
212 .port1active = 0,
213 .port2active = 0,
214 },
215 {
216 .regs_res = & soc_pcie_regs[0],
217 .owin_res = & soc_pcie_owin[0],
218 .irqs = {158, 159, 160, 161, 162, 163},
219 .hw_pci = {
220 .domain = 1,
221 .swizzle = pci_std_swizzle,
222 .nr_controllers = 1,
223 .setup = soc_pci_setup,
224 .scan = soc_pci_scan_bus,
225 .map_irq = soc_pcie_map_irq,
226 },
227 .enable = 1,
228 .isswitch = 0,
229 .port1active = 0,
230 .port2active = 0,
231 },
232 {
233 .regs_res = & soc_pcie_regs[1],
234 .owin_res = & soc_pcie_owin[1],
235 .irqs = {164, 165, 166, 167, 168, 169},
236 .hw_pci = {
237 .domain = 2,
238 .swizzle = pci_std_swizzle,
239 .nr_controllers = 1,
240 .setup = soc_pci_setup,
241 .scan = soc_pci_scan_bus,
242 .map_irq = soc_pcie_map_irq,
243 },
244 .enable = 1,
245 .isswitch = 0,
246 .port1active = 0,
247 .port2active = 0,
248 },
249 {
250 .regs_res = & soc_pcie_regs[2],
251 .owin_res = & soc_pcie_owin[2],
252 .irqs = {170, 171, 172, 173, 174, 175},
253 .hw_pci = {
254 .domain = 3,
255 .swizzle = pci_std_swizzle,
256 .nr_controllers = 1,
257 .setup = soc_pci_setup,
258 .scan = soc_pci_scan_bus,
259 .map_irq = soc_pcie_map_irq,
260 },
261 .enable = 1,
262 .isswitch = 0,
263 .port1active = 0,
264 .port2active = 0,
265 }
266 };
267
268 /*
269 * Methods for accessing configuration registers
270 */
271 static struct pci_ops soc_pcie_ops = {
272 .read = soc_pci_read_config,
273 .write = soc_pci_write_config,
274 };
275
276 /*
277 * Per hnd si bus devices irq map
278 */
279 typedef struct si_bus_irq_map {
280 unsigned short device;
281 unsigned short unit;
282 unsigned short max_unit;
283 unsigned short irq;
284 } si_bus_irq_map_t;
285
286 si_bus_irq_map_t si_bus_irq_map[] = {
287 {BCM47XX_GMAC_ID, 0, 4, 179} /* 179, 180, 181, 182 */,
288 {BCM47XX_USB20H_ID, 0, 1, 111} /* 111 EHCI. */,
289 {BCM47XX_USB20H_ID, 0, 1, 111} /* 111 OHCI. */,
290 {BCM47XX_USB30H_ID, 0, 5, 112} /* 112, 113, 114, 115, 116. XHCI */
291 };
292 #define SI_BUS_IRQ_MAP_SIZE (sizeof(si_bus_irq_map) / sizeof(si_bus_irq_map_t))
293
294 static int si_bus_map_irq(struct pci_dev *pdev)
295 {
296 int i, irq = 0;
297
298 for (i = 0; i < SI_BUS_IRQ_MAP_SIZE; i++) {
299 if (pdev->device == si_bus_irq_map[i].device &&
300 si_bus_irq_map[i].unit < si_bus_irq_map[i].max_unit) {
301 irq = si_bus_irq_map[i].irq + si_bus_irq_map[i].unit;
302 si_bus_irq_map[i].unit++;
303 break;
304 }
305 }
306
307 return irq;
308 }
309
310 static struct soc_pcie_port *soc_pcie_sysdata2port(struct pci_sys_data *sysdata)
311 {
312 unsigned port;
313
314 port = sysdata->domain;
315 BUG_ON(port >= ARRAY_SIZE(soc_pcie_ports));
316 return & soc_pcie_ports[port];
317 }
318
319 static struct soc_pcie_port *soc_pcie_pdev2port(struct pci_dev *pdev)
320 {
321 return soc_pcie_sysdata2port(pdev->sysdata);
322 }
323
324 static struct soc_pcie_port *soc_pcie_bus2port(struct pci_bus *bus)
325 {
326 return soc_pcie_sysdata2port(bus->sysdata);
327 }
328
329 static struct pci_bus *soc_pci_scan_bus(int nr, struct pci_sys_data *sys)
330 {
331 return pci_scan_bus(sys->busnr, &soc_pcie_ops, sys);
332 }
333
334 static int soc_pcie_map_irq(struct pci_dev *pdev, u8 slot, u8 pin)
335 {
336 struct soc_pcie_port *port = soc_pcie_pdev2port(pdev);
337 int irq;
338
339 irq = port->irqs[5]; /* All INTx share int src 5, last per port */
340
341 pr_debug("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
342 pci_domain_nr(pdev->bus),
343 pdev->bus->number,
344 PCI_SLOT(pdev->devfn),
345 PCI_FUNC(pdev->devfn),
346 slot, pin, irq);
347
348 return irq;
349 }
350
351 static void __iomem *soc_pci_cfg_base(struct pci_bus *bus, unsigned int devfn, int where)
352 {
353 struct soc_pcie_port *port = soc_pcie_bus2port(bus);
354 int busno = bus->number;
355 int slot = PCI_SLOT(devfn);
356 int fn = PCI_FUNC(devfn);
357 void __iomem *base;
358 int offset;
359 int type;
360 u32 addr_reg;
361
362 base = port->reg_base;
363
364 /* If there is no link, just show the PCI bridge. */
365 if (!port->link && (busno > 0 || slot > 0))
366 return NULL;
367
368 if (busno == 0) {
369 if (slot >= 1)
370 return NULL;
371 type = slot;
372 __raw_writel(where & 0xffc, base + SOC_PCIE_EXT_CFG_ADDR);
373 offset = SOC_PCIE_EXT_CFG_DATA;
374 } else {
375 /* WAR for function num > 1 */
376 if (fn > 1)
377 return NULL;
378 type = 1;
379 addr_reg = (busno & 0xff) << 20 |
380 (slot << 15) |
381 (fn << 12) |
382 (where & 0xffc) |
383 (type & 0x3);
384
385 __raw_writel(addr_reg, base + SOC_PCIE_CFG_ADDR);
386 offset = SOC_PCIE_CFG_DATA;
387 }
388
389 return base + offset;
390 }
391
392 static void plx_pcie_switch_init(struct pci_bus *bus, unsigned int devfn)
393 {
394 struct soc_pcie_port *port = soc_pcie_bus2port(bus);
395 u32 dRead = 0;
396 u16 bm = 0;
397 int bus_inc = port->hw_pci.domain - 1;
398
399 soc_pci_read_config(bus, devfn, 0x100, 4, &dRead);
400 printk("PCIE: Doing PLX switch Init...Test Read = %08x\n", (unsigned int)dRead);
401
402 /* Debug control register. */
403 soc_pci_read_config(bus, devfn, 0x1dc, 4, &dRead);
404 dRead &= ~(1<<22);
405
406 soc_pci_write_config(bus, devfn, 0x1dc, 4, dRead);
407
408 /* Set GPIO enables. */
409 soc_pci_read_config(bus, devfn, 0x62c, 4, &dRead);
410
411 printk("PCIE: Doing PLX switch Init...GPIO Read = %08x\n", (unsigned int)dRead);
412
413 dRead &= ~((1 << 0) | (1 << 1) | (1 << 3));
414 dRead |= ((1 << 4) | (1 << 5) | (1 << 7));
415
416 soc_pci_write_config(bus, devfn, 0x62c, 4, dRead);
417
418 mdelay(50);
419 dRead |= ((1<<0)|(1<<1));
420 soc_pci_write_config(bus, devfn, 0x62c, 4, dRead);
421
422 soc_pci_read_config(bus, devfn, 0x4, 2, &bm);
423 #if NS_PCI_DEBUG
424 printk("bus master: %08x\n", bm);
425 #endif
426 bm |= 0x06;
427 soc_pci_write_config(bus, devfn, 0x4, 2, bm);
428 bm = 0;
429 #if NS_PCI_DEBUG
430 soc_pci_read_config(bus, devfn, 0x4, 2, &bm);
431 printk("bus master after: %08x\n", bm);
432 bm = 0;
433 #endif
434 /* Bus 1 if the upstream port of the switch.
435 * Bus 2 has the two downstream ports, one on each device number.
436 */
437 if (bus->number == (bus_inc + 1)) {
438 soc_pci_write_config(bus, devfn, 0x18, 4, PLX_PRIM_SEC_BUS_NUM);
439
440 /* TODO: We need to scan all outgoing windows,
441 * to look for a base limit pair for this register.
442 */
443 /* MEM_BASE, MEM_LIM require 1MB alignment */
444 BUG_ON((port->owin_res->start >> 16) & 0xf);
445 soc_pci_write_config(bus, devfn, PCI_MEMORY_BASE, 2,
446 port->owin_res->start >> 16);
447 BUG_ON(((port->owin_res->start + SZ_32M) >> 16) & 0xf);
448 soc_pci_write_config(bus, devfn, PCI_MEMORY_LIMIT, 2,
449 (port->owin_res->start + SZ_32M) >> 16);
450 } else if (bus->number == (bus_inc + 2)) {
451 /* TODO: I need to fix these hard coded addresses. */
452 if (devfn == 0x8) {
453 soc_pci_write_config(bus, devfn, 0x18, 4,
454 (0x00000000 | ((bus->number + 1) << 16) |
455 ((bus->number + 1) << 8) | bus->number));
456 BUG_ON((port->owin_res->start + SZ_48M >> 16) & 0xf);
457 soc_pci_write_config(bus, devfn, PCI_MEMORY_BASE, 2,
458 port->owin_res->start + SZ_48M >> 16);
459 BUG_ON(((port->owin_res->start + SZ_48M + SZ_32M) >> 16) & 0xf);
460 soc_pci_write_config(bus, devfn, PCI_MEMORY_LIMIT, 2,
461 (port->owin_res->start + SZ_48M + SZ_32M) >> 16);
462 soc_pci_read_config(bus, devfn, 0x7A, 2, &bm);
463 if (bm & PCI_EXP_LNKSTA_DLLLA)
464 port->port1active = 1;
465 printk("bm = %04x\n devfn = = %08x, bus = %08x\n", bm, devfn, bus->number);
466 } else if (devfn == 0x10) {
467 soc_pci_write_config(bus, devfn, 0x18, 4,
468 (0x00000000 | ((bus->number + 2) << 16) |
469 ((bus->number + 2) << 8) | bus->number));
470 BUG_ON((port->owin_res->start + (SZ_48M * 2) >> 16) & 0xf);
471 soc_pci_write_config(bus, devfn, PCI_MEMORY_BASE, 2,
472 port->owin_res->start + (SZ_48M * 2) >> 16);
473 BUG_ON(((port->owin_res->start + (SZ_48M * 2) + SZ_32M) >> 16) & 0xf);
474 soc_pci_write_config(bus, devfn, PCI_MEMORY_LIMIT, 2,
475 (port->owin_res->start + (SZ_48M * 2) + SZ_32M) >> 16);
476 soc_pci_read_config(bus, devfn, 0x7A, 2, &bm);
477 if (bm & PCI_EXP_LNKSTA_DLLLA)
478 port->port2active = 1;
479 printk("bm = %04x\n devfn = = %08x, bus = %08x\n", bm, devfn, bus->number);
480 }
481 }
482 }
483
484 static int soc_pci_read_config(struct pci_bus *bus, unsigned int devfn,
485 int where, int size, u32 *val)
486 {
487 void __iomem *base;
488 u32 data_reg;
489 struct soc_pcie_port *port = soc_pcie_bus2port(bus);
490 int bus_inc = port->hw_pci.domain - 1;
491
492 if ((bus->number > (bus_inc + 4))) {
493 *val = ~0UL;
494 return PCIBIOS_SUCCESSFUL;
495 }
496
497 if (port->isswitch == 1) {
498 if (bus->number == (bus_inc + 2)) {
499 if (!((devfn == 0x8) || (devfn == 0x10))) {
500 *val = ~0UL;
501 return PCIBIOS_SUCCESSFUL;
502 }
503 } else if ((bus->number == (bus_inc + 3)) || (bus->number == (bus_inc + 4))) {
504 if (devfn != 0) {
505 *val = ~0UL;
506 return PCIBIOS_SUCCESSFUL;
507 } else if ((bus->number == (bus_inc + 3)) && (port->port1active == 0)) {
508 *val = ~0UL;
509 return PCIBIOS_SUCCESSFUL;
510 } else if ((bus->number == (bus_inc + 4)) && (port->port2active == 0)) {
511 *val = ~0UL;
512 return PCIBIOS_SUCCESSFUL;
513 }
514 }
515 }
516
517 base = soc_pci_cfg_base(bus, devfn, where);
518 if (base == NULL) {
519 *val = ~0UL;
520 return PCIBIOS_SUCCESSFUL;
521 }
522
523 data_reg = __raw_readl(base);
524
525 /* NS: CLASS field is R/O, and set to wrong 0x200 value */
526 if (bus->number == 0 && devfn == 0) {
527 if ((where & 0xffc) == PCI_CLASS_REVISION) {
528 /*
529 * RC's class is 0x0280, but Linux PCI driver needs 0x604
530 * for a PCIe bridge. So we must fixup the class code
531 * to 0x604 here.
532 */
533 data_reg &= 0xff;
534 data_reg |= 0x604 << 16;
535 }
536 }
537
538 if ((bus->number == (bus_inc + 1)) && (port->isswitch == 0) &&
539 (where == 0) && (((data_reg >> 16) & 0x0000FFFF) == 0x00008603)) {
540 plx_pcie_switch_init(bus, devfn);
541 port->isswitch = 1;
542 }
543 if ((bus->number == (bus_inc + 2)) && (port->isswitch == 1) &&
544 (where == 0) && (((data_reg >> 16) & 0x0000FFFF) == 0x00008603))
545 plx_pcie_switch_init(bus, devfn);
546
547 /* HEADER_TYPE=00 indicates the port in EP mode */
548
549 if (size == 4) {
550 *val = data_reg;
551 } else if (size < 4) {
552 u32 mask = (1 << (size * 8)) - 1;
553 int shift = (where % 4) * 8;
554 *val = (data_reg >> shift) & mask;
555 }
556
557 return PCIBIOS_SUCCESSFUL;
558 }
559
560 static int soc_pci_write_config(struct pci_bus *bus, unsigned int devfn,
561 int where, int size, u32 val)
562 {
563 void __iomem *base;
564 u32 data_reg;
565 struct soc_pcie_port *port = soc_pcie_bus2port(bus);
566 int bus_inc = port->hw_pci.domain - 1;
567
568 if (bus->number > (bus_inc + 4))
569 return PCIBIOS_SUCCESSFUL;
570
571 if ((bus->number == (bus_inc + 2)) && (port->isswitch == 1)) {
572 if (!((devfn == 0x8) || (devfn == 0x10)))
573 return PCIBIOS_SUCCESSFUL;
574 }
575 else if ((bus->number == (bus_inc + 3)) && (port->isswitch == 1)) {
576 if (devfn != 0)
577 return PCIBIOS_SUCCESSFUL;
578 }
579 else if ((bus->number == (bus_inc + 4)) && (port->isswitch == 1)) {
580 if (devfn != 0)
581 return PCIBIOS_SUCCESSFUL;
582 }
583
584 base = soc_pci_cfg_base(bus, devfn, where);
585 if (base == NULL) {
586 return PCIBIOS_SUCCESSFUL;
587 }
588
589 if (size < 4) {
590 u32 mask = (1 << (size * 8)) - 1;
591 int shift = (where % 4) * 8;
592 data_reg = __raw_readl(base);
593 data_reg &= ~(mask << shift);
594 data_reg |= (val & mask) << shift;
595 } else {
596 data_reg = val;
597 }
598
599 __raw_writel(data_reg, base);
600
601 return PCIBIOS_SUCCESSFUL;
602 }
603
604 static int soc_pci_setup(int nr, struct pci_sys_data *sys)
605 {
606 struct soc_pcie_port *port = soc_pcie_sysdata2port(sys);
607
608 BUG_ON(request_resource(&iomem_resource, port->owin_res));
609
610 sys->resource[0] = port->owin_res;
611 sys->private_data = port;
612 return 1;
613 }
614
615 /*
616 * Check link status, return 0 if link is up in RC mode,
617 * otherwise return non-zero
618 */
619 static int __init noinline soc_pcie_check_link(struct soc_pcie_port *port, uint32 allow_gen2)
620 {
621 u32 devfn = 0;
622 u16 pos, tmp16;
623 u8 nlw, tmp8;
624 u32 tmp32;
625
626 struct pci_sys_data sd = {
627 .domain = port->hw_pci.domain,
628 };
629 struct pci_bus bus = {
630 .number = 0,
631 .ops = &soc_pcie_ops,
632 .sysdata = &sd,
633 };
634
635 if (!port->enable)
636 return -EINVAL;
637
638
639 pci_bus_read_config_dword(&bus, devfn, 0xdc, &tmp32);
640 tmp32 &= ~0xf;
641 if (allow_gen2)
642 tmp32 |= 2;
643 else {
644 /* force PCIE GEN1 */
645 tmp32 |= 1;
646 }
647 pci_bus_write_config_dword(&bus, devfn, 0xdc, tmp32);
648
649 /* See if the port is in EP mode, indicated by header type 00 */
650 pci_bus_read_config_byte(&bus, devfn, PCI_HEADER_TYPE, &tmp8);
651 if (tmp8 != PCI_HEADER_TYPE_BRIDGE) {
652 pr_info("PCIe port %d in End-Point mode - ignored\n",
653 port->hw_pci.domain);
654 return -ENODEV;
655 }
656
657 /* NS PAX only changes NLW field when card is present */
658 pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
659 pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_LNKSTA, &tmp16);
660
661 #ifdef DEBUG
662 pr_debug("PCIE%d: LINKSTA reg %#x val %#x\n", port->hw_pci.domain,
663 pos+PCI_EXP_LNKSTA, tmp16);
664 #endif
665
666 nlw = (tmp16 & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
667 port->link = tmp16 & PCI_EXP_LNKSTA_DLLLA;
668
669 if (nlw != 0)
670 port->link = 1;
671
672 #ifdef DEBUG
673 for (; pos < 0x100; pos += 2) {
674 pci_bus_read_config_word(&bus, devfn, pos, &tmp16);
675 if (tmp16)
676 pr_debug("reg[%#x]=%#x, ", pos, tmp16);
677 }
678 #endif
679 pr_info("PCIE%d link=%d\n", port->hw_pci.domain, port->link);
680
681 return ((port->link)? 0: -ENOSYS);
682 }
683
684 /*
685 * Initializte the PCIe controller
686 */
687 static void __init soc_pcie_hw_init(struct soc_pcie_port *port)
688 {
689 u32 devfn = 0;
690 u32 tmp32;
691 struct pci_sys_data sd = {
692 .domain = port->hw_pci.domain,
693 };
694 struct pci_bus bus = {
695 .number = 0,
696 .ops = &soc_pcie_ops,
697 .sysdata = &sd,
698 };
699
700 /* Change MPS and MRRS to 512 */
701 pci_bus_read_config_word(&bus, devfn, 0x4d4, &tmp32);
702 tmp32 &= ~7;
703 tmp32 |= 2;
704 pci_bus_write_config_word(&bus, devfn, 0x4d4, tmp32);
705
706 pci_bus_read_config_dword(&bus, devfn, 0xb4, &tmp32);
707 tmp32 &= ~((7 << 12) | (7 << 5));
708 tmp32 |= (2 << 12) | (2 << 5);
709 pci_bus_write_config_dword(&bus, devfn, 0xb4, tmp32);
710
711 /* Turn-on Root-Complex (RC) mode, from reset defailt of EP */
712
713 /* The mode is set by straps, can be overwritten via DMU
714 register <cru_straps_control> bit 5, "1" means RC
715 */
716
717 /* Send a downstream reset */
718 __raw_writel(0x3, port->reg_base + SOC_PCIE_CONTROL);
719 udelay(250);
720 __raw_writel(0x1, port->reg_base + SOC_PCIE_CONTROL);
721 mdelay(250);
722
723 /* TBD: take care of PM, check we're on */
724 }
725
726 /*
727 * Setup the address translation
728 */
729 static void __init soc_pcie_map_init(struct soc_pcie_port *port)
730 {
731 unsigned size, i;
732 u32 addr;
733
734 /*
735 * NOTE:
736 * All PCI-to-CPU address mapping are 1:1 for simplicity
737 */
738
739 /* Outbound address translation setup */
740 size = resource_size(port->owin_res);
741 addr = port->owin_res->start;
742 BUG_ON(!addr);
743 BUG_ON(addr & ((1 << 25) - 1)); /* 64MB alignment */
744
745 for (i = 0; i < 3; i++) {
746 const unsigned win_size = SZ_64M;
747 /* 64-bit LE regs, write low word, high is 0 at reset */
748 __raw_writel(addr, port->reg_base + SOC_PCIE_SYS_OMAP(i));
749 __raw_writel(addr|0x1, port->reg_base + SOC_PCIE_SYS_OARR(i));
750 addr += win_size;
751 if (size >= win_size)
752 size -= win_size;
753 if (size == 0)
754 break;
755 }
756 WARN_ON(size > 0);
757
758 /*
759 * Inbound address translation setup
760 * Northstar only maps up to 128 MiB inbound, DRAM could be up to 1 GiB.
761 *
762 * For now allow access to entire DRAM, assuming it is less than 128MiB,
763 * otherwise DMA bouncing mechanism may be required.
764 * Also consider DMA mask to limit DMA physical address
765 */
766 size = min(_memsize, SZ_128M);
767 addr = PHYS_OFFSET;
768
769 size >>= 20; /* In MB */
770 size &= 0xff; /* Size is an 8-bit field */
771
772 WARN_ON(size == 0);
773 /* 64-bit LE regs, write low word, high is 0 at reset */
774 __raw_writel(addr | 0x1,
775 port->reg_base + SOC_PCIE_SYS_IMAP1(0));
776 __raw_writel(addr | size,
777 port->reg_base + SOC_PCIE_SYS_IARR(1));
778 #ifdef CONFIG_SPARSEMEM
779 addr = PHYS_OFFSET2 + SZ_128M;
780 __raw_writel(addr | 0x1,
781 port->reg_base + SOC_PCIE_SYS_IMAP2(0));
782 __raw_writel(addr | size,
783 port->reg_base + SOC_PCIE_SYS_IARR(2));
784 #endif
785 }
786
787 /*
788 * Setup PCIE Host bridge
789 */
790 static void __init noinline soc_pcie_bridge_init(struct soc_pcie_port *port)
791 {
792 u32 devfn = 0;
793 u8 tmp8;
794 u16 tmp16;
795
796 /* Fake <bus> object */
797 struct pci_sys_data sd = {
798 .domain = port->hw_pci.domain,
799 };
800 struct pci_bus bus = {
801 .number = 0,
802 .ops = &soc_pcie_ops,
803 .sysdata = &sd,
804 };
805
806
807 pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0);
808 pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1);
809 pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 4);
810
811 pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8);
812 pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8);
813 pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8);
814
815 /* MEM_BASE, MEM_LIM require 1MB alignment */
816 BUG_ON((port->owin_res->start >> 16) & 0xf);
817 #ifdef DEBUG
818 pr_debug("%s: membase %#x memlimit %#x\n", __FUNCTION__,
819 port->owin_res->start, port->owin_res->end+1);
820 #endif
821 pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE,
822 port->owin_res->start >> 16);
823 BUG_ON(((port->owin_res->end+1) >> 16) & 0xf);
824 pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT,
825 (port->owin_res->end+1) >> 16);
826
827 /* These registers are not supported on the NS */
828 pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, 0);
829 pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, 0);
830
831 /* Force class to that of a Bridge */
832 pci_bus_write_config_word(&bus, devfn, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
833
834 pci_bus_read_config_word(&bus, devfn, PCI_CLASS_DEVICE, &tmp16);
835 pci_bus_read_config_word(&bus, devfn, PCI_MEMORY_BASE, &tmp16);
836 pci_bus_read_config_word(&bus, devfn, PCI_MEMORY_LIMIT, &tmp16);
837 }
838
839
840 int
841 pcibios_enable_resources(struct pci_dev *dev)
842 {
843 u16 cmd, old_cmd;
844 int idx;
845 struct resource *r;
846
847 /* External PCI only */
848 if (dev->bus->number == 0)
849 return 0;
850
851 pci_read_config_word(dev, PCI_COMMAND, &cmd);
852 old_cmd = cmd;
853 for (idx = 0; idx < 6; idx++) {
854 r = &dev->resource[idx];
855 if (r->flags & IORESOURCE_IO)
856 cmd |= PCI_COMMAND_IO;
857 if (r->flags & IORESOURCE_MEM)
858 cmd |= PCI_COMMAND_MEMORY;
859 }
860 if (dev->resource[PCI_ROM_RESOURCE].start)
861 cmd |= PCI_COMMAND_MEMORY;
862 if (cmd != old_cmd) {
863 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
864 pci_write_config_word(dev, PCI_COMMAND, cmd);
865 }
866 return 0;
867 }
868
869 static void
870 bcm5301x_usb_power_on(int coreid)
871 {
872 int enable_usb;
873
874 if (coreid == NS_USB20_CORE_ID) {
875 enable_usb = getgpiopin(NULL, "usbport1", GPIO_PIN_NOTDEFINED);
876 if (enable_usb != GPIO_PIN_NOTDEFINED) {
877 int enable_usb_mask = 1 << enable_usb;
878
879 si_gpioout(sih, enable_usb_mask, enable_usb_mask, GPIO_DRV_PRIORITY);
880 si_gpioouten(sih, enable_usb_mask, enable_usb_mask, GPIO_DRV_PRIORITY);
881 }
882
883 enable_usb = getgpiopin(NULL, "usbport2", GPIO_PIN_NOTDEFINED);
884 if (enable_usb != GPIO_PIN_NOTDEFINED) {
885 int enable_usb_mask = 1 << enable_usb;
886
887 si_gpioout(sih, enable_usb_mask, enable_usb_mask, GPIO_DRV_PRIORITY);
888 si_gpioouten(sih, enable_usb_mask, enable_usb_mask, GPIO_DRV_PRIORITY);
889 }
890 }
891 else if (coreid == NS_USB30_CORE_ID) {
892 enable_usb = getgpiopin(NULL, "usbport2", GPIO_PIN_NOTDEFINED);
893 if (enable_usb != GPIO_PIN_NOTDEFINED) {
894 int enable_usb_mask = 1 << enable_usb;
895
896 si_gpioout(sih, enable_usb_mask, enable_usb_mask, GPIO_DRV_PRIORITY);
897 si_gpioouten(sih, enable_usb_mask, enable_usb_mask, GPIO_DRV_PRIORITY);
898 }
899 }
900 }
901
902 static void
903 bcm5301x_usb20_phy_init(void)
904 {
905 uint32 dmu_base;
906 uint32 *cru_clkset_key;
907 uint32 *cru_usb2_control;
908
909 /* Check Chip ID */
910 if (!BCM4707_CHIP(CHIPID(sih->chip)))
911 return;
912
913 /* Check Package ID */
914 if (sih->chippkg == BCM4709_PKG_ID) {
915 return;
916 }
917 else if (sih->chippkg == BCM4707_PKG_ID || sih->chippkg == BCM4708_PKG_ID) {
918 dmu_base = (uint32)REG_MAP(0x1800c000, 4096);
919 cru_clkset_key = (uint32 *)(dmu_base + 0x180);
920 cru_usb2_control = (uint32 *)(dmu_base + 0x164);
921
922 /* unlock */
923 writel(0x0000ea68, cru_clkset_key);
924
925 /* fill value */
926 writel(0x00dd10c3, cru_usb2_control);
927
928 /* lock */
929 writel(0x00000000, cru_clkset_key);
930
931 REG_UNMAP((void *)dmu_base);
932 }
933 }
934
935 static void
936 bcm5301x_usb30_phy_init(void)
937 {
938 uint32 ccb_mii_base;
939 uint32 dmu_base;
940 uint32 *ccb_mii_mng_ctrl_addr;
941 uint32 *ccb_mii_mng_cmd_data_addr;
942 uint32 *cru_rst_addr;
943 uint32 cru_straps_ctrl;
944 uint32 usb3_idm_idm_base;
945 uint32 *usb3_idm_idm_reset_ctrl_addr;
946
947 /* Check Chip ID */
948 if (!BCM4707_CHIP(CHIPID(sih->chip)))
949 return;
950
951 dmu_base = (uint32)REG_MAP(0x1800c000, 4096);
952 /* Check strapping of PCIE/USB3 SEL */
953 cru_straps_ctrl = readl((uint32 *)(dmu_base + 0x2a0));
954 if ((cru_straps_ctrl & 0x10) == 0)
955 goto out;
956 cru_rst_addr = (uint32 *)(dmu_base + 0x184);
957
958 /* Reg map */
959 ccb_mii_base = (uint32)REG_MAP(0x18003000, 4096);
960 ccb_mii_mng_ctrl_addr = (uint32 *)(ccb_mii_base + 0x0);
961 ccb_mii_mng_cmd_data_addr = (uint32 *)(ccb_mii_base + 0x4);
962 usb3_idm_idm_base = (uint32)REG_MAP(0x18105000, 4096);
963 usb3_idm_idm_reset_ctrl_addr = (uint32 *)(usb3_idm_idm_base + 0x800);
964
965 /* Perform USB3 system soft reset */
966 writel(0x00000001, usb3_idm_idm_reset_ctrl_addr);
967
968 /* Enable MDIO. Setting MDCDIV as 26 */
969 writel(0x0000009a, ccb_mii_mng_ctrl_addr);
970 OSL_DELAY(2);
971
972 if (CHIPID(sih->chip) == BCM4707_CHIP_ID) {
973 /* PLL30 block */
974 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
975 writel(0x587e8000, ccb_mii_mng_cmd_data_addr);
976
977 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
978 writel(0x582a6400, ccb_mii_mng_cmd_data_addr);
979
980 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
981 writel(0x587e80e0, ccb_mii_mng_cmd_data_addr);
982
983 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
984 writel(0x580a009c, ccb_mii_mng_cmd_data_addr);
985
986 /* Enable SSC */
987 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
988 writel(0x587e8040, ccb_mii_mng_cmd_data_addr);
989
990 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
991 writel(0x580a21d3, ccb_mii_mng_cmd_data_addr);
992
993 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
994 writel(0x58061003, ccb_mii_mng_cmd_data_addr);
995
996 /* Waiting MII Mgt interface idle */
997 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
998
999 /* Deasserting USB3 system reset */
1000 writel(0x00000000, usb3_idm_idm_reset_ctrl_addr);
1001 }
1002 else if (CHIPID(sih->chip) == BCM53018_CHIP_ID) {
1003 /* USB3 PLL Block */
1004 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
1005 writel(0x587e8000, ccb_mii_mng_cmd_data_addr);
1006
1007 /* Assert Ana_Pllseq start */
1008 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
1009 writel(0x58061000, ccb_mii_mng_cmd_data_addr);
1010
1011 /* Assert CML Divider ratio to 26 */
1012 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
1013 writel(0x582a6400, ccb_mii_mng_cmd_data_addr);
1014
1015 /* Asserting PLL Reset */
1016 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
1017 writel(0x582ec000, ccb_mii_mng_cmd_data_addr);
1018
1019 /* Deaaserting PLL Reset */
1020 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
1021 writel(0x582e8000, ccb_mii_mng_cmd_data_addr);
1022
1023 /* Waiting MII Mgt interface idle */
1024 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
1025
1026 /* Deasserting USB3 system reset */
1027 writel(0x00000000, usb3_idm_idm_reset_ctrl_addr);
1028
1029 /* PLL frequency monitor enable */
1030 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
1031 writel(0x58069000, ccb_mii_mng_cmd_data_addr);
1032
1033 /* PIPE Block */
1034 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
1035 writel(0x587e8060, ccb_mii_mng_cmd_data_addr);
1036
1037 /* CMPMAX & CMPMINTH setting */
1038 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
1039 writel(0x580af30d, ccb_mii_mng_cmd_data_addr);
1040
1041 /* DEGLITCH MIN & MAX setting */
1042 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
1043 writel(0x580e6302, ccb_mii_mng_cmd_data_addr);
1044
1045 /* TXPMD block */
1046 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
1047 writel(0x587e8040, ccb_mii_mng_cmd_data_addr);
1048
1049 /* Enabling SSC */
1050 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
1051 writel(0x58061003, ccb_mii_mng_cmd_data_addr);
1052
1053 /* Waiting MII Mgt interface idle */
1054 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000);
1055 }
1056
1057 /* Reg unmap */
1058 REG_UNMAP((void *)ccb_mii_base);
1059 REG_UNMAP((void *)usb3_idm_idm_base);
1060
1061 out:
1062 REG_UNMAP((void *)dmu_base);
1063 }
1064
1065 static void
1066 bcm5301x_usb_phy_init(int coreid)
1067 {
1068 if (coreid == NS_USB20_CORE_ID) {
1069 bcm5301x_usb20_phy_init();
1070 }
1071 else if (coreid == NS_USB30_CORE_ID) {
1072 bcm5301x_usb30_phy_init();
1073 }
1074 }
1075
1076 int
1077 pcibios_enable_device(struct pci_dev *dev, int mask)
1078 {
1079 ulong flags;
1080 uint coreidx, coreid;
1081 void *regs;
1082 int rc = -1;
1083
1084 /* External PCI device enable */
1085 if (dev->bus->number != 0)
1086 return pcibios_enable_resources(dev);
1087
1088 /* These cores come out of reset enabled */
1089 if (dev->device == NS_IHOST_CORE_ID ||
1090 dev->device == CC_CORE_ID)
1091 return 0;
1092
1093 spin_lock_irqsave(&sih_lock, flags);
1094
1095 regs = si_setcoreidx(sih, PCI_SLOT(dev->devfn));
1096 coreidx = si_coreidx(sih);
1097 coreid = si_coreid(sih);
1098
1099 if (!regs) {
1100 printk(KERN_ERR "WARNING! PCIBIOS_DEVICE_NOT_FOUND\n");
1101 goto out;
1102 }
1103
1104 /* OHCI/EHCI only initialize one time */
1105 if (coreid == NS_USB20_CORE_ID && si_iscoreup(sih)) {
1106 rc = 0;
1107 goto out;
1108 }
1109
1110 si_core_reset(sih, 0, 0);
1111
1112 if (coreid == NS_USB20_CORE_ID || coreid == NS_USB30_CORE_ID) {
1113 /* Set gpio HIGH to turn on USB VBUS power */
1114 bcm5301x_usb_power_on(coreid);
1115
1116 /* USB PHY init */
1117 bcm5301x_usb_phy_init(coreid);
1118 }
1119
1120 rc = 0;
1121 out:
1122 si_setcoreidx(sih, coreidx);
1123 spin_unlock_irqrestore(&sih_lock, flags);
1124
1125 return rc;
1126 }
1127
1128 bool __devinit
1129 plat_fixup_bus(struct pci_bus *b)
1130 {
1131 struct list_head *ln;
1132 struct pci_dev *d;
1133 u8 irq;
1134
1135 printk("PCI: Fixing up bus %d\n", b->number);
1136
1137 /* Fix up SB */
1138 if (((struct pci_sys_data *)b->sysdata)->domain == 0) {
1139 for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
1140 d = pci_dev_b(ln);
1141 /* Fix up interrupt lines */
1142 pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
1143 d->irq = si_bus_map_irq(d);
1144 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
1145 }
1146 return TRUE;
1147 }
1148
1149 return FALSE;
1150 }
1151
1152 static int __init allow_gen2_rc(struct soc_pcie_port *port)
1153 {
1154 uint32 vendorid, devid, chipid, chiprev;
1155 uint32 val, bar, base;
1156 int allow = 1;
1157 char *p;
1158
1159 /* Force GEN1 if specified in NVRAM */
1160 if ((p = nvram_get("forcegen1rc")) != NULL && simple_strtoul(p, NULL, 0) == 1) {
1161 printk(KERN_NOTICE "Force PCIE RC to GEN1 only\n");
1162 return 0;
1163 }
1164
1165 /* Read PCI vendor/device ID's */
1166 __raw_writel(0x0, port->reg_base + SOC_PCIE_CFG_ADDR);
1167 val = __raw_readl(port->reg_base + SOC_PCIE_CFG_DATA);
1168 vendorid = val & 0xffff;
1169 devid = val >> 16;
1170 if (vendorid == VENDOR_BROADCOM &&
1171 (devid == BCM4360_CHIP_ID || devid == BCM4360_D11AC_ID ||
1172 devid == BCM4360_D11AC2G_ID || devid == BCM4360_D11AC5G_ID ||
1173 devid == BCM4352_D11AC_ID || devid == BCM4352_D11AC2G_ID ||
1174 devid == BCM4352_D11AC5G_ID)) {
1175 /* Config BAR0 */
1176 bar = port->owin_res->start;
1177 __raw_writel(0x10, port->reg_base + SOC_PCIE_CFG_ADDR);
1178 __raw_writel(bar, port->reg_base + SOC_PCIE_CFG_DATA);
1179 /* Config BAR0 window to access chipc */
1180 __raw_writel(0x80, port->reg_base + SOC_PCIE_CFG_ADDR);
1181 __raw_writel(SI_ENUM_BASE, port->reg_base + SOC_PCIE_CFG_DATA);
1182
1183 /* Enable memory resource */
1184 __raw_writel(0x4, port->reg_base + SOC_PCIE_CFG_ADDR);
1185 val = __raw_readl(port->reg_base + SOC_PCIE_CFG_DATA);
1186 val |= PCI_COMMAND_MEMORY;
1187 __raw_writel(val, port->reg_base + SOC_PCIE_CFG_DATA);
1188 /* Enable memory and bus master */
1189 __raw_writel(0x6, port->reg_base + SOC_PCIE_HDR_OFF + 4);
1190
1191 /* Read CHIP ID */
1192 base = (uint32)ioremap(bar, 0x1000);
1193 val = __raw_readl(base);
1194 iounmap((void *)base);
1195 chipid = val & 0xffff;
1196 chiprev = (val >> 16) & 0xf;
1197 if ((chipid == BCM4360_CHIP_ID ||
1198 chipid == BCM43460_CHIP_ID ||
1199 chipid == BCM4352_CHIP_ID) && (chiprev < 3))
1200 allow = 0;
1201 }
1202 return (allow);
1203 }
1204
1205 static void __init
1206 bcm5301x_3rd_pcie_init(void)
1207 {
1208 uint32 cru_straps_ctrl;
1209 uint32 ccb_mii_base;
1210 uint32 dmu_base;
1211 uint32 *ccb_mii_mng_ctrl_addr;
1212 uint32 *ccb_mii_mng_cmd_data_addr;
1213
1214 /* Check Chip ID */
1215 if (!BCM4707_CHIP(CHIPID(sih->chip)) ||
1216 (sih->chippkg != BCM4708_PKG_ID && sih->chippkg != BCM4709_PKG_ID))
1217 return;
1218
1219 /* Reg map */
1220 dmu_base = (uint32)REG_MAP(0x1800c000, 4096);
1221
1222 /* Check strapping of PCIE/USB3 SEL */
1223 cru_straps_ctrl = readl((uint32 *)(dmu_base + 0x2a0));
1224 /* PCIE mode is not selected */
1225 if (cru_straps_ctrl & 0x10)
1226 goto out;
1227
1228 /* Reg map */
1229 ccb_mii_base = (uint32)REG_MAP(0x18003000, 4096);
1230 ccb_mii_mng_ctrl_addr = (uint32 *)(ccb_mii_base + 0x0);
1231 ccb_mii_mng_cmd_data_addr = (uint32 *)(ccb_mii_base + 0x4);
1232
1233 /* MDIO setting. set MDC-> MDCDIV is 7'd8 */
1234 writel(0x00000088, ccb_mii_mng_ctrl_addr);
1235 SPINWAIT(((readl(ccb_mii_mng_ctrl_addr) >> 8 & 1) == 1), 1000);
1236 /* PCIE PLL block register (base 0x8000) */
1237 writel(0x57fe8000, ccb_mii_mng_cmd_data_addr);
1238 SPINWAIT(((readl(ccb_mii_mng_ctrl_addr) >> 8 & 1) == 1), 1000);
1239 /* Check PCIE PLL lock status */
1240 writel(0x67c60000, ccb_mii_mng_cmd_data_addr);
1241 SPINWAIT(((readl(ccb_mii_mng_ctrl_addr) >> 8 & 1) == 1), 1000);
1242
1243 /* Reg unmap */
1244 REG_UNMAP((void *)ccb_mii_base);
1245 out:
1246 REG_UNMAP((void *)dmu_base);
1247 }
1248
1249 static int __init soc_pcie_init(void)
1250 {
1251 unsigned int i;
1252 int allow_gen2, linkfail;
1253
1254 hndpci_init(sih);
1255
1256 /* Scan the SB bus */
1257 printk(KERN_INFO "PCI: scanning bus %x\n", 0);
1258 pci_scan_bus(0, &pcibios_ops, &soc_pcie_ports[0].hw_pci);
1259
1260 bcm5301x_3rd_pcie_init();
1261 for (i = 1; i < ARRAY_SIZE(soc_pcie_ports); i++) {
1262 struct soc_pcie_port *port = &soc_pcie_ports[i];
1263
1264 /* Check if this port needs to be enabled */
1265 if (!port->enable)
1266 continue;
1267
1268 /* Setup PCIe controller registers */
1269 BUG_ON(request_resource(&iomem_resource, port->regs_res));
1270 port->reg_base =
1271 ioremap(port->regs_res->start,
1272 resource_size(port->regs_res));
1273 BUG_ON(IS_ERR_OR_NULL(port->reg_base));
1274
1275 for (allow_gen2 = 0; allow_gen2 <= 1; allow_gen2++) {
1276 soc_pcie_hw_init(port);
1277 soc_pcie_map_init(port);
1278
1279 /*
1280 * Skip inactive ports -
1281 * will need to change this for hot-plugging
1282 */
1283 linkfail = soc_pcie_check_link(port, allow_gen2);
1284 if (linkfail)
1285 break;
1286
1287 soc_pcie_bridge_init(port);
1288
1289 if (allow_gen2 == 0) {
1290 if (allow_gen2_rc(port) == 0)
1291 break;
1292 pr_info("PCIE%d switching to GEN2\n", port->hw_pci.domain);
1293 }
1294 }
1295
1296 if (linkfail)
1297 continue;
1298
1299 /* Announce this port to ARM/PCI common code */
1300 pci_common_init(&port->hw_pci);
1301
1302 /* Setup virtual-wire interrupts */
1303 __raw_writel(0xf, port->reg_base + SOC_PCIE_SYS_RC_INTX_EN);
1304
1305 /* Enable memory and bus master */
1306 __raw_writel(0x6, port->reg_base + SOC_PCIE_HDR_OFF + 4);
1307 }
1308
1309 return 0;
1310 }
1311
1312 device_initcall(soc_pcie_init);
1313
1314 #endif /* CONFIG_PCI */
Tomato firmware and modifications.